Boost voltage generating circuit including additional pump circuit and boost voltage generating method thereof

This application claims the benefit of Korean Patent Application No. 10-2005-0016260, filed on Feb. 26, 2005, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

1. Field of the Invention

This disclosure relates to a semiconductor device, and more particularly, to a boost voltage generating circuit and method of a semiconductor device.

2. Description of the Related Art

Semiconductor devices, particularly semiconductor memory devices, often use a boost voltage generating circuit for receiving a power supply voltage from an external source and generating a boost voltage VPP higher than the power supply voltage. Generally, the boost voltage generating circuit is referred to as a VPP pump.

FIG. 1 is a circuit diagram illustrating a conventional boost voltage generating circuit, and FIG. 2 is a circuit diagram illustrating a VPP level shifter shown in FIG. 1 . FIG. 3 is a timing diagram illustrating the normal operation of the conventional boost voltage generating circuit shown in FIG. 1 . And FIG. 4 is a timing diagram illustrating the power-up operation of the conventional boost voltage generating circuit shown in FIG. 1 .

Referring to FIG. 1 , the conventional boost voltage generating circuit includes unit pump circuits 11 and 13 , an output control transistor N 12 , and an output controlling circuit 15 . The conventional boost voltage generating circuit may include two or more unit pump circuits.

The unit pump circuit 11 boosts the voltage of a boost node BST 0 in response to a control signal P 1 , and transfers charge from the boost node BST 0 to a boost node BST 1 of the unit pump circuit 13 through a transfer transistor NT 0 . The unit pump circuit 13 boosts the voltage of the boost node BST 1 in response to a control signal P 2 , and transfers charge from the boost node BST 1 to an output node VPP through a transfer transistor NT 1 .

The control signals P 1 and P 2 are non-overlapping pulse signals generated by a boost voltage detector (not shown) that detects the voltage of the output node VPP, and a signal VCCHB is a reset pulse signal generated during the power-up operation.

The conventional boost voltage generating circuit operates as follows. Referring to FIG. 4 , if a power supply voltage VCC increases above the threshold voltage of an NMOS transistor during the power-up operation, the NMOS output control transistor N 12 is turned on and thus the voltage of the output node VPP becomes VCC-VTN, obtained by subtracting the threshold voltage VTN of the NMOS transistor from the power supply voltage VCC. If the control signal P 1 is toggled, the voltage of the output node VPP is held in the power supply voltage VCC until the signal VCCHB is setup. If the power supply voltage VCC increases during the power-up operation, the voltage of the output node VPP also increases.

If the voltage of the output node VPP increases above the voltage for operating the VPP level shifter 21 shown in FIG. 1 , charge from the boost node BST 1 is transferred to the output node VPP through the transfer transistor NT 1 , and the voltage of the output node VPP increases above the power supply voltage VCC. If the voltage of the output node VPP reaches a target value, the control signals P 1 and P 2 become low and thus the pumping operations of the pump circuits 11 and 13 are stopped. If the charge of the output node VPP is consumed by the operation of the semiconductor memory device, the pumping operations are performed again. The transistor and the inverter shown by dotted lines in FIG. 1 are the portions to which the VPP level is applied, and use thick oxide in order to ensure reliability.

FIG. 5 is a timing diagram illustrating the normal operation of the conventional boost voltage generating circuit shown in FIG. 1 at a low power supply voltage VCC. FIG. 6 is a timing diagram illustrating the power-up operation of the conventional boost voltage generating circuit at a low power supply voltage VCC as shown in FIG. 1 .

If the power supply voltage VCC of the semiconductor memory device is decreased, the setup voltage of a power-up reset pulse signal VCCHB is also decreased. A transistor using thick oxide has a higher threshold voltage than a transistor using thin oxide. As shown in FIG. 6 , if the setup voltage of the power-up reset pulse signal VCCHB is decreased below the threshold voltage of the PMOS transistor of the VPP level shifter 21 , the boosting operation and the charge transfer operation are not performed well. Thus, the VPP level does not increase above the setup voltage of the power-up reset pulse signal VCCHB.

Also, although the setup voltage of the power-up reset pulse signal VCCHB increases above the threshold voltage of the PMOS transistor of the VPP level shifter 21 ( FIG. 2 ), it takes much time to transfer the charge of the boost node BST 1 to the output node VPP, due to the weak driving power of the transfer transistor NT 1 . The result is that an active cycle time of the semiconductor memory device is long. In some cases, insufficient charge is transferred from the boost node BST 1 to the output node VPP, and thus the performance of the boost voltage generating circuit may severely deteriorate.

An embodiment includes a boost voltage generating circuit of a semiconductor device including a main pump circuit having a transfer transistor, the main pump circuit to boost a voltage of a boost node and to transfer charge from the boost node to an output node through the transfer transistor in response to at least one control signal, and an additional pump circuit configured to boost a voltage of a terminal of the transfer transistor.

Another embodiment includes a method of generating a boost voltage for a semiconductor device including boosting the voltage of a boost node in response to at least one control signal, transferring charge from the boost node to an output node through a transfer transistor, and additionally boosting the voltage of a terminal of the transfer transistor.

The above and other features and advantages of the invention will become more apparent by describing embodiments in detail with reference to the attached drawings in which:

FIG. 1 is a circuit diagram illustrating a conventional boost voltage generating circuit;

FIG. 2 is a circuit diagram illustrating a VPP level shifter shown in FIG. 1 ;

FIG. 3 is a timing diagram illustrating the normal operation of the conventional boost voltage generating circuit shown in FIG. 1 ;

FIG. 4 is a timing diagram illustrating the power-up operation of the conventional boost voltage generating circuit shown in FIG. 1 ;

FIG. 5 is a timing diagram illustrating the normal operation of the conventional boost voltage generating circuit shown in FIG. 1 at a low power supply voltage VCC;

FIG. 6 is a timing diagram illustrating the power-up operation of the conventional boost voltage generating circuit shown in FIG. 1 at a low power supply voltage VCC;

FIG. 7 is a circuit diagram illustrating a boost voltage generating circuit according to an embodiment;

FIG. 8 is a timing diagram illustrating the normal operation of the boost voltage generating circuit shown in FIG. 7 ;

FIG. 9 is a timing diagram illustrating the power-up operation of the boost voltage generating circuit shown in FIG. 7 ; and

FIG. 10 is a circuit diagram illustrating a boost voltage generating circuit according to another embodiment.

The attached drawings illustrate embodiments of the invention, and are referred to in order to provide a sufficient understanding of the invention, the merits thereof, and the objectives accomplished by the implementation of the embodiments.

Hereinafter, embodiments will be described in detail with reference to the attached drawings. Like reference numerals denote like elements in the drawings.

FIG. 7 is a circuit diagram illustrating a boost voltage generating circuit according to an embodiment.

The boost voltage generating circuit includes unit pump circuits 71 and 73 , an output control transistor N 70 and an additional pump circuit 75 .

The unit pump circuit 71 boosts the voltage of a boost node BST 0 in response to a control signal P 1 , and transfers charge from the boost node BST 0 to a boost node BST 1 of the unit pump circuit 73 through a transfer transistor NT 70 . The unit pump circuit 73 boosts the voltage of the boost node BST 1 in response to a control signal P 2 , and transfers charge from the boost node BST 1 to an output node VPP through a transfer transistor NT 71 . The control signals P 1 and P 2 may be non-overlapping pulse signals generated by a boost voltage detector (not shown) for detecting the voltage of the output node VPP. The unit pump circuit 71 includes delay units D 71 and D 72 , a NOR gate NR 71 , a NAND gate ND 71 , inverters I 71 and I 72 , capacitors C 71 through C 73 , NMOS transistors N 71 through N 76 and an NMOS transfer transistor NT 70 . The unit pump circuit 73 includes delay units D 73 and D 74 , a NOR gate NR 72 , NAND gates ND 72 and ND 73 , inverters I 73 through I 75 , capacitors C 74 through C 76 , a VPP level shifter L 71 , NMOS transistors N 77 through N 82 and an NMOS transfer transistor NT 71 .

The output control transistor N 70 is an NMOS transistor. The output control transistor N 70 is turned on if a power supply voltage VCC increases above the threshold voltage of the NMOS transistor during the power-up operation, and thus the voltage of the output node VPP is pulled to VCC-VTN, the power supply voltage VCC reduced by the threshold voltage VTN of the NMOS transistor.

The additional pump circuit 75 is coupled to the gate of the transfer transistor NT 71 in the unit pump circuit 73 , and additionally boosts the voltage of the gate TG 0 of the transfer transistor NT 71 in response to the signals r 0 and d 0 generated by the control signal P 1 . The additional pump circuit 75 includes inverters I 76 and I 77 , capacitors C 77 and C 78 , NMOS transistors N 83 through N 86 , and an NMOS transfer transistor NT 72 .

Since the detailed structures of the pump circuits 71 , 73 , and 75 are well known to those of ordinary skill in the art, the descriptions will be omitted. It is apparent that the unit pump circuits 71 and 73 may be of various types. Also, although the boost voltage generating circuit according to this embodiment includes the two unit pump circuits in FIG. 7 , other embodiments may include three or more unit pump circuits. The transistor NT 71 , and the inverter I 75 and capacitor C 76 shown by dotted lines in FIG. 7 are the portions to which the VPP level is applied, and use thick oxide in order to ensure reliability.

FIG. 8 is a timing diagram illustrating the normal operation of the boost voltage generating circuit shown in FIG. 7 . FIG. 9 is a timing diagram illustrating the power-up operation of the boost voltage generating circuit shown in FIG. 7 . Referring to FIGS. 8 and 9 , the operation of the boost voltage generating circuit according to an embodiment will now be described in detail.

In the conventional boost voltage generating circuit shown in FIG. 1 , when the VPP level shifter 21 does not operate at a low power supply voltage VCC, the voltage of the gate TG 0 of the transfer transistor NT 1 is held at the power supply voltage VCC, as shown in FIG. 3 . Accordingly, although the voltage of the boost node BST 1 is boosted to 2.5*VCC by the control signals P 1 and P 2 , insufficient charge is transferred through the transfer transistor NT 1 , and thus the voltage of the output node VPP does not increase above VCC-VT.

However, in the boost voltage generating circuit shown in FIG. 7 , the additional pump circuit 75 boosts the voltage of the gate TG 0 of the transfer transistor NT 71 even though the VPP level shifter L 71 does not operate at the low power supply voltage VCC. Accordingly, the voltage of the gate TG 0 increases to 1.5*VCC, as shown in FIG. 9 . As a result, the voltage of the output node VPP can increase to 1.5*VCC-VT. Here, VT denotes the threshold voltage of the NMOS transfer transistor NT 71 .

During normal operation, the voltage between the gate and the source Vgs of the transfer transistor NT 1 is VCC in the conventional circuit shown in FIG. 1 , but is 1.5*VCC in the embodiment shown in FIG. 7 when transferring charge. Accordingly, as shown in FIG. 8 , the driving power of the transfer transistor NT 71 increases when transferring charge, thus reducing the time required for transferring charge from the boost node BST 1 to the output node VPP. Thereby, an active cycle time of the semiconductor memory device can be reduced.

FIG. 10 is a circuit diagram illustrating a boost voltage generating circuit according to another embodiment.

The boost voltage generating circuit according to another embodiment includes two unit pump circuits 101 and 103 , an output control transistor N 100 and an additional pump circuit 105 .

This embodiment is different from the embodiment shown in FIG. 7 in that the additional pump circuit 105 is coupled to an output node VPP and additionally boosts the voltage of the output node VPP. The additional pump circuit 105 additionally boosts the voltage of the output node VPP in response to a control signal P 1 , a power-up reset signal VCCH generated during a power-up operation, and a pulse signal PWCBR generated when setting a mode register set (MRS) of the semiconductor memory device.

The additional pump circuit 105 and the unit pump circuits 101 and 103 have substantially the same structure as the additional pump circuit 75 and the unit pump circuits 71 and 73 shown in FIG. 7 . The additional pump circuit 105 includes a NOR gate NR 103 , NAND gates ND 105 and ND 106 , inverters I 106 through I 111 , capacitors C 107 through C 109 , a PMOS transistor P 101 , NMOS transistors N 113 through N 120 , and an NMOS transfer transistor NT 102 .

The unit pump circuit 101 includes delay units D 101 and D 102 , a NOR gate NR 101 , a NAND gate ND 101 , inverters I 101 and I 102 , capacitors C 101 through C 103 , a VPP level shifter L 101 , NMOS transistors N 101 through N 106 , and an NMOS transfer transistor NT 100 . The unit pump circuit 103 includes delay units D 103 and D 104 , a NOR gate NR 102 , NAND gates ND 102 and ND 103 , inverters I 103 through I 105 , capacitors C 104 through C 106 , a VPP level shifter L 102 , NMOS transistors N 107 through N 112 , and NMOS transfer transistor NT 1 O 1 .

The output control transistor N 100 is equivalent to the output control transistor N 70 shown in FIG. 7 . The transistors NT 100 , NT 101 , the inverters I 102 , I 105 and capacitors C 103 , C 106 shown by dotted lines in FIG. 10 are the portions to which the VPP level is applied, and may use thick oxide in order to ensure reliability.

In the boost voltage generating circuit shown in FIG. 10 , the voltage of the output node VPP is increased to 2*VCC by the additional pump circuit 105 , even though the VPP level shifter L 102 does not operate during the power-up operation. Thereafter, if the voltage of the output node VPP increases above the voltage for operating the VPP level shifter L 102 , the main pump circuits 101 and 103 may operate.

If the voltage of the output node VPP increases to above 2*VCC, the additional pump circuit 105 need not operate. Accordingly, in the embodiment of FIG. 10 , if the power-up reset signal VCCH is set to “HIGH” and the pulse signal PWCBR generated when setting the MRS is set to “HIGH,” the additional pump circuit 105 is disabled.

As mentioned above, according to the boost voltage generating circuit and method, a boost voltage VPP can increase above the setup voltage of the power-up reset pulse signal VCCHB even when the power supply voltage VCC is low, and thus the charge of the boost node BST 1 can be rapidly transferred to the output node VPP.

While embodiments have been particularly shown and described with reference to the drawings, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the following claims.