Apparatus and method for charge pump control with adjustable series resistance

The invention is related to charge pumps, and in particular, to an apparatus and method for a charge pump in which the voltage is regulated by employing an adjustable resistance circuit that is connected in series with the switches and driven by an error amplifier.

A charge pump typically employs switched capacitor(s) for voltage conversion. For example, a voltage doubler type charge pump typically operates as follows. During a first phase, a flying capacitor is switched to sample a voltage, e.g., the voltage between the power supplies. During a second phase, the flying capacitor is switched so that the bottom terminal of the flying capacitor is coupled to the power supply voltage, and the top terminal is connected to the output capacitor. Accordingly, the voltage doubler provides an output voltage that is greater than the supply voltage.

Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following drawings, in which:

FIG. 1 shows a block diagram of an embodiment of a charge pump circuit;

FIG. 2A illustrates a timing diagram of a waveform for phase φ 1 for an embodiment the charge pump circuit of FIG. 1 ;

FIG. 2B illustrates a timing diagram of a waveform for phase φ 2 for an embodiment the charge pump circuit of FIG. 1 ;

FIG. 3 shows a block diagram of an embodiment of the charge pump circuit of FIG. 1 in which load current is regulated;

FIG. 4 illustrates a block diagram of an embodiment of a portion of an embodiment of the charge pump circuit of FIG. 1 in which a voltage doubler architecture is employed;

FIG. 5 shows a block diagram of an embodiment of a portion of an embodiment of the charge pump circuit of FIG. 1 during phase φ 1 in which a voltage doubler architecture is employed;

FIG. 6 shows a block diagram of an embodiment of the charge pump circuit of FIG. 1 in which a voltage doubler architecture is employed;

FIG. 7 illustrates a block diagram of an embodiment of the charge pump circuit of FIG. 1 in which a negative charge pump architecture is employed;

FIG. 8 shows a block diagram of an embodiment of the charge pump circuit of FIG. 1 in which a voltage tripler architecture is employed;

FIG. 9 illustrates a block diagram of an embodiment of the charge pump circuit of FIG. 8 during phase φ 2 ; and

FIG. 10 shows a block diagram of an embodiment of the charge pump circuit of FIG. 8 , arranged in accordance with aspects of the invention.

Various embodiments of the present invention will be described in detail with reference to the drawings, where like reference numerals represent like parts and assemblies throughout the several views. Reference to various embodiments does not limit the scope of the invention, which is limited only by the scope of the claims attached hereto. Additionally, any examples set forth in this specification are not intended to be limiting and merely set forth some of the many possible embodiments for the claimed invention.

Throughout the specification and claims, the following terms take at least the meanings explicitly associated herein, unless the context dictates otherwise. The meanings identified below do not necessarily limit the terms, but merely provide illustrative examples for the terms. The meaning of “a,” “an,” and “the” includes plural reference, and the meaning of “in” includes “in” and “on.” The phrase “in one embodiment,” as used herein does not necessarily refer to the same embodiment, although it may. The term “coupled” means at least either a direct electrical connection between the items connected, or an indirect connection through one or more passive or active intermediary devices. The term “circuit” means at least either a single component or a multiplicity of components, either active and/or passive, that are coupled together to provide a desired function. The term “signal” means at least one current, voltage, charge, temperature, data, or other signal. Where either a field effect transistor (FET) or a bipolar transistor may be employed as an embodiment of a transistor, the scope of the words “gate”, “drain”, and “source” includes “base”, “collector”, and “emitter”, respectively, and vice versa.

Briefly stated, the invention is related to a charge pump that may include an oscillator, a first switch, a second switch, a capacitor/switch network, an error amplifier, an adjustable resistance circuit, a first switch driver, and a second switch driver. In one embodiment, the first and second drivers each receive the oscillator voltage, and drive the first and second switches, respectively. Further, the adjustable resistance circuit is connected in series with the first and second switch circuits. The charge pump is arranged in a closed loop with the error amplifier driving the adjustable resistance circuit. The resistance of the adjustable resistance circuit is modulated to regulate the output voltage.

FIG. 1 shows a block diagram of an embodiment of charge pump circuit 100 . Charge pump circuit 100 may include error amplifier 120 , adjustable resistance circuit Radj, switch circuit S 1 , switch circuit S 2 , capacitor/switch network 110 , output capacitor Cout, resistor R 1 , resistor R 2 , and load 130 .

In operation, charge pump circuit 100 provides output voltage Vout at node N 1 . Resistors R 1 and R 2 may operate as a voltage divider to provide feedback signal FB at node N 2 responsive to output voltage Vout. Further, error amplifier 120 is operable to provide an error signal ERR at node N 4 responsive to signal FB and reference signal REF (received at node N 3 ). Adjustable resistance circuit Radj has a resistance that is modulated based on signal ERR.

The switch circuits—including switch circuit S 1 , S 2 , and switch circuits in capacitor/switch network 110 —open and close according to at least two phases, phase φ 1 and phase φ 2 . Also, capacitor/switch network 110 includes a flying capacitor (not shown in FIG. 1 ). The switch circuits are arranged and controlled such that, in phase φ 2 , the flying capacitor is coupled in series with adjustable resistance circuit Radj, and such that the series combination of the flying capacitor and adjustable resistance circuit Radj is coupled between node N 7 and node N 5 . In one embodiment, node N 7 is a high power supply voltage node for receiving supply voltage VDD and node N 5 is a low power supply node connected to ground (or VSS). The supply voltage is interchangeably referred to as VDD or Vs in this document.

During phase φ 2 , the flying capacitor samples a voltage that is approximately given by: the voltage between nodes N 7 and N 5 , minus the voltage drop across adjustable resistance circuit Radj. During phase φ 1 , the switch circuits are controlled so that charge is transferred from the flying capacitor to output capacitor Cout, or vice versa, for providing output voltage Vout. Phase φ 1 acts as a hold phase and phase φ 2 acts as a sample phase. The arrangement that occurs in phase φ 1 may be different in various embodiments, as described in greater detail below. During phase φ 2 , the flying capacitor is not supplying charge to output node N 1 , but output capacitor Cout causes the voltage at node N 1 to be maintained at the substantially the same level as it was at the end of the last phase φ 1 .

Charge pump circuit 100 operates to regulate output voltage Vout by modulating adjustable resistance circuit Radj. If output voltage Vout is less than the steady-state value, the resistance of adjustable resistance circuit Radj is decreased, which in turn increases the flying capacitor voltage. Conversely, if output voltage Vout is greater than the steady-state value, the resistance of adjustable resistance circuit Radj is increased, which in turn decreases the flying capacitor voltage.

In one embodiment, error amplifier 120 , switch circuit S 1 , switch circuit S 2 , and adjustable resistance circuit Radj are all included on an integrated circuit, while resistor R 1 , resistor R 2 , load 130 , and capacitor/switch network 110 are external to the integrated circuit. In another embodiment, the switch circuits in capacitor/switch network 110 are on-chip and the flying capacitor is off-chip.

In one embodiment, error amplifier 120 is an operational amplifier with built-in loop compensation. In another embodiment, error amplifier 120 is a simple gm amplifier. In this embodiment, compensation can be performed with a simple compensation circuit coupled to node N 4 . Because node N 4 is a high impedance node, it is suitable for loop compensation.

FIGS. 2A and 2B illustrate timing diagrams of waveforms for phases φ 1 and φ 2 respectively for an embodiment charge pump circuit 100 of FIG. 1 . As shown in FIG. 2A , during phase φ 1 , switch circuit S 1 is on and switch circuit S 2 is off. As shown in FIG. 2B , during phase φ 2 , switch circuit S 2 is on and switch circuit S 1 is off. As shown, phases φ 1 and φ 2 may be provided employing two signals out of phase with each other operating at 50% duty cycle, provided by an oscillator or the like. In another embodiment, one signal is used for controlling phase φ 1 and phase φ 2 for each of the switch circuits.

Although FIG. 1 shows one arrangement for an embodiment of charge pump circuit 100 , other circuits may be arranged in a different manner. For example, in one embodiment, adjustable resistance circuit Radj may be placed in a different location than shown in FIG. 1 , having a different arrangement than the one illustrated in FIG. 1 in which adjustable resistance circuit Radj is also coupled in series with the flying capacitor during the sampling phase. For example, in other embodiments, the position of switch circuit S 2 and adjustable resistance circuit Radj may be reversed, adjustable resistance circuit Radj may be placed next to a high-side switch rather than a low-side switch, or the like.

As another example, although charge pump circuit 100 illustrates an embodiment in which charge pump 100 is used for voltage regulation, in other embodiments, a current may be regulated rather than a voltage.

For example, FIG. 3 shows a block diagram of an embodiment of charge pump circuit 300 , which is an embodiment of charge pump circuit 100 of FIG. 1 in which load voltage Iload is regulated. Charge pump circuit 300 further includes resistor R 3 and load 331 . In one embodiment, load 331 is a string of white LEDs coupled in series.

Also, virtually any type of charge pump arrangement may be employed within the scope and spirit of the invention. As one example, a voltage doubler type architecture may be used to provide a regulated output voltage Vout that is between 1x and 2x, where x represents the voltage at node N 7 minus the voltage at node N 5 .

FIG. 4 illustrates a block diagram of portion 405 of an embodiment of charge pump 100 in which a voltage doubler architecture is employed. Capacitor/switch network 410 includes switch circuit S 3 , switch circuit S 4 , and flying capacitor Cp. Flying capacitor Cp is coupled between first flying capacitor node N 6 and second flying capacitor node N 8 . Switch circuit S 3 is closed during phase φ 2 and open during phase φ 1 . Conversely, switch circuit S 4 is open during phase φ 2 and closed during phase φ 1 .

As shown in FIG. 4 , during phase φ 2 , flying capacitor Cp and adjustable resistance circuit Radj are couples in series, and the series combination of flying capacitor Cp and adjustable resistance circuit Radj are coupled between node N 7 and node N 5 .

FIG. 5 shows a block diagram of an embodiment of capacitor/switch network 510 during phase φ 1 . Capacitor/switch network 510 is an embodiment of capacitor/switch network 410 of FIG. 4 . As shown, during phase φ 1 , the bottom plate of flying capacitor Cp is coupled to supply voltage Vs, and the top plate of capacitor Cp is coupled to node N 1 to provide output voltage Vout.

FIG. 6 shows a block diagram of an embodiment of charge pump circuit 100 of FIG. 1 in which an embodiment of a voltage doubler architecture is employed as described with regard to FIG. 4 and FIG. 5 as discussed above. Charge pump circuit 600 further includes oscillator 640 , driver DRV 1 , and driver DRV 2 . Switch circuit 1 includes transistor M 1 . Similarly, switch circuit S 2 includes transistor M 2 . Adjustable resistance circuit Radj includes transistor M 3 . Switch circuit S 3 includes diode D 1 . Further, switch circuit S 4 includes diode D 2 .

Although particular embodiments of switch circuits are shown in FIG. 6 , any of the switch circuits may be implemented by a different type of switch within the scope and spirit of the invention. For example, although field effect transistors are used for switches S 1 and S 2 , in other embodiments, bipolar transistors or the like may be used instead. Similarly, although diodes are used for switch circuits S 3 and S 4 , in other embodiments, one or more of the diodes may be replaced with a transistor switch, or the like.

Similarly, although adjustable resistance circuit Radj is implemented with a field effect transistor in the embodiment illustrated in FIG. 6 , in other embodiment, transistor M 3 may be replaced with a bipolar transistor or another circuit capable of providing a variable resistance based on signal ERR.

Similarly, although FIG. 6 illustrates an embodiment in which transistors M 2 and M 3 are n-type transistors, and transistor M 1 is a p-type transistor, in other embodiments, other types of transistor may be employed. For example, in one embodiment, transistor M 3 is a p-type transistor, and reference signal REF is referenced to supply voltage Vs rather than ground. These variations and others are within the scope and spirit of the invention.

FIG. 7 illustrates a block diagram of an embodiment of charge pump circuit 700 , in which a negative charge pump architecture is employed. Charge pump circuit 700 further includes reference circuit REF 2 . Capacitor/switch network circuit 710 includes flying capacitor Cp, switch circuit S 4 , and switch circuit S 8 . Switch circuit S 4 includes diode D 2 . Similarly, Switch circuit S 8 includes diode D 3 .

In operation, charge pump circuit 700 may be used to provide a regulated output voltage Vout that is between −1x and 0. During phase φ 2 , charge pump circuit 700 operates in a similar manner as a voltage doubler architecture. However, during phase φ 1 , the top plate of flying capacitor Cp is coupled to ground and the bottom plate of flying capacitor Cp is coupled to output node N 1 .

FIG. 8 shows a block diagram of an embodiment of charge pump circuit of 800 , in which a voltage tripler architecture is employed. Capacitor/switch network 810 includes flying capacitor Cp 1 , flying capacitor Cp 2 , switch circuit S 3 , switch circuit S 4 , switch circuit S 5 , switch circuit S 6 , and switch circuit S 7 . Flying capacitor Cp 1 is coupled between first flying capacitor node N 6 and second flying capacitor node N 8 . Further, flying capacitor Cp 2 is coupled between third flying capacitor node N 9 and fourth flying capacitor node N 10 .

During phase φ 1 , switch circuits S 1 , S 4 , and S 7 are closed, and switch circuits S 2 , S 3 , S 5 , and S 6 are open. Conversely, during phase φ 2 , switch circuits S 1 , S 4 , and S 7 are open, and switch circuits S 2 , S 3 , S 5 , and S 6 are closed. Charge pump circuit 800 may be used to provide a regulated output voltage Vout that is between 1x and 3x.

In one embodiment, as shown in FIG. 8 , resistor Radj is employed to modulate the voltage across both flying capacitor Cp 1 and flying capacitor Cp 2 during phase φ 2 . In this embodiment, resistor Radj is used to modulate the voltage on both flying capacitors with only one control loop, simplifying the design and allows simple building blocks along with a minimum amount of die space.

FIG. 9 illustrates a block diagram of an embodiment of charge pump circuit 900 during phase φ 2 . Charge pump circuit 900 is an embodiment of charge pump circuit 800 of FIG. 8 . As shown, during phase φ 2 , flying capacitors Cp 1 and Cp 2 are coupled in parallel between node N 6 and node N 7 , and adjustable resistance circuit Radj is coupled in series with the parallel combination of the flying capacitors. The voltage Vcp 1 across flying capacitor Cp 1 , and voltage Vcp 2 across flying capacitor Cp 2 , are both modulated based on the resistance of adjustable resistance circuit Radj. Voltages Vcp 1 and Vcp 2 may be approximately the same; however, there may be some difference due to on-resistance mismatch of the switches. During phase φ 1 , charge pump circuit 900 provides a voltage of Vs+Vcp 1 +Vcp 2 to output node N 1 .

FIG. 10 shows a block diagram of an embodiment of charge pump circuit 1000 , which may be employed as an embodiment of charge pump circuit 800 of FIG. 8 . Charge pump circuit 1000 further includes driver DRV 3 , resistor R 3 , and capacitor C 3 . Switch circuit S 5 includes transistor M 4 . Switch circuit S 4 includes transistors M 5 and M 6 . Switch circuit S 6 includes diode D 4 . Similarly, switch circuit S 7 includes diode D 5 .

Also, resistor R 3 and capacitor C 3 form a simple compensation network as discussed above.

Although one embodiment charge pump circuit 1000 is illustrated in FIG. 10 , many variations are within the scope and spirit of the inventions, such as the variations discussed above, and others. In one embodiment, instead of placing flying capacitors Cp 1 and Cp 2 in parallel during phase φ 2 , two different variable resistance circuits may be used, each coupled in series with a separate one of the two flying capacitors during phase φ 2 . In this example, either one or two error amplifiers may be used.

Further, many different embodiments with different gains are within the scope and spirit of the invention. For example, the 3x architecture shown in FIGS. 8-10 may be expanded resulting in a 4x architecture, a 5x architecture, and so on. Also, a negative charge pump architecture may be employed resulting in a −2x architecture, a −3x architecture, and so on. These variations and others are within the scope and spirit of the invention.

The above specification, examples and data provide a description of the manufacture and use of the composition of the invention. Since many embodiments of the invention can be made without departing from the spirit and scope of the invention, the invention also resides in the claims hereinafter appended.