Pulse frequency modulated voltage regulator with linear regulator control

This invention relates to voltage regulators and, in particular, to pulse-frequency-modulated (PFM) switching-type voltage regulators.

Switching regulators and linear regulators are well known types of voltage regulators for converting an unregulated voltage, such as a battery voltage, to a regulated DC output voltage of a desired value.

Linear regulators, also referred to as low dropout (LDO) regulators, include a control circuit and a linear switch (transistor) that is connected between the unregulated power supply and an output terminal. The control circuit monitors the regulated DC output voltage at the output terminal by way of a feedback signal, and controls the gate voltage of the linear switch such that the switch's conductance is adjusted to produce the desired DC output voltage level.

Switching regulators include a switch (transistor) and an inductor connected in series between the unregulated voltage and the output terminal, a filter capacitor, and an oscillator-based control circuit. The oscillator-based control circuit provides a time-varying control signal to the gate terminal of the switch, whereby the switch is turned on to pass the unregulated voltage to the inductor in short pulses. These pulses cause the inductor to store energy in its magnetic field, which produces the regulated DC output voltage. The filter capacitor serves to smooth and maintain the regulated DC output voltage between pulses. The regulated DC output voltage is fed back to an oscillator-based control circuit, which compares the feedback voltage with a reference voltage, and controls the oscillator output such that the switch duty cycle produces the desired regulated DC output voltage.

Switching regulators can generally be classified by the type of oscillator control as either pulse-width-modulated (PWM) or pulse-frequency-modulated (PFM) regulators. PWM regulators include an oscillator control circuit that produces a pulse train having a fixed frequency and a variable pulse width. PFM regulators, on the other hand, use oscillator control circuits that produce a fixed pulse width and a variable pulse frequency. In either case, the duty cycle of the transistor is controlled by the feedback voltage such that the regulated output voltage maintains the desired voltage level. Switching regulators are also characterized by whether they convert the unregulated voltage upward (boost or step-up configuration), convert the unregulated voltage downward (buck or step-down configuration), or invert the unregulated voltage (buck-boost or inverting configuration).

Switching regulators are generally considered to be more efficient than linear regulators, but are generally much noisier during operation. A linear regulator provides a very smooth output voltage because the linear switch is always partially on (conducting), but wastes power due to the large voltage differential across the linear switch. In contrast, the switching regulator transistor is either fully on or fully off. When a switching regulator transistor is fully on, such as in saturation or near the edge of saturation, the transistor is a highly efficient switch, and there is a minimum of wasted power through the switch. However, when load conditions suddenly increase, unlike linear voltage regulators that instantaneously adjust to the increased current demand, switching-type regulators can experience delays because the current through the inductor cannot change instantaneously with time. In addition, the control system around the switching regulator requires a longer time than a linear system to adjust the duty cycle to current-load the inductor properly.

What is needed is a voltage regulator circuit that combines the smooth, quickly responding output voltage of a linear voltage regulator and the high efficiency of a switching-type voltage regulator.

The present invention is directed to a voltage regulator circuit that utilizes a linear regulator circuit that is activated only when the regulated output voltage falls to a predetermined minimum target voltage level, and a pulse control circuit that detects activation of the linear regulator circuit, and refreshes the regulated output voltage to a predetermined maximum target voltage level each time the regulated output voltage reaches the minimum target voltage. By allowing output current to flow in the linear regulator circuit only when the regulated output voltage reaches the minimum target voltage level, and by designing the linear regulator circuit to naturally eliminate its output current each time the regulated output voltage is boosted by the pulse control circuit, the voltage regulator circuit of the present invention successfully combines the fast transient characteristics of conventional linear regulators with the high efficiency characteristics of a switching-type voltage regulator.

In accordance with an embodiment of the present invention, the voltage regulator circuit includes a first transistor connected in series with an inductor between an unregulated input voltage and the regulated output voltage and is controlled by the pulse control circuit, and the linear regulator circuit including a second transistor that is connected in parallel with the first transistor and inductor. The linear regulator circuit also includes a linear control circuit that generates a linear control voltage, which is on continuously, but serves to regulate the output of the second transistor each time the regulated output voltage falls to the predetermined minimum target voltage. The linear control voltage controls the second transistor to provide sufficient current to maintain the regulated output voltage at the predetermined minimum target voltage until the pulse control circuit activates the first transistor. In addition, the pulse control circuit includes a sensor for detecting a current through the second transistor, and transmits a pulse signal to the first transistor in response to the detected current. The pulse signal fully turns on the first transistor for a predetermined duration (time period), thereby causing a ramp in inductor current that raises the regulated output voltage. The amount of voltage increase is proportional to a difference between the input and output voltages (V IN −V OUT ), the inductance, the time the first switch is held on, and the amount of inductor current. At the end of the predetermined duration, the pulse signal is de-asserted, which turns off the first transistor. The output voltage, stored on a capacitor, thus begins to fall in response to the applied load. When the output voltage again falls to the predetermined minimum target voltage level, the cycle is repeated. In this way, the efficiency of the voltage regulator circuit is dramatically increased over conventional linear regulators due to the relatively short time load current is passed through the second transistor, thus avoiding the high losses associated with linear regulators, and even approaching efficiencies associated with “pure” switching voltage regulators. That is, the only time that the linear regulator circuit conducts load current through the first transistor is during the delay period between detection of current through the second transistor and assertion of the pulse signal and subsequent enabling of the first transistor, which makes up a relatively small amount of the operating time, particularly when the applied load draws a relatively small current. Further, the voltage regulator circuit avoids the noise problems associated with “pure” switching type voltage regulators because the linear voltage circuit provides the required load current during the delay period between detection of current through the second transistor and the assertion of the pulse signal and subsequent enabling of the first transistor.

These and other features, aspects and advantages of the present invention will become better understood with regard to the following description, appended claims, and accompanying drawings, where:

FIG. 1 is a simplified diagram showing a generalized voltage regulator circuit according to an embodiment of the present invention;

FIGS. 2(A) , 2 (B), 2 (C) and 2 (D) are timing diagrams showing signals generated during operation of the voltage regulator circuit of FIG. 1 ;

FIG. 3 is a simplified diagram showing a voltage regulator circuit according to a specific embodiment of the present invention; and

FIG. 4 is a simplified diagram showing a voltage regulator circuit according to another specific embodiment of the present invention.

The terms “coupled”, “connected”, “switched”, which are utilized herein, are defined as follows. The term “connected” is used to describe a direct connection between two circuit elements, for example, by way of a metal line formed in accordance with normal integrated circuit fabrication techniques. In contrast, the term “coupled” is used to describe either a direct connection or an indirect connection between two circuit elements. For example, two coupled elements may be directly connected by way of a metal line, or indirectly connected by way of an intervening circuit element (e.g., a capacitor, resistor, inductor, or transistor). The term “switched” is utilized to describe a transistor that has a large gate-to-source voltage (V gs ), and can be represented as a low value resistor.

FIG. 1 is a simplified diagram depicting a voltage regulator circuit 100 for converting an unregulated input voltage V IN received at an input node 101 into a regulated output voltage V OUT provided at an output node 103 . Voltage regulator circuit generally includes a voltage control circuit 110 , a linear regulator circuit 120 , and a pulse-frequency-modulation (PFM) control circuit 130 (also referred to as a pulse control circuit herein). In one embodiment, voltage regulator circuit 100 is a discrete component (i.e., formed on a semiconductor “chip”) that is separate from an applied load (represented by resistor R LOAD ) and or a feedback circuit 140 (represented by feedback resistors R 1 and R 2 ). In this discrete embodiment input node 101 and output node 103 , along with a ground node 105 and an optional feedback node 107 , are connected to device pins or other terminal structures provided on a package structure housing the chip. In other embodiments, voltage regulator circuit 100 may be incorporated into a larger device (e.g., a microprocessor) that is fabricated on a single chip along with the load and feedback circuitry, in which case input node 101 and output node 103 may represent internal nodes of the larger circuit. The following description is intended to cover either of these broader classifications of integrated circuit devices.

Voltage control circuit 110 generally includes a (first) transistor (e.g., a field-effect transistor) 111 , an inductor 113 , a schottky diode 117 (or a switch) and a capacitor 119 that operate in conjunction with PFM control circuit 130 to function in a manner similar to a conventional PFM-type switching regulator (i.e., to generate periodic currents having a predetermined duration between input node 101 and inductor 113 ). Switch 111 and inductor 113 are connected in series by way of a node 112 between input node 101 and output node 103 , with the gate terminal of transistor 111 being coupled to receive a pulse signal V PFM generated by PFM control circuit 130 in the manner described below. Switch 111 is sized and pulse signal V PFM is generated at a level such that transistor 111 is switched whenever pulse signal V PFM is applied to its gate (control) terminal, thereby causing transistor 111 to couple unregulated input voltage V IN to node 112 during the time (duration) that pulse signal V PFM is asserted. Therefore, the voltage difference V IN −V OUT appears across inductor 113 , causing a ramp increase in inductor current to generate an associated increase in voltage on output pin 103 . Capacitor 119 , which is connected between output node 103 and ground node 105 , serves to store the charge provided by inductor 113 during assertions of pulse signal V PFM .

Linear regulator circuit 120 functions in a manner similar to a conventional linear regulator to maintain output node 103 at a predetermined minimum target voltage level, but as is well known in linear systems, only conducts output current I LDO between input node 101 and the output node 103 when regulated output voltage V OUT is equal to or less than the predetermined minimum target voltage level. Linear regulator circuit 120 includes an output (second) transistor 121 that has first and second terminals respectively connected between input node 101 and output node 103 (i.e., in parallel with the current path formed by transistor 111 and inductor 113 ), and a linear (LDO) control circuit 123 that compares a linear reference voltage V REF with a feedback signal V FB , and generates a linear control signal V LDO having a voltage level that is proportional to a difference between linear reference V LDO voltage and feedback signal V FB . Linear reference voltage V REF and feedback signal V FB are generated substantially in accordance with conventional methods. However, in accordance with an aspect of the present invention, transistor 121 is fabricated and linear control signal V LDO , linear reference voltage signal V REF and feedback signal V FB are generated such that transistor 121 conducts current I LDO only when regulated output voltage V OUT is equal to or less than the predetermined minimum target voltage level. That is, while output voltage V OUT is greater than the predetermined minimum target voltage level, linear regulator circuit 120 controls transistor 121 to a non-conductive state. Conversely, while output voltage V OUT is less than or equal to the predetermined minimum target voltage level, linear regulator circuit 120 controls (i.e., linear control signal V LDO is generated at a voltage level that turns on transistor 121 such that a current I LDO flows between input node 101 and output node 103 though transistor 121 ). The amount of current I LDO passed by transistor 121 to output node 103 when voltage regulator circuit 120 is activated (in control) is equal to the difference between the load current and the residual current in inductor 113 .

In accordance with another aspect of the invention, PFM control circuit 130 functions to detect current conduction in linear regulator circuit 120 (i.e., when a non-zero current I LDO is passed through linear regulator circuit 130 ), and to generate pulse signal V PFM while linear regulator circuit 120 is active. In one embodiment, PFM control circuit 130 includes a current sensing circuit 132 that, in effect, senses current I LDO (i.e., the current through transistor 121 ), compares current I LDO with a predetermined minimum reference current I REF , and generates pulse control signal V PC when the current I LDO exceeds a predetermined minimum current I REF . Note that in one embodiment, minimum reference current I REF may be substantially zero Amps (i.e., any detected current triggers generation of pulse control signal V PC ). Pulse control signal V PC is supplied to a pulse generator 137 (e.g., a one-shot circuit) that asserts pulse signal V PFM for a predetermined duration in response to pulse control signal V PC . As mentioned above, pulse signal V PFM is applied to the gate terminal of transistor 111 , and has a predetermined fixed duration that fully turns on transistor 111 to increase the voltage at internal node 112 to essentially unregulated input voltage V IN .

FIGS. 2(A) to 2(D) are timing diagrams depicting exemplary signals generated during operation of voltage regulator 100 . FIG. 2(A) shows an exemplary regulated output voltage V OUT that is generated at output node 103 in response to hypothetical applied loads. FIGS. 2(B) , 2 (C) and 2 (D) show current I LDO through transistor 121 , pulse control signal V PC , and pulse signal V PFM , respectively, that are generated in conjunction with the exemplary regulated output voltage of FIG. 2(A) . In these figures, the time period between time t 0 and time t 6 depicts operation of voltage regulator 100 in response to a relatively light applied load, and the time period between time t 7 and time t 12 depicts operation of voltage regulator 100 in response to a relatively heavy applied load.

Referring to the left side of FIG. 2(A) , a charge generated at output node 103 and stored by capacitor 119 ( FIG. 1 ) and is gradually depleted between time t 0 and t 1 by the relatively light applied load, thus causing regulated output voltage V OUT to gradually decrease toward a predetermined minimum target voltage V T-MIN . As mentioned above, when regulated output voltage V OUT reaches predetermined minimum target voltage V T-MIN (e.g., at time t 1 ; FIG. 2 (A)), feedback signal V FB drops below linear reference voltage signal V REF , causing LDO control circuit 123 to conduct current I LDO through transistor 121 (which is depicted in FIG. 2(B) ). This interrupts the fall of regulated output voltage V OUT at minimum target voltage V T-MIN with minimal noise generation. Using known techniques utilized in conventional linear regulators, linear control signal V LDO is generated at a voltage level such that current I LDO through transistor 121 is equal to the current drawn by the applied load, thereby preventing output node 103 from falling below minimum target voltage V T-MIN . Because current I LDO increases above the predetermined minimum current I REF ( FIG. 2(B) ; shortly after time t 1 ), current sensing circuit 132 asserts pulse control signal V PC (just after time t 1 ; FIG. 2(C) ). After a brief switching delay (DELAY; FIG. 2 (D)), in response to the assertion of pulse control signal V PC , pulse generator 137 asserts pulse signal V PFM (time t 2 ; FIG. 2 (D)), which turns on transistor 111 . Note that the length of the delay period in FIG. 2(D) is arbitrarily selected for illustrative purposes. As described above, the resulting movement of transistor 111 to input voltage V IN is converted to an increasing inductor current by inductor 113 and pulls up output node 103 , causing regulated output voltage V OUT to increase above minimum target voltage V T-MIN (time t 2 ; FIG. 2(A) ). The increase of output voltage V OUT above minimum target voltage V T-MIN is detected by LDO control circuit 123 , which under linear control causes current I LDO to drop below predetermined minimum current I REF (shortly after time t 2 ; FIG. 2(B) ). The assertion of pulse control signal V PC is edge-triggered at the moment the comparator exceeds the minimum threshold (shortly after time t 2 ; FIG. 2(C) ). Referring again to FIG. 2(D) , pulse signal V PFM remains asserted for predetermined duration D, which in the present example maintains regulated output voltage V OUT at the maximum target voltage level V T-MAX . At time t 3 , pulse signal V PFM is de-asserted, and regulated output voltage V OUT again begins to decline from its maximum level.

Similar to conventional PFM-type switching regulators, the frequency at which fixed-duration pulse signal V PFM is generated is determined by the applied load. In the disclosed example, the relatively light applied load causes regulated output voltage V OUT to drop to minimum target voltage V T-MIN at time t 4 (FIG. 2 (A)), causing current I LDO to again flow through transistor 121 (time t 4 ; FIG. 2 (B)), which re-asserts pulse control signal V PC (shortly after time t 4 ; FIG. 2 (C)), which in turn re-asserts pulse control signal V PC (time t 5 ; FIG. 2(D) ). Thus, in response to the relatively light load, pulse signal V PFM is asserted at a relatively low frequency f 1 (shown in FIG. 2(D) ). In contrast, as indicated at the right side of FIGS. 2(A) to 2(D) , a relatively heavy load causes regulated output voltage V OUT to drop to minimum target voltage V T-MIN at a relatively fast rate (e.g., between time t 7 and t 8 and between time t 10 and t 11 in FIG. 2 (A)), which produces current I LDO through transistor 121 ( FIG. 2(B) ) and pulse control signal V PC ( FIG. 2(C) ) in the manner described above, thereby causing assertion of pulse signal V PFM at a relatively high frequency f 2 (measured between assertion times t 9 and t 12 , as shown in FIG. 2(D) ). Note also that, in addition to drawing down regulated output voltage V OUT at a faster rate, the heavy applied load draws a relatively high current I LDO through transistor 121 ( FIG. 2(B) ). Linear regulator circuit 120 adjusts current I LDO to meet the load demand utilizing conventional linear voltage regulator methods.

As illustrated in the above example, the efficiency of voltage regulator circuit 100 is dramatically increased over linear regulators due to the relatively short amount time load current is passed through linear regulator 120 , thus minimizing the high losses associated with linear regulators, and even approaching efficiencies associated with “pure” switching voltage regulators. That is, the only time that linear regulator circuit 120 conducts load current through transistor 121 is during the delay period between detection of current I LDO and assertion of pulse signal V PFM and subsequent enabling of the transistor 111 , which as indicated in FIG. 2(A) makes up a relatively small amount of the operating time, particularly when the loads are light.

In addition, as illustrated in the above example, the voltage regulator circuit 100 avoids the low voltage noise problems associated with “pure” switching type voltage regulators in that linear voltage circuit 120 provides the required load current during the delay period between detection of current I LDO and assertion of pulse signal V PFM and subsequent enabling of the transistor 111 .

FIG. 3 is a simplified diagram depicting a voltage regulator circuit 200 according to a specific embodiment of the present invention. Portions of voltage regulator circuit 200 that are similar to those of voltage regulator circuit 100 are identified with the similar reference numbers (e.g., transistor 121 of voltage regulator circuit 100 is represented by PMOS transistor 221 in voltage regulator circuit 200 ).

The voltage control portion of voltage regulator circuit 200 is characterized by the use of a PMOS transistors 211 and a rectifier circuit 217 in place of schottky diode 117 . PMOS transistor 211 is the preferred transistor due to its low on-resistance. Rectifier circuit 217 is provided to enable synchronous operation. That is, voltage regulator 100 is depicted a non-synchronous configuration. Synchronous configuration is implemented according to known techniques by providing an NMOS transistor (not shown) in rectifier circuit 217 that is controlled using an optional synchronous operation control signal V SYNCH generated by PFM control circuit 230 . During operation, after the time-out period of the one-shot circuit and PFM control circuit 230 shuts off PMOS transistor 211 , instead of the resulting current circulating through schottky diode 117 , the current is circulated through the NMOS transistor, which is activated by PFM control circuit 230 according to known techniques.

Linear regulator circuit 220 is also characterized by the use of a PMOS transistor 221 , and a comparator 223 is utilized to generate linear control signal V LDO according to the methods described above.

PFM control circuit 230 includes a current sensing circuit 232 and a pulse generator 237 that operate substantially as described above. Current sensing circuit 232 includes a resistive sensor 233 , a current comparator 234 , and a (third) PMOS transistor 235 . PMOS transistor 235 is connected in parallel with PMOS transistor 221 between input node 201 and output node 203 , and is controlled by linear control signal V LDO . Resistive sensor 233 generates a current detection signal V I-LDO when linear control signal V LDO is generated to produce current I LDO through PMOS transistors 221 and 235 . Comparator 234 compares current detection signal V I-LDO with a predetermined reference signal V I--REF , and generates pulse control signal V PC when current detection signal V I-LDO is greater than predetermined reference signal V I--REF Pulse control signal V PC is applied to a one-shot circuit 238 provided in pulse generator 237 , which generates pulse signal V PFM for a preset time period (the predetermined duration) in response to pulse control signal V PC .

The above embodiments depicted a non-synchronous configuration. In another embodiment a synchronous configuration is implemented according to known techniques in which diode circuit 217 includes an NMOS transistor (not shown) that is controlled by PFM control circuit 230 . After the time-out period of the one-shot circuit and PFM control circuit 230 shuts off PMOS transistor 211 , instead of the resulting current circulating through schottky diode 117 , the current is circulated through the NMOS transistor, which is activated by PFM control circuit 230 according to known techniques.

FIG. 4 is a simplified diagram depicting a voltage regulator circuit 300 according to another embodiment of the present invention. Portions of voltage regulator circuit 300 that are identical to voltage regulator circuit 200 are identified with the same reference numbers. Voltage regulator circuit 300 differs from voltage regulator circuit 200 in that it includes a pulse-width-modulating (PWM) control circuit 360 and a pulse signal selection circuit 370 . PWM control circuit 360 generates a pulse-width modulated control signal V PWM according to known techniques, and pulse signal selection circuit 370 determines the current demands of the applied load (the “applied load condition”), and selectively passes one of the PWM control signal V PWM and the pulse signal V PFM to the gate terminal of transistor 211 in response to the applied load condition. In one embodiment, the pulse signal V PFM is transmitted by pulse signal selection circuit 370 to transistor 211 when current loads are below 100 mA, and PWM control signal V PWM is transmitted by pulse signal selection circuit 370 to transistor 211 when current loads are greater than 100 mA.

Although the present invention has been described with respect to certain specific embodiments, it will be clear to those skilled in the art that the inventive features of the present invention are applicable to other embodiments as well, all of which are intended to fall within the scope of the present invention.