Chain-chopping current mirror and method for stabilizing output currents

This application claims the priority benefit of Taiwan application serial no. 95112969, filed on Apr. 12, 2006. All disclosure of the Taiwan application is incorporated herein by reference.

1. Field of Invention

The present invention relates to a current mirror, and more particularly, to a chain-chopping current mirror and a method for stabilizing output currents.

2. Description of the Related Art

In various application circuits, such as an amplifier, an multi-channel constant current driver and so on, a current mirror is often required as a bias circuit of the above-mentioned circuits. FIG. 1 is a drawing of a conventional current mirror circuit configuration. Referring to FIG. 1 , the current mirror includes five transistors MP 1 ˜MP 5 . The transistor MP 1 produces a bias at the gate thereof according to the input current at an input terminal I 101 . The gates of the transistors MP 2 ˜MP 5 are coupled with the gate of the transistor MP 1 to receive the gate bias of the transistor MP 1 and the transistors MP 2 ˜MP 5 respectively and output a current according to the gate bias and the proportions among the sizes of the transistors MP 2 ˜MP 5 .

For some applications, the above-mentioned channel sizes of the transistors MP 2 ˜MP 5 are equal to each other, which is designed purposely for outputting the same current at every output node (also called ‘current channel’) OUT 1 ˜OUT 4 . However, due to an imperfect IC (integrated circuit) process, a deviation between the real output current at the output nodes OUT 1 ˜OUT 4 and the originally desired current may occurs.

To make the current passing through every current channel equal to each other, a prior art configuration called ‘cross-chopping current mirror’ was provided as shown in FIG. 2 . Referring to FIG. 2 , in the circuit herein, in addition to the transistors MP 1 ˜MP 5 of the original current mirror, two transmission-gates functioning as switches are further disposed between every two adjacent transistors and two adjacent output terminals, i.e. eight transistors in total, SW 1 ˜SW 8 . By using a first clock signal CK and a second clock signal CKB, the transmission-gates SW 1 ˜SW 8 of the circuit are controlled to be turned on or off, wherein the first clock signal CK and the second clock signal CKB are phase-inverted to each other.

When the first clock signal CK takes a logic-high level, the second clock signal CKB takes a logic-low level. At the point, the output node OUT 1 outputs a current passing through the transistor MP 2 , the output node OUT 2 outputs a current passing through the transistor MP 3 , the output node OUT 3 outputs a current passing through the transistor MP 4 and the output node OUT 4 outputs a current passing through the transistor MP 5 . When the first clock signal CK takes a logic-low level, the second clock signal CKB takes a logic-high level. At the point, the output node OUT 1 outputs a current passing through the transistor MP 3 , the output node OUT 2 outputs a current passing through the transistor MP 2 , the output node OUT 3 outputs a current passing through the transistor MP 5 and the output node OUT 4 outputs a current passing through the transistor MP 4 .

Although the above-described cross-chopping current mirror is able to average the currents of the current channel OUT 1 and the current channel OUT 2 and the currents of the current channel OUT 3 and the current channel OUT 4 , respectively, however, output current variations with the above-described design still remain. It is assumed that the desired current of the original design is I; under the process influence, the real output current of the transistor MP 2 is I+a, the real output current of the transistor MP 3 is I+b, the real output current of the transistor MP 4 is I−c and the real output current of the transistor MP 5 is I−d; all of a, b, c and a are larger than zero. By using the scheme of the above-described cross-chopping current mirror, the output current at the output nodes OUT 1 and OUT 2 is I+(a+b)/2, while the output current at the output nodes OUT 3 and OUT 4 is I−(c+d)/2, therefore, an output current difference between at OUT 2 and OUT 3 would be (a+b+c+d)/2.

An objective of the present invention is to provide a chain-chopping current mirror for improving the performance of the conventional current mirror to advance the equality of the output currents.

Another objective of the present invention is to provide a method for stabilizing output currents for reduce the current difference between adjacent current channels.

The present invention provides a chain-chopping current mirror, which includes multiple output nodes, a bias source unit, multiple current mirroring units and multiple switch components. The bias source unit provides a reference bias at the reference voltage terminal thereof according to a current received by the input terminal thereof. Each current mirroring unit includes a bias input terminal and an output terminal, the bias input terminal is coupled with the reference voltage terminal to receive the reference bias and an output current is output at the output terminal thereof according to the reference bias. Each switch component includes a first terminal, a second terminal, a third terminal and a control terminal; the control terminal receives a clock signal, and whether the first terminal is coupled with the second terminal or the third terminal thereof is determined according to the clock signal. Wherein, the first terminal of the i th switch component is coupled with the output terminal of the i th current mirroring unit, the second terminal thereof is coupled with the i th output node and the third terminal thereof is coupled with the (i+1) th output node where i is a natural number.

According to the chain-chopping current mirror described in an embodiment of the present invention, the above-mentioned bias source unit includes a first transistor, wherein the gate terminal thereof is coupled with the first source/drain thereof, the second source/drain thereof is coupled with a first voltage level, the first source/drain is coupled with the input terminal of the bias source unit and the gate thereof is coupled with the reference voltage terminal of the bias source unit. In another embodiment, the bias source unit further includes a second transistor, wherein the gate thereof is coupled with a bias voltage, the first source/drain thereof is coupled with the input terminal of the bias source unit and the second source/drain thereof is coupled with the first source/drain of the first transistor.

According to the chain-chopping current mirror described in an embodiment of the present invention, each of the above-mentioned current mirroring units includes a third transistor, wherein the gate thereof is coupled with the reference voltage terminal to receive the bias voltage, the first source/drain thereof is coupled with the output terminal of the current mirroring unit and the second source/drain thereof is coupled with the first voltage level. In another embodiment, the bias source unit further includes a fourth transistor, wherein the gate thereof is coupled with a bias voltage, the first source/drain thereof is coupled with the output terminal of the current mirroring unit and the second source/drain thereof is coupled with the first source/drain of the third transistor.

According to the chain-chopping current mirror described in an embodiment of the present invention, the above-mentioned clock signal includes a first clock signal and a second clock signal, and each switch component includes: a first transmission-gate, which includes a first control terminal, a second terminal, a first transmission terminal and a second transmission terminal, wherein the first control terminal receives the first clock signal, the second control terminal receives the second clock signal, the first transmission terminal is coupled with the first terminal of the switch component and the second transmission terminal is coupled with the second terminal of the switch component; a second transmission-gate, which includes a first control terminal, a second terminal, a first transmission terminal and a second transmission terminal, wherein the first control terminal receives the second clock signal, the second control terminal receives the first clock signal, the first transmission terminal is coupled with the first terminal of the switch component and the second transmission terminal is coupled with the third terminal of the switch component.

According to the chain-chopping current mirror described in an embodiment of the present invention, the above-mentioned first transistor, each of the second transistor, the third transistor and the fourth transistor is a P-type metal oxide semiconductor field effect transistor (MOSFET).

The present invention provides a method for stabilizing output currents, which includes the following steps. First, multiple output nodes are provided. Next, a reference bias is provided according to an input current. Afterwards, multiple current mirroring units are provided and each current mirroring unit outputs an output current according to the reference bias. At a first time, the output terminal of the i th current mirroring unit is controlled for coupling with the i th output node. Furthermore, at a second time, the output terminal of the i th current mirroring unit is controlled for coupling with the (i+1) th output node. Wherein, i is a natural number.

According to the method for stabilizing output currents described in an embodiment of the present invention, the method further includes providing a clock signal; the time of a first status of the clock signal is the first time, and the time of a second status of the clock signal is the second time.

The present invention provides a chain-chopping current mirror, which includes multiple output nodes, a bias source unit, multiple current mirroring units and multiple switch components. The bias source unit provides a reference bias at the reference voltage terminal thereof according to a current received by the input terminal thereof. Each current mirroring unit includes a bias input terminal and an output terminal, the bias input terminal is coupled with the reference voltage terminal of the bias source unit to receive the reference bias and an output current is output at the output terminal thereof according to the reference bias. Each of the switch components includes 1˜(K+1) terminals, i.e. from the first terminal to the (K+1) th terminal, and the first terminal thereof is coupled with one of the K terminals, i.e. from the second terminal to the (K+1) th terminal, in response to one of the K clock signals, i.e. from the first clock signal to the K th clock signal. Wherein, the first terminal of the i th switch component is coupled with the output terminal of the i th current mirroring unit and the m th terminal thereof is coupled with the (i+m−1) th output node where i, K and m are natural numbers.

According to the chain-chopping current mirror described in an embodiment of the present invention, each of the above-described switch components includes K switch units and each of the switch units includes a control terminal, a first terminal and a second terminal. The control terminals of the (1˜K) th switch units respectively receive the (1˜K) th clock signals, wherein the first terminal of the a th switch unit is coupled with the first terminal of the switch component and the second terminal of the a th switch unit is coupled with the (a+1) th terminal of the switch component. Each of the clock signals includes a first status and a second status, the frequency of every clock signal is the same, between the (b−1) th clock signal and the b th clock signal there is a predetermined phase difference, and the time for each clock signal to take the first status is not overlapped with each other, where 0<a or b<K.

Since all the current channels are connected in series to each other through the switches and multiple series switching operations are conducted in the present invention, the goal to advance the equality of the output currents and the goal to reduce the current difference between adjacent current channels are achieved.

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve for explaining the principles of the invention.

FIG. 1 is a drawing of a conventional current mirror circuit configuration.

FIG. 2 is a drawing of a conventional cross-chopping current mirror circuit.

FIG. 3 is a block diagram of a chain-chopping current mirror circuit according to an embodiment of the present invention.

FIG. 4 is an implementation circuit drawing of the present embodiment in FIG. 3 .

FIG. 5 is an alternation of the implementation circuit drawing of the present invention in FIG. 4 .

FIG. 6 is another implementation circuit drawing of the present embodiment in FIG. 3 .

FIG. 7 is yet another implementation circuit drawing of the present embodiment in FIG. 3 .

FIG. 8 is another alternation of the implementation circuit drawing of the present embodiment in FIG. 4 .

FIG. 9 is a schematic drawing of a chain-chopping current mirror circuit according to another embodiment of the present invention.

FIG. 10 is an implementation circuit drawing of the present embodiment in FIG. 9 .

FIG. 11 is an implementation circuit drawing of a transmission-gate according to an embodiment of the present invention.

FIG. 12 is a circuit drawing of a chain-chopping current mirror circuit according to yet another embodiment of the present invention.

FIG. 13 is an implementation circuit drawing of the present embodiment in FIG. 12 .

FIG. 3 is a block diagram of a chain-chopping current mirror circuit according to an embodiment of the present invention. Referring to FIG. 3 , the current mirror includes a bias source unit 301 , multiple current mirroring units 302 , multiple switch components 303 and multiple output nodes OUT 1 ˜OUTN.

The bias source unit 301 provides a reference bias B 301 at a reference voltage terminal R 301 according to the received current at an input terminal I 301 . Each current mirroring unit 302 includes a bias input terminal and an output terminal and the bias input terminal is coupled with the reference voltage terminal R 301 to receive the reference bias B 301 . The output terminal of the current mirroring unit 302 outputs an output current according to the reference bias B 301 . Each switch component 303 includes a first terminal, a second terminal, a third terminal and a control terminal. The control terminal receives a clock signal, which decides whether the first terminal of the switch component is coupled with the second terminal thereof or the third terminal thereof. Wherein, the first terminal of the first switch component is coupled with the output terminal of the first current mirroring unit, the second terminal thereof is coupled with the first output node OUT 1 , the third terminal thereof is coupled with the second output node OUT 2 and the rest can be deduced by analogy.

It should be noted that the chain-chopping current mirror of the above-described embodiment does not limit the present invention. Anyone skilled in the art knows that the design and connection of the switch component 303 geared to a specific application by manufacturers vary. Therefore, as long as switch components are used to connect the current mirroring units 302 serially and multiple series switching operations are conducted according to the clock signal CLK, it is considered to belong to the scope or spirit of the invention.

For anyone skilled in the art to easily implement the present invention, a couple of embodiments are given as follows.

FIG. 4 is an implementation circuit drawing of the present embodiment in FIG. 3 . In the embodiment, the bias source unit 301 is implemented by using a transistor MP 1 connected to a diode, the multiple current mirroring units 302 are respectively implemented by using transistors MP 2 ˜MP 5 , and the second source/drain of each transistor of MP 1 ˜MP 5 is coupled with a first voltage level VDD (the higher power supply voltage VDD herein). For simplicity, only four current mirroring units 302 (MP 2 ˜MP 5 ) are given as exemplary in FIG. 4 ; however, the present invention does not limit the number of the current mirroring units. In fact, three or more than four current mirroring units 302 (transistors) can be disposed without departing from the scope or spirit of the invention.

When the clock signal CLK takes, for example, a logic-high level, the first terminal and the second terminal of the switch components S 401 , S 402 , S 403 and S 404 are in connection, the transistor MP 2 is coupled with the first output node OUT 1 , the transistor MP 3 is coupled with the second output node OUT 2 , the transistor MP 4 is coupled with the third output node OUT 3 and the transistor MP 5 is coupled with the fourth output node OUT 4 .

When the clock signal CLK takes, for example, a logic-low level, the first terminal and the third terminal of the switch components S 401 , S 402 , S 403 and S 404 are in connection, the transistor MP 2 is coupled with the second output node OUT 2 , the transistor MP 3 is coupled with the third output node OUT 3 , the transistor MP 4 is coupled with the fourth output node OUT 4 and the transistor MP 5 is coupled with the first output node OUT 1 . Based on such a chain-chopping working mode, the current mirror of the present invention is called ‘chain-chopping current mirror’.

To explain the performance of the chain-chopping current mirror provided by the present invention, it is assumed that the nominal output current of the design is I; affected by the process, the real output current of the transistor MP 2 is I+a, the real output current of the transistor MP 3 is I+b, the real output current of the transistor MP 4 is I+c and the real output current of the transistor MP 5 is I+d. By using the above-described chain-chopping current mirror of the present embodiment, the output current at the output node OUT 1 would be I+(d+a)/2, the output current at the output node OUT 2 would be I+(a+b)/2, the output current at the output node OUT 3 would be I+(b+c)/2 and the output current at the output node OUT 4 would be I+(c+d)/2. From the above-described output current equations, it can be seen that the output current at each output node has a same ‘average current error’ as the prior art.

Furthermore, the maximum current differences of two adjacent output nodes are evaluated assuming all of a, b, c and d are larger than zero. A simple calculation indicates the maximum current difference of the output nodes OUT 1 and OUT 2 is (a+b)/2, the maximum current difference of the output nodes OUT 2 and OUT 3 is (b+c)/2 , the maximum current difference of the output nodes OUT 3 and OUT 4 is (c+d)/2 and the maximum current difference of the output nodes OUT 4 and OUT 1 is (d+a)/2. In comparison with the conventional cross-chopping current mirror where the maximum current difference of the two adjacent output nodes OUT 2 and OUT 3 is (a+b+c+d)/2, it is clear that the current difference of two adjacent output nodes in the chain-chopping current mirror of the embodiment is much less than the conventional cross-chopping current mirror.

In the above-described embodiment, P-type transistors are used, however, the embodiment of the present invention allows using N-type transistors for another implementation as shown in FIG. 5 . The embodiment of the present invention allows each of the transistors MP 2 ˜MP 5 to respectively couple a transistor of MP 6 ˜MP 9 and a bias voltage VBB to be applied at each gate of the transistors MP 2 ˜MP 5 for adjusting the output currents of the output nodes OUT 1 ˜OUT 4 as shown in FIG. 6 . Further, the implementation shown in FIG. 6 allows adding a transistor MP 10 coupled with the input terminal thereof to form yet another implementation as shown in FIG. 7 . Furthermore, the circuits of FIG. 6 and FIG. 7 allow using N-type transistors as an alternative, which should be known by anyone skilled in the art and the detail is omitted herein for simplicity.

FIG. 8 is another alternation of the implementation circuit drawing of the present embodiment in FIG. 4 . In FIG. 8 , each of the switch components S 401 ˜S 404 in FIG. 4 is substituted by a first transmission-gate TR 1 and a second transmission-gate TR 2 and the clock signal CLK is divided by a first clock signal CK and a second clock signal CKB, wherein the clock signals CK and CKB are phase-inverted to each other. The first clock signal CK and the second clock signal CKB are provided to the first control terminal and the second control terminal of the first transmission-gate TR 1 and a second transmission-gate TR 2 , respectively. In this way, the above-described switch components S 401 ˜S 404 are switched.

Although the above-described scheme is able to reduce the output current differences of different output nodes, however, if an error resulted from the process with the transistor MP 1 , MP 1 may not match MP 2 ˜MP 5 , which causes a comprehensive current error at the output terminals OUT 1 ˜OUT 4 . To reduce the errors between the input current and the output currents, another embodiment of the present invention is provided. FIG. 9 is a schematic drawing of a chain-chopping current mirror circuit according to another embodiment of the present invention. Referring to FIG. 9 , in comparison with the above-described embodiment, an extra switch component S 405 is added at the input terminal and a first switch unit SW 91 and a second switch unit SW 92 are employed.

When the clock signal CLK takes, for example, a logic-high level, the first terminal and the second terminal of the switch components S 401 , S 402 , S 403 , S 404 and S 405 are in connection, and the first switch unit SW 91 is on and the second switch unit SW 92 is off, which makes the input terminal 1301 couple with the transistor MP 1 and the gate of the transistor MP 1 produces a bias voltage provided to the transistors MP 2 ˜MP 5 . The transistor MP 2 is coupled with the first output node OUT 1 , the transistor MP 3 is coupled with the second output node OUT 2 , the transistor MP 4 is coupled with the third output node OUT 3 and the transistor MP 5 is coupled with the fourth output node OUT 4 , so that the currents produced by the transistors MP 2 ˜MP 5 are provided to the output nodes OUT 1 ˜OUT 4 .

When the clock signal CLK takes, for example, a logic-low level, the first terminal and the third terminal of the switch components S 401 , S 402 , S 403 , S 404 and S 405 are in connection, and the first switch unit SW 91 is off and the second switch unit SW 92 is on, which makes the input terminal I 301 couple with the transistor MP 5 , and the transistor MP 5 now functions as the transistor MP 1 and the gate of the transistor MP 5 produces a bias voltage provided to the transistors MP 1 ˜MP 4 . The transistor MP 1 is coupled with the first output node OUT 1 , the transistor MP 2 is coupled with the second output node OUT 2 , the transistor MP 3 is coupled with the third output node OUT 3 and the transistor MP 4 is coupled with the fourth output node OUT 4 , so that the currents produced by the transistors MP 1 ˜MP 4 are sent to the output nodes OUT 1 ˜OUT 4 .

The above-described embodiment can be further modified, so that the input current channel is also controlled by the chain-chopping operation. The modified circuit has advantages that not only improving the current equality between adjacent channels, but also reducing the current difference accumulated with layers and caused by the unmatched input transistor. Referring to FIG. 10 , it is an implementation circuit drawing of the present embodiment in FIG. 9 . In the implementation circuit, all switch components S 401 ˜S 405 are substituted by a first transmission-gate TR 1 and a second transmission-gate TR 2 , all switch units SW 91 ˜SW 92 are substituted by a third transmission-gate TR 3 , and the clock signal CLK is divided into a first clock signal CK and a second clock signal CKB, which are phase-inverted to each other. In this way, the switching operations in FIG. 9 are implemented.

In both FIG. 9 and FIG. 10 , P-type transistors are employed. However, anyone skilled in the art should know that the embodiment of the present invention can employ N-type transistors instead of P-type transistors. With the N-type transistors used in the circuit, the circuit requires a first voltage level with a lower power supply voltage VSS instead of the first voltage level with a higher power supply voltage VDD required by the original circuit, which is a common knowledge and the description is omitted herein for simplicity. Anyone skilled in the art knows that the transmission-gate can be implemented by using the structure similar to FIG. 11 . Besides, the operations of the components are the conventional knowledge in the art too, so the detail is omitted herein.

The above-described embodiments have disclosed the chain-chopping current mirror circuits for switching two current channels; the present invention further provides a chain-chopping current mirror circuit for switching multiple channels. FIG. 12 is a circuit drawing of a chain-chopping current mirror circuit according to yet another embodiment of the present invention. Referring to FIG. 12 , the circuit includes a bias source unit 1201 , six current mirroring units 1202 , six switch components 1203 and six output nodes OUT 1 ˜OUT 6 , wherein the switch component SW 121 ˜SW 126 includes five terminals T 1 ˜T 5 , respectively. Each of the switch components determines the terminal T 1 to couple one of the terminals T 2 ˜T 5 according to the clock signals CK 1 ˜CK 4 .

FIG. 13 is an implementation circuit drawing of the present embodiment in FIG. 12 . Referring to FIG. 13 , the bias source unit 1201 is implemented by using a P-type transistor MP 1 , the six current mirroring units 1202 are implemented by using P-type transistor MP 2 ˜MP 7 , respectively, each of the switch components SW 121 ˜SW 126 is implemented by using four switch units M 01 ˜M 04 , and each of the switch units M 01 ˜M 04 is implemented by using an N-type transistor.

When the first clock signal CK 1 takes, for example, a logic-high level and the rest clock signals CK 2 ˜CK 4 take a logic-low level, all the switch units M 01 are on, the switch units M 02 ˜M 04 are off, the transistor MP 2 is coupled with the first output node OUT 1 , the transistor MP 3 is coupled with the second output node OUT 2 , the transistor MP 4 is coupled with the third output node OUT 3 , the transistor MP 5 is coupled with the fourth output node OUT 4 , the transistor MP 6 is coupled with the fifth output node OUT 5 and the transistor MP 7 is coupled with the sixth output node OUT 6 .

When the second clock signal CK 2 takes, for example, a logic-high level and the rest clock signals CK 1 , CK 3 and CK 4 take a logic-low level, all the switch units M 02 are on, the switch units M 01 , M 03 and M 04 are off, the transistor MP 2 is coupled with the second output node OUT 2 , the transistor MP 3 is coupled with the third output node OUT 3 , the transistor MP 4 is coupled with the fourth output node OUT 4 , the transistor MP 5 is coupled with the fifth output node OUT 5 , the transistor MP 6 is coupled with the sixth output node OUT 6 and the transistor MP 7 is coupled with the first output node OUT 1 .

When the third clock signal CK 3 takes, for example, a logic-high level and the rest clock signals CK 1 , CK 2 and CK 4 take a logic-low level, all the switch units M 03 are on, the switch units M 01 , M 02 and M 04 are off, the transistor MP 2 is coupled with the third output node OUT 3 , the transistor MP 3 is coupled with the fourth output node OUT 4 , the transistor MP 4 is coupled with the fifth output node OUT 5 , the transistor MP 5 is coupled with the sixth output node OUT 6 , the transistor MP 6 is coupled with the first output node OUT 1 and the transistor MP 7 is coupled with the second output node OUT 2 .

When the fourth clock signal CK 4 takes, for example, a logic-high level and the rest clock signals CK 1 ˜CK 3 take a logic-low level, all the switch units M 04 are on, the switch units M 01 ˜M 03 are off, the transistor MP 2 is coupled with the fourth output node OUT 4 , the transistor MP 3 is coupled with the fifth output node OUT 5 , the transistor MP 4 is coupled with the sixth output node OUT 6 , the transistor MP 5 is coupled with the first output node OUT 1 , the transistor MP 6 is coupled with the second output node OUT 2 and the transistor MP 7 is coupled with the third output node OUT 3 . Subsequently, the next cycle of the chain-chopping operations is repeated according to the clock signals CK 1 ˜CK 4 .

It is a common knowledge for anyone skilled in the art that all the switch units M 01 ˜M 04 can be implemented by multiple means, such as by using P-type transistors or by using transmission-gates as shown in FIG. 11 . For those modifications, the clock signals need to be modified too. In the embodiment, N-type transistors, but not limited to by the present invention, are used to implement the above-described switch units. Similarly, although in the embodiment, the P-type transistors MP 1 ˜MP 7 are used to implement the above-described bias source unit 1201 and current mirroring units 1202 , but N-type transistors are also feasible instead of the P-type transistors MP 1 ˜MP 7 and the present invention does not limit it. Note that although the above-described embodiments take four current channels to form a chain-chopping current mirror as exemplary, however, according to the spirit of the present invention, three current channels, five current channels or more current channels can be used to form a chain-chopping current mirror, which is not limited by the invention.

In summary, since every current channel is connected in series to each other through multiple switches for series-switching operations, thus, the present invention is able to advance the equality of the output currents and further accordingly reduce the current difference between adjacent current channels.

It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the specification and examples to be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims and their equivalents.