USPatent applicationPatented

Computer power indicator circuit

Granted 19 Aug 2008 · 1 office action

Life of the application

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Abstract

In one preferred embodiment, a power indicator circuit for a computer comprises a light-emitting diode (LED) indicating power management states of a computer; a first resister connected between one pole of the LED and a power source; a second resistor connected between the other pole of the LED and a power source, a first branch circuit connected between the one pole and ground; and a second branch circuit connected between the other pole and ground. Wherein the first resistor and the second resistor control a current through the LED. Because the LED emits lights of different colors or turns off according to the different power management states, it is easy for users to see what the power management state of the computer is.

Description

4 parts
›DESCRIPTION

1. Field of the Invention

The present invention relates to the field of power indicator circuits for computers, and particularly to a circuit for indicating power management states of a computer.

2. Description of Related Art

Typical computers employ a single color light-emitting diode (LED) as a power indicator to indicate power management states. However, if a current through the LED is less than a rated current of the LED, the LED is likely to be too dim to see clearly. If the current through the LED is greater than the rated current of the LED, the LED is likely to burn out or at the very least have a shortened life span. Thus, the function and reliability of the power indicator are not stable.

What is desired, therefore, is a power indicator circuit for indicating power management states of a computer which has a stable function and reliability.

›SUMMARY OF THE INVENTION

In one preferred embodiment, a power indicator circuit for a computer comprises a light-emitting diode (LED) indicating power management states of a computer; a first resister connected between one pole of the LED and a power source; a second resistor connected between the other pole of the LED and a power source, wherein the first resistor and the second resistor controls current through the LED; a first branch circuit connected between the one pole and ground; and a second branch circuit connected between the other pole and ground.

Other advantages and novel features will become more apparent from the following detailed description of preferred embodiments when taken in conjunction with the accompanying drawings, in which:

›BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram of a power indicator circuit for a computer of a preferred embodiment of the present invention; and

FIG. 2 is a schematic graph showing current through a light emitting diode in relation to resistance of a resistor used in the circuit of FIG. 1 .

›DETAILED DESCRIPTION OF THE INVENTION

As shown in FIG. 1 , in a preferred embodiment of the present invention, a power indicator circuit for indicating a power management state of a computer includes a bi-color light-emitting diode (LED) U 1 , a first resistor R 1 , a second resister R 2 , a first transistor Q 1 , a second transistor Q 2 , a third transistor Q 3 , and a forth transistor Q 4 . The first transistor Q 1 , the second transistor Q 2 , the third transistor Q 3 , and the forth transistor Q 4 are all bipolar junction transistors (BJTs). The first resistor R 1 and the second resistor R 2 are used to control current passing through the bi-color LED U 1 .

One pole of the bi-color LED U 1 is connected to a voltage VCC via the first resistor R 1 . A capacitor C 1 is connected between the one pole of the bi-color LED U 1 and ground. A base of the first transistor Q 1 as a first port receives a first signal S 3 LED from a motherboard. In this embodiment, the Advanced Configuration and Power Interface (ACPI) specification will be used as an example. According to the ACPI, the first signal S 3 LED is a control signal to control the LED U 1 to indicate an S 3 (or suspend to RAM) power management state. The base of the first transistor Q 1 is connected to a voltage VCC via a resistor R 3 . A collector of the first transistor Q 1 is connected to a node M between the one pole of the bi-color LED U 1 and the first resistor R 1 . An emitter of the first transistor Q 1 is connected to a collector of the second transistor Q 2 . An emitter of the second transistor Q 2 is grounded. A base of the second transistor Q 2 as a second port receives a second signal S 4 LED from the motherboard. According to the ACPI specification, the second signal S 4 LED is a control signal to control the LED U 1 to indicate an S 4 (or suspend to disk) power management state.

The other pole of the bi-color LED U 1 is connected to a voltage VCC via the second resistor R 2 . A capacitor C 2 is connected between the other pole of the bi-color LED U 1 and ground. A base of the third transistor Q 3 as a third port receives a third signal S 1 LED from a motherboard. According to the ACPI specification, the third signal S 1 LED is a control signal to control the LED U 1 to indicate the S 1 power management state where both a central processing unit (CPU) and a random access memory (RAM) has power. The base of the third transistor Q 3 is connected to a voltage VCC via a resistor R 5 . A collector of the third transistor Q 3 is connected to a node N between the other pole of the LED U 1 and the second resistor R 2 . An emitter of the third transistor Q 3 is connected to a collector of the forth transistor Q 4 . An emitter of the forth transistor Q 4 is grounded. A base of the forth transistor Q 4 as a forth port receives the second signal S 4 LED from the motherboard.

Impedances of the first resistor R 1 and the second resistor R 2 are same. Impedances of the resistor R 3 and R 5 are same. The first transistor Q 1 and the second transistor Q 2 cooperatively form a first branch circuit. The third transistor Q 3 and the forth transistor Q 4 cooperatively form a second branch circuit.

In operation, when the power management state of the computer is the S 3 state, the first transistor R 1 and the second transistor R 2 are turned on, and the third transistor R 3 is turned off. A current flows through the LED U 1 from the other pole to the one pole. Thus, the LED U 1 emits one color of light. When the power management state of the computer is the S 1 state, the third transistor R 3 and the forth transistor R 4 are turned on, and the fist transistor R 1 is turned off. A current flows through the LED U 1 from the one pole to the other pole. Thus, the LED U 1 emits another color of light. When the power management state of the computer is the S 4 state, the second transistor R 2 and the forth transistor R 4 are both turned off. There is no current flowing through the LED U 1 . Thus, the LED U 1 does not emit light.

Referring to the FIG. 2 , what is shown is that when BJT transistors are used in the circuit, the current through the LED U 1 can be controlled by the resistance of the first resistor R 1 . Therefore, the resistor R 1 is selected according to the inversely proportional relationship to the current through the LED U 1 , that is to say, the greater the resistance of the first resistor R 1 , the smaller the current through the LED U 1 . Thus, designers can select a proper resistor as the first resistor R 1 according to a rated current of the LED U 1 so that the LED U 1 can function normally and have a long life in operation.

It is believed that the present embodiment and its advantages will be understood from the foregoing description, and it will be apparent that various changes may be made thereto without departing from the spirit and scope of the invention or sacrificing all of its material advantages, the example hereinbefore described merely being a preferred or exemplary embodiment.

Claims as granted

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Classifications

9 codes
IPC · International Patent Classification
Section G — Physics
  • G09F9/33
  • G08B5/22
Section H — Electricity
  • H05B44/00
  • H01J7/42
USPC · US Patent Classification
340/815.45340/691.6315/133315/129340/691.1

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File wrapper

⤢ drag to zoomApr 2006Jul 2006Oct 2006Jan 2007Apr 2007Jul 2007Oct 2007Jan 2008Apr 2008Jul 2008Oct 2008USPTOApplicantNon-final rejectionResponse after non-finalNotice of allowance
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Pendency
2.3 y
844 days filing → grant
Office actions
1
non-final + final
Responses
1
no RCE
Examiner
Toan N Pham
art unit 2612 · TC 2600
Citations: 4 back · 1 forward

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