Bootstrapped switch for sampling inputs with a signal range greater than supply voltage

This application claims priority under 35 USC § 119 (e) (1) of provisional application No. 60/659,705 filed Mar. 8, 2005.

The present invention relates to electronic circuitry and, in particular, to a bootstrapped switch for sampling inputs with a signal range greater than supply voltage.

Highly integrated power management applications often require the ability to measure voltage quantities that exceed the supply voltage in magnitude. This is primarily due to a basic need to maximize efficiency by running the power management IC with the lowest supply voltage possible, while still maintaining the ability to sample and measure quantities from the surroundings that could well exceed the battery voltage.

In today's highly integrated power management applications, a low power successive approximation register (SAR) analog-to-digital converter (ADC) is usually present to monitor on-chip and off-chip voltage quantities. The need often arises to extend the on-chip ADC range to sample voltage inputs that are greater than the power supply value. The ADC has to run on the lowest battery voltage possible while still maintaining the ability to sample inputs beyond the supply range.

The most widely used prior art bootstrap circuit in ADC applications is shown in FIG. 1 . The circuit of FIG. 1 includes transistors MN 1 -MN 10 , MP 1 , and MP 2 ; inverter INV; capacitors C 1 , C 2 , and C 3 ; input node IN; output node OUT; clock signal nodes PHI and PHIZ; and source voltage V DD . NMOS transistor MN 1 connected to terminal OUT is the bootstrapped switch. A sampling capacitor (not shown) connects between terminal OUT and ground. This circuit is widely used in pipelined ADC converters to increase the bandwidth of the track and hold circuit at the front end of the converter. Most pipelined ADC converters typically have relatively small fully differential ranges that fall well within the supply range of the chip. As a result, the prior art switch presented in FIG. 1 will do the job just fine.

The circuit of FIG. 1 operates as follows. First consider the charge pump formed by transistors MN 8 , MN 9 , capacitors C 1 and C 2 , and the inverter INV. It works as follows, assume that initially the voltage across the capacitors C 1 and C 2 is zero, when the clock signal PHIZ goes high, the top plate of capacitor C 1 goes to supply voltage V DD and since the bottom plates of capacitors C 2 and C 3 are grounded for this state, those capacitors are charged till their top plates reach voltage V DD −V tn (where V tn is the threshold voltage for NMOS transistors MN 9 and MN 10 ). When the clock signal PHIZ goes low, the top plate of capacitor C 2 is pushed well above voltage V DD (or 2V DD −V tn to be exact) yielding complete charging of capacitor C 1 to V DD through the switch MN 8 . With the next phase when PHIZ goes high again, since capacitor C 1 is charged to V DD , the top plate of capacitor C 1 will be pushed to 2V DD (two times voltage V DD ) and capacitors C 2 and C 3 will be completely charged to V DD . In steady state, capacitors C 1 , C 2 , and C 3 will be charged to V DD and the voltage on the top plates of capacitors C 1 and C 2 will change between V DD and 2V DD . The classical bootstrapped switch reaches its steady state after at least one clock period.

Under the assumption that all the capacitors are charged to V DD , the bootstrapped switch operates as follows: when PHIZ goes high, the bottom plate of capacitor C 3 is grounded and switch MN 10 is on, hence capacitor C 3 is charged to V DD ; switch MP 2 is also on, driving the gate of transistor MP 1 to V DD , hence transistor MP 1 is off and finally transistor MN 6 is on and grounds the gate terminal of the main switch MN 1 . Since their gate terminal is grounded, transistors MN 3 , MN 2 , and MN 1 are off. During this phase, the switch MN 1 disconnects the input node IN from the output node OUT and capacitor C 3 is charged to V DD . When PHIZ goes low, since transistor MN 6 is off, the gate terminal of MN 1 becomes high impedance. Initially, the bottom plate of capacitor C 3 is floating, but because of the fact that switch MN 4 connects capacitor C 3 between the gate and source terminal of transistor MP 1 , this transistor turns on immediately and the charge stored on capacitor C 3 starts flowing to the gate terminal of main switch MN 1 . While the gate voltage of switch MN 1 rises, transistor MN 2 turns on and forces the bottom plate of capacitor C 3 towards the input voltage VIN, which pushes the top plate of capacitor C 3 to voltage V DD +VIN. Eventually this voltage appears at the gate of transistor MN 1 and as a result transistor MN 1 turns on completely to connect the input terminal IN to the output terminal OUT. Transistor MN 2 turns on completely to connect input terminal IN to the bottom terminal capacitor C 3 and transistor MN 3 turns on completely to drive the gate of transistor MP 1 to the input voltage level. The gate-to-source voltages of all these four switches MN 1 , MN 2 , MN 3 and MP 1 , are all equal to V DD . An important detail about device reliability is the following: even though the bootstrapped switch can be turned on by pulling the gate terminal of MP 1 to ground, if the input signal is equal to V DD then the voltage difference between the gate and source of transistor MP 1 would be 2V DD . For this reason, during the phase the bootstrapped switch is turned on, the gate voltage on transistor MP 1 is forced to the input signal through the switch MN 3 so that the gate-to-source voltage of transistor MP 1 is bounded within V DD , and hence the reliability is enhanced. The main challenge of this switch is the design of the scheme that protects MP 1 by restricting maximum voltage appearing across its terminals.

Even though the prior art switch in FIG. 1 performs well for input signal levels that are within the supply range, it is useless when the input signal exceeds the supply voltage. The reason is the following: When the switch is turned on, input voltage appears at the gate of transistor MP 1 . As mentioned previously, this is necessary in order to restrict the gate-to-source voltage of this device to V DD . Since switch MP 2 is a PMOS transistor, if its drain voltage exceeds the supply voltage (because the input signal is greater than V DD ), the parasitic drain-substrate diode of this device will be forward biased, which will yield a huge current flow through the path formed by transistors MN 2 and MN 3 , and the parasitic body diode of transistor MP 2 . This current path renders the prior art bootstrapped switch useless for applications where input signal level exceeds supply voltage. The body diode that would be activated here is that between the drain D of transistor MP 2 and the bulk B of transistor MP 2 , shown in FIG. 2 . A cross-section of transistor MP 2 , shown in FIG. 2 , includes p type region p; n type region n; drain D; gate G; source S; and bulk B.

A bootstrapped switch for sampling inputs with a signal range greater than supply voltage includes: a bootstrapped switch coupled between an input node and an output node; a first transistor having a first end coupled to a control node of the bootstrapped switch, and having a backgate coupled to a second end of the first transistor; a first capacitor having a first end coupled to a second end of the first transistor; a second transistor coupled between the first end of the first transistor and a supply node, and having a control node coupled to a first clock signal node; a third transistor coupled between the second end of the first transistor and the supply node; a charge pump having an output coupled to a control node of the third transistor; a level shifter having a first output coupled to a second end of the first capacitor; a fourth transistor coupled between the supply node and a control node of the first transistor; a fifth transistor having a first end coupled to a control node of the fourth transistor and a second end coupled to the output of the charge pump, having a control node coupled to the supply node, and having a backgate coupled to the second end of the fifth transistor; a sixth transistor coupled between the first end of the fifth transistor and a common node, and having a control node coupled to the first clock signal node; a seventh transistor coupled between the input node and the control node of the first transistor, and having a control node coupled to the first clock signal node; an eighth transistor coupled between the input node and the control node of the first transistor, and having a control node coupled to the control node of the bootstrapped switch; and a ninth transistor coupled between the first end of the first transistor and the common node, and having a control node coupled to the second clock signal node.

In the drawings:

FIG. 1 is a circuit diagram of a prior art bootstrap circuit;

FIG. 2 is a cross-section of a transistor shown in FIG. 1 ;

FIG. 3 is a circuit diagram of a preferred embodiment bootstrapping circuit, according to the present invention.

A bootstrapping circuit, according to the present invention, enables the precise sampling of input signals larger than the chip supply voltage with minimal power consumption overhead. The bootstrapped switch enables extending the range of low power SAR ADCs beyond supply voltage enabling a greater dynamic range, while minimizing power consumption. This is very useful in highly integrated power management applications where multi-channel SAR ADCs are utilized to measure off-chip voltage quantities that could well exceed the supply voltage. The prior art bootstrapped switches cannot be used to sample voltage inputs greater than the supply voltage, without suffering from huge power losses due to parasitic body diodes that get forward biased as the input exceeds the supply. This solution is cost-effective to fabricate and does not introduce any more stresses on the devices than a standard bootstrapping switch would.

Power consumption is minimized in the present invention since the switch consumes no static power and suffers from no parasitic body diodes that get turned on when the input voltage exceeds the supply voltage. Prior art bootstrap switches suffer from huge currents through drain-bulk body diode junctions which render them useless for sampling input signals that exceed the supply voltage.

The bootstrapped switch, according to the present invention, operates with minimal power consumption since no static currents are needed to keep the switch operational. Furthermore, all body diode junctions in the switch are reverse biased for the entire input voltage range including voltages that are greater than the supply voltage. Prior art bootstrapped switches (for example, the type used in pipelined ADC Converters) would suffer from forward biased body diode junctions in the event of feeding an input signal greater than the supply voltage. Furthermore, the present invention has a constant Vgs (gate to source voltage) drive of the bootstrapped switch over the entire range of the input signal enhancing the switch's bandwidth capabilities.

FIG. 3 shows a preferred embodiment bootstrapping circuit according to the present invention. The circuit of FIG. 3 includes NMOS transistors MN 20 -MN 33 ; PMOS transistors MP 11 , MP 12 , MP 13 , and MP 14 ; capacitors C 11 -C 14 ; supply node V DD ; input node IN; clock signals PHI and PHIZ; and output node OUT. The bootstrapped switch is NMOS transistor MN 20 that is connected to the output node OUT. Clock signal PHIZ is clock signal PHI inverted. Capacitor C 13 is the clock-bootstrapped capacitor. Transistors MN 23 and MN 24 , and capacitors C 11 and C 12 form a charge pump.

Transistors MP 11 , MP 12 , MN 21 , MN 22 , MN 29 , and MN 30 form a simple level shifter. This level shifter is used in digital designs when it is necessary to convey a logic signal to a digital block having different power supply level. When the differential logic signals PHI and PHIZ are applied to transistors MN 30 and MN 29 , the positive feedback created by PMOS transistors MP 11 and MP 12 forces one of the nodes N 2 or N 3 to go to ground and the other to go to input voltage level Vin. The transistors MN 21 and MN 22 are used to guarantee this behavior when the input signal level is very low (close or equal to the threshold voltage of transistor MP 11 and MP 12 ). If the input signal is low, there isn't enough gate over-drive for transistors MP 11 and MP 12 to switch the state of the level shifter. In this case transistor MN 21 or MN 22 , driven by the clock signals, will act as a switch and drive the appropriate output node to the input voltage. To prevent meta-stable condition, transistors MN 29 and MN 30 should be designed much stronger than transistors MP 11 and MP 12 . This level shifter operates such that nodes N 2 and N 3 change between ground and Vin, at alternate phases.

The switch operates as follows: The operation of the charge-pump formed by transistors MN 23 and MN 24 , and capacitors C 11 and C 12 , is explained above for the prior art switch of FIG. 1 . Hence, capacitors C 11 and C 12 are charged to source voltage V DD after one clock period once the clock is applied; and node N 4 and node N 5 change between V DD and 2V DD at alternate phases. It is obvious from the schematic that when node N 5 goes to 2V DD (when clock signal PHIZ goes high) to turn on MN 26 , node N 2 is grounded (because transistor MN 29 is on), hence capacitor C 13 is also charged to source voltage V DD .

Before analyzing the operation of the bootstrapped switch, the circuit formed by transistors MP 14 , MN 25 , and MN 33 is described. Notice that the source terminal of MP 14 , together with its bulk terminal, is connected to node N 5 , hence it changes between voltage levels V DD and 2V DD . Since the gate terminal of transistor MP 14 is connected to source voltage V DD , when node N 5 goes to 2V DD (clock signal PHIZ goes high), transistor MP 14 turns on and since for this case transistor MN 33 is off, node N 6 is charged to voltage 2V DD to turn on transistor MN 25 . At the alternate phase, the gate to source voltage of transistor MP 14 is zero, hence it is off, and since transistor MN 33 is on, node N 6 is drained to ground and consequently transistor MN 25 is off. In short, node N 6 changes between voltage level 2V DD and 0. Notice that even though the gate to source voltage of transistor MN 33 is less than or equal to source voltage V DD , the drain to gate voltage of this device can go twice as high. Therefore, it is necessary to protect this device from over voltage stress. This can be achieved with either using a cascode device, exactly like transistor MN 5 in FIG. 1 or transistor MN 33 has to be chosen as a drain extended device.

Now the main bootstrapped switch is described. During off phase (clock signal PHIZ is high), transistor MN 28 is on, therefore node N 1 is at ground and the switch is off. Node N 5 is at voltage 2V DD , hence transistor MP 14 is on, therefore transistor MN 25 is on driving node N 7 to voltage V DD . Transistor MN 29 is on hence the bottom plate of capacitor C 13 is at ground and transistor MN 26 is on charging the top plate of capacitor C 13 , i.e., node N 8 , to V DD . Since node N 7 and N 8 are both at V DD , transistor MP 13 is off. And finally, transistors MN 31 , MN 32 , and MN 27 are all off.

At the beginning of the on phase of the switch, transistor MN 27 begins charging node N 1 until it reaches to voltage V DD −V T(MN27) (where V T(MN27) is the threshold voltage of transistor MN 27 ). From this point on, transistor MN 27 is off since it doesn't have enough gate overdrive to conduct. Furthermore, when the charge stored on capacitor C 13 takes over and drives node N 1 to voltage V DD +V IN , transistor MN 27 is completely turned off.

With the rising edge of the clock signal PHI, node N 2 is pushed to input voltage V IN ; since capacitor C 13 is already charged to source voltage V DD , the top plate of capacitor C 13 , i.e., node N 8 , goes to voltage V DD +V IN and the charge on capacitor C 13 passes through transistor MP 13 to charge node N 1 . There are two distinct mechanisms that turn transistor MP 13 on by forcing node N 7 to input voltage V IN in three different input signal regions:

1. When input signal is within the voltage range V DD −V T(MN31) <V IN (where V T(MN31) is threshold voltage of transistor MN 31 ), transistor MN 31 is always off (its drain voltage is equal to V IN , its gate voltage is at V DD and its source voltage is initially at V DD and then at V IN ). For this case, transistor MP 13 is turned on as follows: initially since transistor MN 25 is turned off, node N 7 is floating and it is at source voltage V DD . When node N 8 is pushed to voltage V DD +V IN , the voltage on node N 7 increases because of the capacitive coupling from node N 8 to N 7 through the parasitic C GS (gate-to-source capacitance) of transistor MP 13 . The voltage on node N 7 at the end of this transition can be expressed as:

V N ⁢ ⁢ 7 = V DD + C GS ⁡ ( MP ⁢ ⁢ 13 ) C GS ⁡ ( MP ⁢ ⁢ 13 ) + C 14 ⁢ V IN

Hence, the gate to source voltage of transistor MP 13 can be expressed as:

=

Since the input signal is large, by properly choosing the value of capacitor C 14 , it is possible to make voltage V GS(MP13) greater than the threshold voltage of transistor MP 13 and turn it on. Once transistor MP 13 is turned on, Capacitor C 13 charges node N 1 to voltage V DD +V IN , which turns on transistor MN 20 to connect the input signal to the output, and at the same time transistor MN 32 further drives node N 7 to the input signal. Notice that transistor MP 13 is protected from over voltage stress.

2. When the input signal is within the voltage range 0<V IN <V T(MP13) , regardless of the value of capacitor C 14 , it is not possible to make the gate to source voltage of transistor MP 13 greater than V T(MP13) using the transient on node N 8 , as it is clear from the above equation. But for this case, since the input signal is low enough, transistor MN 31 , driven by clock signal PHI, will turn on and drain node N 7 from voltage V DD towards the input voltage. Furthermore, once transistor MP 13 turns on and node N 1 is charged to voltage V DD +V IN , transistor MN 32 also turns on to force node N 7 further towards the input signal level. 3. When the input signal is within the voltage range V T(MP13) <V IN <V DD −V T(MN31) , both of the mechanisms described above are active and drive node N 7 to the input signal level.

One of the advantages of the present invention over the prior art circuit is the switch turn on time. Notice that the bottom plate of capacitor C 3 in FIG. 1 is charged to the input voltage level through transistor MN 2 ; but transistor MN 2 itself is gradually turned on. Therefore, for fast turn on time, it is necessary to choose a large aspect ratio for transistor MN 2 , which results in a larger parasitic load on the gate terminal of transistor MN 1 requiring a larger value for capacitor C 3 to overcome charge losses to these parasitic capacitors. The present invention, shown in FIG. 3 , on the other hand, charges the bottom plate of capacitor C 13 directly to the input voltage. Furthermore, transistor MN 27 helps at the beginning of the turn on transition for faster response. This extra speed can be very useful for a pipelined ADC system where the speed of the switch turn-on and turn-off is as important as its accuracy. The trade-off for this extra-speed is small shoot-through current flowing from the input node to ground through the level shifter circuit.

To easily understand the operation of this switch one needs to examine the state of the nodes in the switch before and after every timing event. There are two timing events associated with the operation of this switch: 1) PHI going from 0 to 1, which puts the switch in PHI=1 state, and 2) PHI going from 1 to 0, which puts the switch in PHI=0 state. With the initial condition for capacitors C 11 , C 12 , and C 13 in mind, the state of the nodes in the switch for the PHI=0, and the PHI=1 states are examined below:

During PHI=0 state, transistor MP 13 will be OFF because its V gs =V N7 −V N8= 0, while its drain is at V N1 =0. During PHI=0 state, transistor MP 14 will be ON because its source is at V N5 =2V DD while its gate is at V DD which will charge node N 6 to 2V DD from the charge stored on capacitor C 11 . During PHI=1 state, transistor MN 27 starts charging node N 1 until N 1 reaches V DD −V tn , where V tn is the threshold voltage of an NMOS device. After that, transistor MN 27 turns OFF either because node N 1 goes to a value above V DD or there is not enough gate overdrive. After that point the circuit works such that the path through transistor MP 13 takes over and drives node N 1 to V DD +V in . During PHI=1 state and for V in <V tp , where V tp is the threshold voltage of a PMOS device, transistor MP 13 starts by being OFF because its V gs =V in <V tp (node N 8 =V DD +V in while node N 7 stays at V DD because of capacitor C 14 ). Transistor MN 31 will be turned ON pulling node N 7 to V in which will turn ON transistor MP 13 because V gs of MP 13 becomes equal to V DD now. As MP 13 turns ON the positive feedback loop provided by MN 32 and node N 1 will further connect node N 7 to V in through transistor MN 32 . During PHI=1 state and for V in >V DD −V tn transistor MN 31 will always be OFF because its V gs <V tn (its gate is at V DD , its source is at V in >V DD −V tn , while its drain is at V DD or V in ). As node N 8 gets pushed to V DD +V in , the voltage on node N 7 (initially a floating node charged to V DD ) will be determined by the capacitive division between capacitor C 14 and the gate-source parasitic capacitance associated with transistor MP 13 . By increasing the size of capacitor C 14 , we guarantee that node N 7 remains at roughly the same voltage, V DD , even after the capacitive division. This will guarantee that transistor MP 13 will turn ON to charge node N 1 , and the positive feedback through transistor MN 32 will further guarantee that node N 7 is charged to V in . During PHI=1 state and for V tp <V in <V DD −V tn , this is a mixture of the two cases explained in two items above.

A bootstrapped switch, according to the present invention, with an input range greater than the supply voltage is described above. Unlike traditional prior art bootstrapped switches the present invention suffers from no body diode problems for inputs greater than the supply voltage. The switch can be employed in a variety of applications where sampling of input signals beyond the supply voltage is needed (i.e. SAR ADCs, Pipelined ADCs, etc.). The switch maintains a constant V gs drive on the bootstrapped NMOS transistor for the entire input signal range, and requires only one phase of the system clock (i.e. no delayed phases required). Furthermore, the switch is easily manufacturable in standard CMOS technologies with high voltage CMOS capability or drain extended device capability.

While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.