Multi-phase clock generator and method thereof

1. Field of the Invention

The present invention relates to a data receiving circuit, especially to a multi-phase clock generator and method thereof.

2. Description of the Prior Art

For a large system-on-a-chip (SOC), the manufacturing process is limited primarily by the manufacturing process of the silicon intellectual property (SIP) adopted by the SOC. If the manufacturing process of each SIP were more flexible, the difficulty and time in exploiting an SOC could be reduced. For a common high-speed serial link, data reception and transmission are frequently achieved in the following ways: full-rate reception and transmission, half-rate reception and transmission, or multi-phase over-sampling reception and transmission. The former two methods require a full or a half transmission rate for the operating clock of the chip. When the data transmission rate is as high as or higher than the giga-Hertz (G-bit/sec) level, low-cost manufacturing processes such as 0.25 μm and 0.35 μm processes become deficient and can hardly be utilized. As to the multi-phase over-sampling reception and transmission, plenty of sampling circuits adopting relatively low sampling rates are utilized to achieve high transmission rates. Therefore, the operating clock of the chip can be effectively reduced such that the limit on the manufacturing process can be lowered.

It is therefore an objective of the present invention to provide a multi-phase clock generator.

According to an embodiment of the claimed invention, a multi-phase clock generator is disclosed. The multi-phase clock generator generates a set of multi-phase clock signals, and the multi-phase clock generator includes a signal generator, a phase adjusting circuit, and a phase interpolator. The signal generator generates a plurality of first clock signals according to a reference clock signal. The phase adjusting circuit, which is a phase rotator or a phase selecting circuit, which are coupled to the signal generator, receives the first clock signals and adjusts the phases of the first clock signals according to a control signal to generate a plurality of second clock signals. The phase interpolator, which is coupled to the phase adjusting circuit, interpolates the second clock signals to generate the set of multi-phase clock signals.

According to another embodiment of the claimed invention, a method for generating a set of multi-phase clock signals is disclosed. The method includes the steps of: generating a plurality of first clock signals according to a reference clock signal; adjusting the phases of the first clock signals according to a control signal to generate a plurality of second clock signals; and interpolating the second clock signals to generate the set of multi-phase clock signals.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

FIG. 1 is a block diagram of a multi-phase clock generator according to a first embodiment of the present invention.

FIG. 2 shows the clock signals generated by the signal generator shown in FIG. 1 .

FIG. 3 shows the multi-phase clock signals generated by the phase interpolator shown in FIG. 1 .

FIG. 4 is a block diagram of a multi-phase clock generator according to a second embodiment of the present invention.

FIG. 5 shows the relation between a data signal and the multi-phase clock signals.

FIG. 6 is the truth table that is utilized by a phase detecting circuit shown in FIG. 4 to generate a phase shifting signal.

FIG. 1 shows a multi-phase clock generator 100 according to the first embodiment of the present invention. As shown in FIG. 1 , the multi-phase clock generator 100 includes a signal generator 110 , a phase adjusting circuit 120 , and a phase interpolator 130 . In this embodiment, the signal generator 110 receives a reference clock signal S 1 and generates a plurality of clock signals S 2 . The clock signals S 2 include a plurality of signals that have the same frequency and are each delayed by a specific and constant phase difference. In other words, the result when graphed on a timing diagram forms a ladder or step-like appearance. The phase adjusting circuit 120 can simultaneously shift all of the phases of the clock signals S 2 by advancing or delaying the phases by a specific period. The clock signals S 2 are phase shifted into the clock signals S 3 , which also include a plurality of signals. Then the clock signals S 3 are transmitted to the phase interpolator 130 . The phase interpolator 130 interpolates the clock signals S 3 by a specific multiple to generate a set of multi-phase clock signals S 4 .

For example, the signal generator 110 can be a phase locked loop (PLL). The PLL along with a delay circuit and a divider receives a reference clock signal S 1 of 100 MHz and then generates 10 clock signals S 2 of 250 MHz each of which is delayed by a specific and constant period of 400 ps. Referring to FIG. 2 , the clock signals S 2 include 10 signals having different phases. The phase adjusting circuit 120 can be a phase selecting circuit or a phase rotator. Practically, the phase adjusting circuit 120 can shift the 10 clock signals S 2 [ 0 ], S 2 [ 1 ], . . . , S 2 [ 9 ] by advancing or delaying the phases of the 10 clock signals by a specific period to generate the clock signals S 3 which also include 10 signals. In addition, the phase interpolator 130 can interpolate the 10 clock signals S 3 with a multiple of 2 to generate 20 multi-phase clock signals S 4 of 250 MHz each of which is delayed by a specific and constant period of 200 ps. As shown in FIG. 3 , the multi-phase clock signals S 4 include 20 signals named S 4 [ 0 ], S 4 [ 1 ], S 4 [ 2 ], . . . , S 4 [ 19 ]. The number of the signals, the frequencies, and the phase delays of clock signals S 1 , S 2 , S 3 , and S 4 can be optionally adjusted. Because the adjusting method and the operating principles of the phase selecting circuit, the phase rotator, and the phase interpolator are well known by those skilled in the art, the lengthy description is omitted for brevity.

The multi-phase clock generator 100 mentioned above can be utilized for data reception and transmission in a high-speed serial link such as PCI express. Please refer to FIG. 4 . FIG. 4 shows a multi-phase clock generator 400 according to the second embodiment of the present invention. The multi-phase clock generator 400 can be applied in a receiving circuit for adjusting the set of multi-phase clock signals S 4 according to the receiving status of the receiving circuit. The multi-phase clock generator 400 includes a signal generator 402 , a phase adjusting circuit 404 , a phase interpolator 406 , an over-sampler 410 , a phase detecting circuit 420 , and a digital filter 430 . The operating principles of the signal generator 402 , the phase adjusting circuit 404 , and the phase interpolator 406 are the same as those described in the first embodiment so they are not described again for brevity. Please note that in this embodiment the multi-phase clock generator 400 and the receiving circuit share the same over-sampler 410 . The over-sampler 410 receives a data signal S D and then samples the data signal S D by utilizing the set of multi-phase clock signals S 4 as the sampling signal.

In this embodiment, the data signal S D is over sampled by a sampling signal whose frequency is double of the frequency of the data signal S D , i.e., the frequency of the sampling signal is twice the frequency of the data signal S D . The set of multi-phase clock signals S 4 can be regarded as a high frequency signal, therefore, if the frequency of the data signal S D is 2.5 GHz, then the effective frequency of the set of multi-phase clock signals S 4 is supposed to be 5 GHz or more, according to the sampling theorem. For example, the set of multi-phase clock signals S 4 may include 20 signals each of which is 250 MHz and delayed by 200 ps as shown in FIG. 3 . That is, the set of multi-phase clock signals S 4 can be regarded as a signal S 4 whose effective frequency is equal to 20*250 MHz (=5 GHz). Therefore, although the frequency of the data signal S D is as high as 2.5 GHz, the multi-phase clock generator 400 merely needs to generate signals of 250 MHz by utilizing the aforementioned technique. As a result, the manufacturing cost can be greatly reduced.

Because the sampling signal, i.e., the set of multi-phase clock signals S 4 , includes 20 signals, in each sampling process the over sampler 410 generates 20 sampled data D correspondingly. In this embodiment, to achieve better sampling result, the phase detecting circuit 420 collects 20 sampled data of a sampling process (D n [ 0 ], D n [ 1 ], . . . , D n [ 19 ]) along with the last sampled data of the previous sampling process (D n−1 [ 19 ]) to generate a set of sampled result having 21 sampled data, and then analyze the relationship between the set of sampled result and the set of multi-phase clock signals S 4 . Please refer to FIG. 5 . FIG. 5 illustrates the operating principle of the phase detecting circuit 420 . In FIG. 5 three successive multi-phase clock signals S 4 (S 4 [n−1], S 4 [n], S 4 [n+1]) sample the data signal S D to obtain three sampled data (D[n−1], D[n], D[n+1]). If the multi-phase clock signal S 4 [n] matches the rising edge or the falling edge of the data signal S D , then the multi-phase clock signals S 4 [n- 1 ] and S 4 [n+1] will correspond to the centers of data bits. As a result, the sampled data D[n−1] and D[n+1] would be more correct.

As mentioned above, the phase detecting circuit 420 detects a set of sampled results of 21 bits, taking three successive bits as a set to determine the logic values, and generates a signal UP/DN according to the truth table shown in FIG. 6 . The signal UP/DN is regarded as determining signal to shift the phases of the set of multi-phase clock signals S 4 . Referring to FIG. 6 , when the phase detecting circuit 420 detects the situations of lines 4 and 5 ( 011 , 100 ), a signal UP for advancing the phases is generated; alternatively, when the phase detecting circuit 420 detects the situations of lines 2 and 7 ( 001 , 110 ), a signal DN for delaying the phases is generated. As for the other situations, since information acquired is not sufficient to make a judgment, no signal for advancing or delaying the phases is generated. The signal UP/DN is then transmitted to the digital filter 430 for further processing.

The function of the digital filter 430 is effectively equal to a low pass filter. The present invention provides three methods that the digital filter 430 follows to determine the timing of phase shifting.

Method 1: Running average. The UP signal is regarded as a “1”, the DN signal is regarded as a “−1”, and the initial value of the digital filter 430 is set to be “0”. The digital filter 430 sums the received UP signal and DN signal, and a threshold M is set. When the summed value is larger than M, the digital filter 430 generates a signal PUP for advancing the phases, and the phase adjusting circuit 404 shifts the clock signals S 3 by advancing the phases according to the signal PUP. The summed value is then reset to 0. Alternatively, when the summed value is less than−M, the digital filter 430 generates a signal PDN for delaying the phases, and the phase adjusting circuit 404 shifts the clock signals S 3 by delaying the phases according to the signal PDN. Then, the summed value is reset to 0.

Method 2: Averaging in an interval. The UP signal is regarded as a “1”, the DN signal is regarded as a “−1”, and the initial value of the digital filter 430 is set to be “0”. The digital filter 430 sums the received UP signal and DN signal, and a time threshold T is set. By summing up the received UP signal and DN signal over the time threshold T, the digital filter 430 generates the signal PUP for advancing the phases or the signal PDN for delaying the phases according to the summed value. If the summed value is larger than “0”, the digital filter 430 generates the signal PUP to instruct the phase adjusting circuit 404 to shift the clock signals S 3 by advancing the phases, and the summed value is reset to 0. If the summed value is less than “0”, the digital filter 430 generates the signal PDN to instruct the phase adjusting circuit 404 to shift the clock signals S 3 by delaying the phases, and the summed value is reset to 0.

Method 3: Accounting separately. The UP signal and the DN signal are both regarded as a “1”, and the initial value of the digital filter 430 is set to be “0”. The received UP signal and DN signal are summed up respectively, and a threshold M is set. When the summed value corresponding to the UP signal is larger than M, the digital filter 430 generates the signal PUP to instruct the phase adjusting circuit 404 to shift the clock signals S 3 by advancing the phases, and the summed value corresponding to the UP signal is reset to 0. Alternatively, when the summed value corresponding to the DN signal is larger than M, the digital filter 430 generates the signal PDN to instruct the phase adjusting circuit 404 to shift the clock signals S 3 by delaying the phases, and the summed value corresponding to the DN signal is reset to 0.

In this embodiment, because the 10 clock signals S 2 (250 MHz) required by the phase adjusting circuit 404 are generated by the signal generator 402 , and each of the 10 clock signals S 2 is delayed by 400 ps, after being processed by the phase adjusting circuit 404 , the phases of the 10 clock signals S 3 are advanced or delayed for a specific period. Therefore, the clock signals S 3 whose phases are adjusted can be utilized as the sampling signal to obtain more accurate sampling results.

Please note that the number of clock signals S 2 is not constrained to 10. Basically, it is only required that the effective frequency A*B*C, is larger than the frequency of the data signal S D , where A is the number of the clock signals outputted by the phase adjusting circuit 404 , B is the frequency of the clock signals, and C is the multiple utilized by the phase interpolator 406 . For example, if the effective frequency (A*B*C) is twice the frequency of the data signal S D , and the frequency of the data signal S D is 2.5 Gb/sec, these are the several choices for the clock signals S 2 and the multiple of the phase interpolator 406 :

1. 10 clock signals of 250 MHz each of which is delayed by 400 ps, and the multiple is 2. Therefore, a sampling signal including 20 clock signals with 250 MHz each of which is delayed by 200 ps is obtained. The effective frequency is 250 MHz*10*2 (=5 GHz).

2. 5 clock signals of 250 MHz each of which is delayed by 800 ps, and the multiple is 4. Therefore, a sampling signal including 20 clock signals with 250 MHz each of which is delayed by 200 ps is obtained. The effective frequency is 250 MHz*5*4 (=5 GHz).

3. 5 clock signals of 500 MHz each of which is delayed by 400 ps, and the multiple is 2. Therefore, a sampling signal including 10 clock signals with 500 MHz each of which is delayed by 200 ps is obtained. The effective frequency is 500 MHz*5*2 (=5 GHz).

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.