Semiconductor memory device capable of storing data of various patterns and method of electrically testing the semiconductor memory device

This application claims priority and benefit of Korean Patent Application No. 10-2004-0091883, filed on Nov. 11, 2004, the disclosure of which is herein incorporated by reference in its entirety.

1. Field of the Invention

The invention relates to semiconductor memory devices, and more particularly, to a semiconductor device capable of storing data of various patterns and a method of electrically testing the same.

2. Description of the Related Art

Functions of semiconductor memory devices are electrically tested using address pins, data pins, and control pins included in the semiconductor memory devices. Testing the semiconductor memory devices simultaneously provides an efficient means of performing the electrical test and, thus, minimizes costs. However, since a tester has a limited number of channels, the number of semiconductor memory devices capable of being simultaneously tested, that is, being subject to a parallel test, is limited.

A means of increasing the number of semiconductor memory devices that can be simultaneously tested is by reducing the number of I/O channels of a tester allotted to data pins of semiconductor memory devices. A related technique was disclosed by Samsung Electronics Ltd in U.S. Pat. No. 6,323,664, issued to Kim, et al. on Nov. 27, 2001, entitled “Semiconductor Memory Device Capable of Accurately Testing for Defective Memory Cells at a Wafer Level.”

FIG. 1 is a block diagram of a memory cell array in a conventional test mode of a semiconductor memory device. FIG. 2 is a flowchart illustrating a method of electrically testing the semiconductor memory device of FIG. 1 .

Referring to FIGS. 1 and 2 , the semiconductor memory device includes data input/output pads PAD 0 through PAD 31 and a memory cell array 18 , to and from which data can be written and read.

To undergo an electrical function test, the semiconductor memory device is connected to a tester 16 via a probe card/device under test (DUT) board 14 . To reduce the number of I/O channels 10 of the tester 16 used to test the semiconductor memory device, the data input/output pads PAD 0 through PAD 31 are divided into groups MDQ 0 through MDQ 7 , each of which include four data input/output pads. One representative data input/output pad from each group is the coupled to one I/O channel 10 of the tester 16 via an assigned probe needle 12 of the probe card/DUT board 14 . For example, PAD 0 is selected as the representative data input/output pad of the group MDQ 0 and PAD 4 is selected as the representative data input/output pad of the group MDQ 1 . Thus, eight representative data input/output pads PAD 0 , PAD 4 , . . . , PAD 28 are coupled to the tester 16 via probe needles 12 of the probe card/DUT board 14 .

In an electrical test of a semiconductor memory device based on the design scheme shown in FIG. 1 , a general direct current (DC) test and a function test for memory devices are performed first. As shown in FIG. 2 , to test a writing function of the memory cell array 18 , the I/O channels 10 of the tester 16 via the probe card/DUT board 14 send to-be-written data to memory cells through the representative pads PAD 0 , PAD 4 , . . . , PAD 28 . The data is transferred not only to data input buffers DIN_BUF 0 , DIN_BUF 4 , . . . , DIN_BUF 28 corresponding to the representative pads PAD 0 , PAD 4 , . . . , PAD 28 , but also to the remaining data input buffers via a data transfer path for a test mode illustrated by a dotted line in FIG. 1 , and written to the memory cell array 18 , in operation S 10 . Then, the written data is read out from the memory cell array 18 to check if the memory cell array 18 is normal or defective, in operation S 20 .

In the conventional art as shown in FIG. 1 , when data is written to the memory cell array 18 via representative pads PAD 0 , PAD 4 , . . . , and PAD 28 of groups MDQ 0 through MDQ 7 , identical data bits are transmitted to the four input/output pads in each group. For example, a data bit of 0 or 1 is transferred to all of the four input/output pads PAD 0 , PAD 1 , PAD 2 , and PAD 3 in group MDQ 0 . Thus, when different data bits are written through neighboring input/output pads, it is impossible to determine defective memory cells. For example, when data of 1111 is written to neighboring memory cells of the memory cell array 18 through input/output pads in a group, for example, PAD 0 through PAD 3 of group MDQ 0 , the writing test is properly performed. However, when data of 1010 is written to neighboring memory cells of the memory cell array 18 , defective cells cannot be checked.

As described above, in the conventional art, semiconductor devices can be effectively parallel tested by reducing the number of I/O channels of a tester that are assigned to data pins of the semiconductor devices. However, in the conventional art, accurately testing the memory cell array 18 through writing of data of various bit patterns is limited.

The invention provides a semiconductor memory device including a control signal generation pad capable of writing different data to data input/output pads of each group during a test mode.

The invention also provides a method of electrically testing a semiconductor memory device using a control signal generation pad capable of writing different data to data input/output pads of each group during a test mode.

According to an aspect of the invention, there is provided a semiconductor memory device including: a memory cell array storing data; address pads used to designate the memory cell array; data input/output pad groups via which the data is read from and written to the memory cell array, the data input/output pad groups into each of which N data input/output pads are classified in a test mode for the memory cell array; and a control signal generation pad capable of writing non-identical data to the N data input/output pads of each group when data is written to the memory cell array in the test mode for the memory cell array.

The control signal generation pad may be connected to a data input multiplexer (DINMUX) included in the semiconductor memory device. The DINMUX may control designation of data input/output pads according to the frequency of toggling of a control signal.

The control signal generation pad may be a control pin for a semiconductor memory device not used in a test mode for the memory cell array.

According to another aspect of the invention, there is provided a method of electrically testing a semiconductor memory device, including operations of: starting a test for a writing function of a memory cell array of the semiconductor memory device; grouping N data input/output pads of the semiconductor memory device; enabling a control signal generation pad capable of writing non-identical data to the N data input/output pads of each group when data is written through the N data input/output pads; writing different data bits to neighboring memory cells of the memory cell array of the semiconductor memory device using the control signal generation pad; reading out the written data from the memory cell array of the semiconductor memory device; and concluding the test for the writing function of the memory cell array of the semiconductor memory device.

The test for the writing function of the memory cell array may be included in an electrical die sort (EDS) test or a final test.

The above and other features and advantages of the invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:

FIG. 1 is a block diagram for explaining an operation of writing data to a memory cell array in a test mode of a conventional semiconductor memory device;

FIG. 2 is a flowchart illustrating a method of electrically testing the semiconductor memory device of FIG. 1 ;

FIG. 3 is a block diagram for explaining an operation of writing data to a memory cell array in a test mode of a semiconductor memory device according to the invention;

FIG. 4 is a timing chart for explaining an example where a data input/output multiplexer (DINMUX) of FIG. 3 applies a clock to select input/output pads PAD 0 through PAD 3 ; and

FIG. 5 is a flowchart illustrating a method of electrically testing the semiconductor memory device according to the invention.

The invention will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. The invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art.

FIG. 3 is a block diagram for explaining an operation of writing data to a memory cell array in a test mode of a semiconductor memory device according to the invention. The semiconductor memory device according to the invention, to which data of various bit patterns can be written, includes a memory cell array 106 , address pads A 0 -AN 104 , data input/output pads PAD 0 through PAD 31 , and control signal generation pads CLK 1 through CLKN 100 . The memory cell array 106 stores data. The address pads A 0 -AN 104 are used to designate the memory cell array 106 . In a mode for testing the memory cell array 106 , the data input/output pads PAD 0 through PAD 31 are grouped into MDQ 0 through MDQ 7 , each group comprising four data input/output pads. The data input/output pad groups MDQ 0 through MDQ 7 can read information of data bits from and write information of data bits to the memory cell array 106 . The control signal generation pads CLK 1 -CLKN 100 enable non-identical data to be written to the data input/output pads PAD 0 through PAD 31 when data is written to the memory cell array 106 in the test mode for the memory cell array 106 .

The semiconductor device further includes a data input multiplexer (DINMUX) 102 , which is connected to the control signal generation pad 100 , to write non-identical data to the data input/output pads PAD 0 through PAD 31 in write and read test modes. The control signal generation pad 100 may be a control pin not used in the write and read test modes for the memory cell array 106 .

The control signal generation pad 100 is coupled to representative pads PAD 0 , PAD 4 , . . . , and PAD 28 of the data input/output pads PAD 0 through PAD 31 via probe needles 112 to which input/output (I/O) channels 110 of a tester 108 are connected. Thereafter, four data input/output pads in each group, for example, PAD 0 , PAD 1 , PAD 2 , and PAD 3 in group MDQ 0 , are designated to be connected to an I/O channel 110 of the tester 108 one by one according to the frequency of toggling of a clock generated by the DINMUX 102 . Similarly, the remaining data input/output pads PAD 4 through PAD 31 in groups MDQ 1 through MDQ 7 are designated separately.

When the data input/output pads PAD 0 through PAD 31 are designated by the control signal generation pad 100 , different data are provided to the data input/output pads PAD 0 through PAD 31 of the groups MDQ 0 through MDQ 7 from the I/O channels 110 of the tester 108 via a probe card/DUT board 114 , transferred to data input buffers DIN_BUF 0 through DIN_BUF 31 and input/output drivers 10 DRV 0 through IO DRV 31 along a data transfer path for a test mode, and written to the memory cell array 106 .

Although the number of data input/output pads included in each of the groups MDQ 0 through MDQ 7 is 4 in the present embodiment, the number may be changed to a multiple of 2, for example, 2 or 8. Also, although a control pin not used in the mode for testing the memory cell array 106 is used as the control signal generation pad 100 in the present embodiment, a Not Connection (NC) pin not used in a semiconductor memory device may be used as the control signal generation pad 100 . The control signal generation pad 100 may be produced in various forms by a circuit designer of a semiconductor memory device.

FIG. 4 is a timing chart for explaining an example where the DINMUX 102 applies a clock to select the data input/output pads PAD 0 through PAD 3 . Referring to FIG. 4 , a control signal which is sent to the data input/output pad groups MDQ 0 through MDQ 7 via the control signal generation pad 100 is illustrated. In case (a) where toggling occurs only in interval T 1 , a first input/output pad, for example, PAD 0 , is enabled. In case (b) where toggling occurs in intervals T 1 and T 2 , a second input/output pad, for example, PAD 1 , is enabled. In case (c) where toggling occurs in intervals T 1 , T 2 , and T 3 , a third input/output pad, for example, PAD 2 , is enabled. In case (d) where toggling occurs in intervals TI through T 4 , a fourth input/output pad, for example, PAD 3 , is enabled.

In case (e) where toggling occurs in intervals T 1 through T 5 , a pair of input/output pads may be enabled. For example, in case (e), input/output pads PAD 0 and PAD 1 may be selected, or input/output pad PAD 2 and PAD 3 may be selected. However, the selection of the input/output pads PAD 0 through PAD 31 according to the control signal clocks (a) through (e) may be achieved by other methods by a circuit designer of a semiconductor memory device. The present embodiment introduces only an example.

FIG. 5 is a flowchart illustrating a method of electrically testing a semiconductor memory device according to the invention. Referring to FIG. 5 , an electrical test for a semiconductor memory device starts. At this time, typically conducted DC characteristic test and other function tests are executed. Thereafter, a test for a writing function of a memory cell array starts. In operation S 100 , N data input/output pads of the semiconductor memory device are grouped in the test for the writing function of the memory cell array. N is a multiple of 2, so it may be, for example, 2, 4, or 8. Then, N input/output pads of each group are coupled to a single I/O channel of a tester, in operation S 110 .

In operation S 120 , a control signal generation pad capable of writing different data to memory cells through N data input/output pads in each group is enabled as illustrated in FIG. 4 . Thereafter, non-identical data, for example, data bits of 1, 0, 1, and 0, are written to the memory cell array through neighboring data input/output pads using the control signal generation pad, in operation S 130 . Then, the written data, namely, non-identical data, are checked in operation S 140 , thereby testing a function of the memory cell array of the semiconductor memory device. The test is concluded.

According to the invention as described above, the number of I/O channels of a tester that are used when electrically testing a semiconductor memory device can be effectively reduced, and data of various bit patterns can be written to a cell array of the semiconductor memory device through a reduced number of I/O channels of the tester. Thus, the accuracy of an electrical test for semiconductor memory devices is increased.

While the invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the following claims.