Digital/analog converter, display device using the same, and display panel and driving method thereof

This application claims priority to and the benefit of Korean Patent Application No. 10-2004-0080368, filed in the Korean Intellectual Property Office on Oct. 8, 2004, the entire content of which is incorporated herein by reference.

The present invention relates to a display device. More particularly, the present invention relates to an organic light emitting diode (OLED) display using a digital/analog converter, a display panel of the OLED display, and a driving method thereof.

In general, an OLED display is a display device that electrically excites fluorescent organic material for emitting light and visualizes an image by voltage programming or current programming N×M organic light emitting pixels.

An organic light emitting pixel (or diode) includes anode (indium tin oxide or ITO), organic thin film, and cathode (metal) layers.

The organic thin film layer has a multi-layer structure including an emitting layer (EML), an electron transport layer (ETL), and a hole transport layer (HTL) so as to balance electrons and holes to thereby enhance light emitting efficiency. Further, the organic thin film separately includes an electron injection layer (EIL) and a hole injection layer (HIL).

Methods of driving the organic light emitting pixels having the foregoing configuration include a passive matrix method and an active matrix method employing a thin film transistor (TFT) or a MOSFET.

In the passive matrix method, an anode and a cathode are formed crossing each other, and a line is selected to drive the organic light emitting pixels. In the active matrix method, an indium tin oxide (ITO) pixel electrode is coupled to the TFT, and the light emitting pixel is driven in accordance with a voltage maintained by capacitance of a capacitor.

Herein, the active matrix method can be classified as a voltage programming method or a current programming method depending on the type of signals transmitted to the capacitor so as to distinctively control the voltage applied to the capacitor.

A pixel circuit according to a conventional voltage programming method has difficulties in expressing high-level grayscales due to deviations of threshold voltages V TH of TFTs and/or mobilities of carriers of the TFTs, the deviations being generated as a result of a non-uniform manufacturing process of the TFTs.

On the other hand, although currents and/or voltages supplied from driving transistors in a plurality of pixel circuits may not be uniform, a pixel circuit employing a current programming method can provide panel uniformity as long as a current supplied from a current source to the pixel circuits is uniform.

In realization of a display device by using the pixel circuit that employs the current programming method, a digital/analog (D/A) converter is required to convert grayscale data into a grayscale current so as to apply the grayscale current to the pixel circuit. In addition, the D/A converter performs a gamma correction on the grayscale data in consideration of characteristics of a display panel of the display device.

However, a conventional D/A converter outputs linear grayscale currents corresponding to grayscale data so that the conventional D/A converter cannot satisfy non-linear gamma characteristics of a display panel.

Accordingly, a desired image is not displayed on the display panel and thus image quality is degraded.

The above information disclosed in this Background of the Invention section is only for enhancement of understanding of the background of the invention and therefore, unless explicitly described to the contrary, it should not be taken as an acknowledgment or any form of suggestion that the above information forms the prior art that is already known in this country to a person skilled in the art.

An embodiment of the present invention provides a digital/analog converter capable of outputting non-linear grayscale currents and a display device using the same.

An exemplary display device includes a display unit, a data driver, and a scan driver. The plurality of data lines transmit data currents, the plurality of scan lines transmit scan signals, and the plurality of pixel areas are defined by the data lines and the scan lines. The data driver converts a plurality of grayscale data that include first data and second data into at least one of the data currents, and applies the at least one of the data currents to at least one of the data lines. The scan driver sequentially applies the scan signals to the plurality of scan lines. Further, the data driver divides the plurality of grayscale data into at least two grayscale ranges including a first grayscale range, outputs a first current of the first grayscale range in which at least one of the plurality of grayscale data is included by using the first data, and outputs a second current that corresponds to the second data in the first grayscale range.

In another embodiment, a display panel includes a display unit including a plurality of pixels that display an image corresponding to applied data currents, and a grayscale current generator for converting a plurality of grayscale data into the data currents and applying the data currents to the plurality of pixels. In addition, the grayscale current generator divides the plurality of grayscale data into at least two grayscale ranges that include a first grayscale range, generates a first current of the first grayscale range in which at least one of the plurality of grayscale data are included by using a high-order bit data of the at least one of the plurality of grayscale data, generates a second current of the first grayscale range by using a low-order bit data of the at least one of the plurality of grayscale data, and adds the first and second currents and outputs a sum of the first and second currents as at least one of the data currents.

A further embodiment includes a digital/analog (D/A) converter for converting digital grayscale data that include first data and second data into grayscale currents and outputting the converted grayscale currents. The D/A converter divides the grayscale data into a plurality of grayscale ranges including a first grayscale range and converts the divided grayscale data into the grayscale currents. The D/A converter includes a first current output unit, a multiplexer, and a second current output unit. The first current output unit outputs a first reference current of the first grayscale range including the grayscale data by using the first data of the grayscale data. The multiplexer selects a first reference voltage of the first grayscale range from among a plurality of first voltages respectively corresponding to unit currents of the respective grayscale ranges. The second current output unit outputting a second current by using the first reference voltage output from the multiplexer and the second data

Another further embodiment includes a digital/analog (D/A) converter converting digital grayscale data that include first data and second data into grayscale currents and outputting a converted result. The digital/analog converter divides the grayscale data into a plurality of grayscale ranges including the first grayscale range and converts the divided grayscale data into the grayscale currents. The digital/analog converter includes a first current output unit, a first multiplexer, and a second current output unit. The first current output unit outputs a first current of the first grayscale range in which the grayscale data is included by using a first data among the grayscale data. The first multiplexer selects a third reference current from among a plurality of third currents that respectively correspond to unit currents of the respective grayscale ranges and outputting the selected third current. The second current output unit copies the third reference current output from the first multiplexer and outputs a current that corresponds to a product of the third reference current and the second data as a second current.

Another further embodiment includes a method for driving a display panel having a plurality of pixel circuits displaying an image corresponding to applied data currents. In the method, a plurality of grayscale data are divided into at least two grayscale ranges that include a first grayscale range. The driving method includes generating a first current of the first grayscale range including at least one of the plurality of the grayscale data by using a first data of the at least one of the plurality of grayscale data; selecting a first reference signal of the first grayscale range from among a plurality of first signals that respectively correspond to the at least two grayscale ranges and outputting the selected first signal; generating a third current corresponding to the first reference signal; generating a second current by using the third current and a second data of the at least one of the plurality of grayscale data; and adding the first current and the second current and outputting an added result as at least one of the data currents.

FIG. 1 is a top plan view schematically illustrating an OLED display according to an embodiment of the present invention.

FIG. 2 is a block diagram of a data driver according to an embodiment of the present invention.

FIG. 3 is a block diagram of a grayscale current generator of the D/A converter according to a first embodiment of the present invention.

FIG. 4 shows a gamma curve according to the first embodiment of the present invention.

FIG. 5 shows a range that corresponds to a second grayscale range in the gamma curve of FIG. 4 .

FIG. 6 is a circuit diagram illustrating the D/A converter according to the first embodiment of the present invention.

FIG. 7 is a circuit diagram illustrating a D/A converter according to a second embodiment of the present invention.

An embodiment of the present invention will hereinafter be described in detail with reference to the accompanying drawings.

In the following detailed description, a connection between one part to another includes a direct connection between them, or an electrical connection via a third device.

The drawings and description are to be regarded as illustrative in nature and not restrictive.

Like reference numerals designate like elements throughout the specification and the drawings.

A display device and a driving method of the same according to an embodiment of the present invention will now be described in more detail with reference to the accompanying drawings.

Throughout the description of certain embodiments of the present invention, a display device that uses electro-luminescence of an organic material will be described as a light emitting display device.

FIG. 1 is a top plan view schematically illustrating an organic light emitting diode (OLED) display according to an embodiment of the present invention.

As shown in FIG. 1 , the OLED display according to the embodiment of the present invention includes a substrate 1000 to form a display panel that has a display unit 100 for displaying an image thereon and a peripheral part.

A data driver 200 and scan drivers 300 and 400 are formed in the peripheral part.

The display unit 100 includes a plurality of data lines D 1 -Dm, a plurality of scan lines S 1 -Sn, a plurality of light emission control lines E 1 -En, and a plurality of pixels 110 .

The plurality of data lines Dl-Dm are arranged in a column direction, and are for transmitting data currents for an image to the pixels 110 .

The plurality of scan lines (or first scan lines) S 1 -Sn and the plurality of light emission control lines (or second scan lines) E 1 -En are respectively arranged in a row direction, and are for respectively transmitting scan signals and light emission control signals to the pixels 110 .

A pixel area is defined by one data line and one scan line.

The data driver 200 applies a data current (or data currents) to the data lines D 1 -Dm.

The scan driver 300 sequentially applies scan signal(s) to the plurality of scan lines S 1 -Sn, and the scan driver 400 sequentially applies light emission control signal(s) to a plurality of light emitting scan lines E 1 -En.

The data driver 200 and/or scan drivers 300 and 400 may be coupled to the substrate 1000 in various schemes. For example, it may be realized in a form of a chip so as to be installed to various types of electrical connection members, such as a tape carrier package (TCP), a flexible printed circuit, and a film.

On the other hand, the data driver 200 and/or the scan drivers 300 and 400 may be directly attached to the substrate 1000 of the display unit, and/or they may be realized as a driving circuit that is formed on the substrate 1000 and has a layer structure similar to the data lines D 1 -Dm, scan and light emission control lines S 1 -Sn and E 1 -En, and transistors of the pixels (or pixel circuits).

FIG. 2 is a block diagram illustrating a data driver 200 according to an embodiment of the present invention.

As shown in FIG. 2 , the data driver 200 includes a shift register 210 , a latch 220 , a grayscale current generator 230 , and an output unit 240 .

The shift register 210 sequentially shifts a start signal SP and outputs the sequentially shifted start signal in synchronization with a clock signal Clk.

The latch 220 latches a video signal and outputs the latched video signal in synchronization with an output signal of the shift register 210 .

The grayscale current generator 230 receives the output video signal of the latch 220 and generates a grayscale current that corresponds to the video signal.

According to an embodiment of the present invention, the grayscale current generator 230 includes a plurality of digital/analog (D/A) converters DAC 1 -DACm. Each of the plurality of D/A converters DAC 1 -DACm converts an input digital video signal into a respective one of the grayscale currents Iout 1 -Ioutm and outputs the respective one of the grayscale currents Iout 1 -Ioutm.

The output unit 240 applies the grayscale currents Iout 1 -Ioutm output from the grayscale current generator 230 to the data lines D 1 -Dm.

The output unit 240 may be provided as a plurality of buffer circuits respectively coupled between the D/A converters DAC 1 -DACm included in the grayscale current generator 230 and the data lines D 1 -Dm.

A grayscale current generator (e.g., the grayscale current generator 230 ) according to a first embodiment of the present invention will now be described with reference to FIGS. 3 , 4 , and 5 .

In the following descriptions, a video signal is described to be a 6-bit grayscale data, for better understanding and ease of description, but the present invention is not thereby limited.

FIG. 3 is a block diagram illustrating a D/A converter DACm of the grayscale current generator 230 according to the first embodiment of the present invention.

FIG. 4 illustrates a gamma curve according to the first embodiment of the present invention, and FIG. 5 exemplarily illustrates an output grayscale current corresponding to an input grayscale data of a second grayscale range.

As shown in FIG. 3 , the D/A converter DACm includes a reference current output unit 231 , a multiplexer 232 , and a fine current output unit 233 according to the first embodiment of the present invention.

The reference current output unit 231 receives a high-order bit data of the grayscale data and outputs a reference current I R.

The multiplexer 232 selects a reference voltage V R that corresponds to the high-order bit data and transmits the selected reference voltage V R to the fine current output unit 233 , and the fine current output unit 233 receives the reference voltage V R and outputs a fine current ΔI that corresponds to a low-order bit data of the grayscale data.

Referring to FIG. 4 and according to one embodiment of the present invention, the grayscale current generator 230 controls the gamma curve to be divided into a plurality of grayscale ranges, controls the reference current output unit 231 to output reference currents I R1 -I R3 or an offset current by using the high-order bit data of the grayscale data, and controls the fine current output unit 233 to output grayscale data that corresponds to the low-order bit data of the grayscale data.

The fine current may be obtained by multiplying respective unit currents I 1 -I 4 of the respective grayscale ranges and the low-order bit data. Values of the unit currents I 1 -I 4 vary according to the gradient of the gamma curve in first through fourth grayscale ranges, respectively.

Thus, when the multiplexer 232 selects a reference voltage of a grayscale range in which the corresponding grayscale data is included and transmits the selected reference voltage to the fine current output unit 233 , the fine current output unit 233 outputs a fine current ΔI by using a unit current I and a lower-order bit data of grayscale data of the grayscale range.

In other words, as shown in FIG. 5 , when a grayscale data Gin of the second grayscale range is input, the reference current output unit 231 outputs a reference current I R1 by using a high-order bit data of the grayscale data Gin.

The multiplexer 232 transmits a reference voltage V R2 of the second grayscale range to the fine current output unit 233 , and the fine current output unit 233 outputs a fine current ΔI by using a low-order bit data of the grayscale data Gin.

For example, when the grayscale data Gin is 25 (011001), the reference current output unit 231 outputs a reference current I R1 corresponding to the high-order bit data 16 (01), and the multiplexer 232 outputs the reference voltage V R2 , and the fine current output unit 233 outputs a current that corresponds to 9 times the unit current I 2 .

Accordingly, the grayscale current generator 230 outputs a grayscale current corresponding to a grayscale data with respect to the divided grayscale ranges.

An internal configuration of a D/A converter (e.g., the D/A converter DACm) according to the first embodiment will now be described in more detail with reference to FIG. 6 .

FIG. 6 is a circuit diagram illustrating the D/A converter (e.g., the D/A converter DACm) according to the first embodiment of the present invention.

As shown in FIG. 6 , the reference current output unit 231 includes four transistors M 11 -M 14 and four switches SW 1 -SW 14 , receives a high-order bit data of grayscale data, and outputs a corresponding reference current I R .

Gates of the respective transistors M 11 -M 14 are applied with reference voltages V R1 -V R3 and offset voltages Voffset, and sources of the respective transistors M 11 -M 14 are coupled to a power source VDD.

The switches SW 11 -SW 14 are respectively coupled to drains of the respective transistors M 11 -M 14 , and turned on/off by the high-order bit data of the grayscale data.

In addition, the transistors M 11 -M 13 may be set to respectively output currents that correspond to 16 times the unit currents I 1 , I 2 , and I 3 by using reference voltages V R1 , V R2 , and V R3 applied to the gates of the transistors M 11 -M 13 , respectively. The transistor M 14 may be set to output an offset current Ioffset by using an offset voltage Voffset applied to the gate of the transistor M 14 .

In this instance, the offset current Ioffset corresponds to grayscale data 0.

Thus, the switch SW 14 is turned on and outputs the offset current Ioffset when the high-order bit data of the grayscale data is ‘00’, and the switch SW 11 is turned on and outputs the reference current I R1 when the high-order bit data is ‘01’.

When the high-order bit data is ‘10’, the switches SW 11 and SW 12 are turned on and output the reference current I R2 as shown in the Equation 1, and when the high-order bit data is ‘11’, the switches SW 11 , SW 12 , and SW 13 are turned on and output the reference current I R3 as shown in the Equation 2.

I R2 =16× I 1 +16× I 2   [Equation 1]

I R3 =16× I 1 +16× I 2 +16× I 3   [Equation 2]

Since a current does not have to be output when the high-order bit data of the grayscale data is ‘00’, the offset current Ioffset may be output when the high-order bit data is ‘01’. A case in which the offset current Ioffset is output when the high-order bit data of the grayscale data is ‘00’ will now be described in more detail.

The multiplexer 232 receives the high-order bit data of the grayscale data, selects one of four reference voltages V R1 -V R4 , and transmits the selected reference voltage to the fine current output unit 233 .

That is, the reference voltage V R1 is output when the high-order bit data of the grayscale data (00) is included in the first grayscale range, and the reference voltages V R2 -V R4 are output when the high-order bit data of the grayscale data are ‘01’, ‘10’, and ‘11’ respectively.

The fine current output unit 233 includes four transistors M 21 -M 24 and four switches SW 21 -SW 24 .

Each transistor M 21 -M 24 outputs a current that corresponds to a reference voltage output from the multiplexer 232 , and each switch SW 21 -SW 24 is turned on in response to a low-order bit data of the grayscale data.

According to an embodiment of the present invention, a width and a length of a channel of the transistor M 21 is set such that the transistor M 21 outputs a unit current I of a grayscale range that corresponds to the reference voltage V R , and widths and lengths of channels of the transistors M 22 -M 24 are set such that transistors M 22 -M 24 output 2 times, 4 times, and 8 times the unit current I, respectively.

In more detail, a width-to-length ratio between the channel of the transistor M 21 and the channel of each of the transistors M 11 -M 14 included in the reference current output unit 231 is set to be one to sixteen (1:16), and the width and the length of the channels of the transistors M 22 -M 24 are respectively set to be 2 times, 4 times, and 8 times the width and length of the channel of the transistor M 21 .

Thus, when the grayscale data of the first grayscale range is input, the multiplexer 232 selects the reference voltage V R1 and transmits the selected reference voltage V R1 to the fine current output unit 233 , and a current corresponding to 0 to 15 times the unit current I 1 is output as the fine current ΔI by the switches SW 21 -SW 24 being turned on/off by a low-order bit data of the grayscale data.

In a like manner, when grayscale data of the second to the fourth grayscale ranges are input, the multiplexer 232 selects one of the reference voltages V R2 -V R4 and transmits the selected reference voltage to the fine current output unit 233 , and currents corresponding to 0 to 15 times the respective unit currents I 2 -I 4 are output as the fine currents ΔI by the switches SW 21 -SW 24 being turned on/off by low-order bit data of the grayscale data.

As described above, a grayscale current that reflects nonlinear gamma characteristics may be output by dividing grayscales using a high-order bit data of grayscale data and outputting a fine current in an associated grayscale range using a low-order bit data of the grayscale data.

In FIG. 6 , the transistors M 11 -M 14 , M 21 -M 24 are provided as a MOS transistor of a P-type channel, and a power source VDD is applied to a source of the MOS transistor, but it should be understood that the present invention is not limited thereto. Thus, the transistors M 11 -M 14 , M 21 -M 24 may be provided as an N-type channel MOS transistor according to another embodiment of the present invention.

A D/A converter (e.g., the D/A converter DACm) according to a second embodiment of the present invention will now be described with reference to FIG. 7 .

FIG. 7 illustrates the D/A converter (e.g., the D/A converter DACm) according to the second embodiment of the present invention.

The D/A converter (e.g., the D/A converter DACm) in the second embodiment is a current mirror D/A converter that uses a reference current in contrast with the D/A converter in the first embodiment of the present invention.

In more detail, the current mirror D/A converter of FIG. 7 includes a reference current output unit 231 ′, a fine current output unit 233 ′, a first multiplexer 234 , and a second multiplexer 235 according to the second embodiment of the present invention.

The reference current output unit 231 ′ includes a current mirror circuit formed by transistors M 11 ′, M 12 ′, M 31 , and M 32 , and the first multiplexer 234 .

The first multiplexer 234 selects a current that corresponds to a high-order bit data of the grayscale data from four currents (I R1 -I R3 and Ioffset), and applies the selected current to the transistors M 31 and M 32 .

Since gates of the transistors M 31 , M 32 and gates of the transistors M 11 ′, M 12 ′ are coupled to each other and form the current mirror circuit, a current flowing to/from the first transistors M 11 ′ and M 12 ′ is substantially equivalent to the selected current.

Thus, the reference current output unit 231 ′ outputs the offset current I offset when the high-order bit data is ‘00’, and outputs the reference currents I R1 -I R3 when the high-order bit data are ‘01’, ‘10’, and ‘11’, respectively.

The second multiplexer 235 selects a unit current that corresponds to the high-order bit data of the grayscale data from unit currents I 1 -I 4 and applies the selected unit current to the fine current output unit 233 ′.

In other words, the unit current I 1 is output when the high-order bit data of the grayscale data is ‘00’, and the unit currents I 2 -I 4 are output when the high-order bit data are ‘01’, ‘10’, and ‘11’, respectively.

The fine current output unit 233 ′ includes transistors M 41 and M 42 coupled between a power source VDD and the second multiplexer 235 , transistors M 21 ′-M 28 ′ copying currents flowing to/from the transistors M 41 and M 42 , and switches SW 21 ′-SW 24 ′ being turned on/off by a low-order bit data of the grayscale data.

The transistors M 21 ′ and M 25 ′ are coupled in series between the power source VDD and the switch SW 21 ′, and gates of the transistors M 21 ′ and M 25 ′ are respectively coupled to gates of the transistors M 41 and M 42 such that the currents flowing to/from the transistors M 41 and M 42 are copied.

According to an embodiment of the present invention, a width-to-length ratio of channels of the transistors M 21 ′ and M 25 ′ is set to be substantially equivalent to that of the transistors M 41 and M 42 .

In a like manner, the transistors M 22 ′ and M 26 ′, the transistors M 23 ′ and M 27 ′, and the transistors M 24 ′ and M 28 ′ are respectively coupled in series between the power source VDD and the switches SW 22 ′-SW 24 ′, and lengths and widths of channels of the transistors M 22 ′ and M 26 ′, the transistors M 23 ′ and M 27 ′, and the transistors M 24 ′ and M 28 ′ are respectively set to output 2 times, 4 times, and 8 times the current flowing to/from the transistors M 41 and M 42 .

With this configuration, a fine current ΔI within a grayscale range may be output by turning on/off the switches SW 21 ′-SW 24 ′ by using the low-order bit data of the grayscale data.

The current mirror D/A converter of FIG. 7 may also include a sample/hold circuit (not shown) that samples and holds a grayscale current output from the D/A converter.

In this case, output currents of a plurality of D/A converters DAC 1 -DACm are sampled and held on each data line D 1 -Dm at a substantially equivalent period.

According to an embodiment of the present invention, a grayscale data is divided into a plurality of grayscale ranges by using a high-order bit data of the grayscale data, and a fine current of each grayscale range is generated by using a low-order bit data of the grayscale data such that a grayscale current that satisfies a nonlinear characteristic of the gamma curve may be applied to pixel circuits.

While the invention has been described in connection with certain exemplary embodiments, it is to be understood by those skilled in the art that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications included within the spirit and scope of the appended claims and equivalents thereof.