Gray-scale current generating circuit, display device using the same, and display panel and driving method thereof

This application claims priority to and the benefit of Korean Patent Applications Nos. 10-2004-0080384 and 10-2004-0080388 filed in the Korean Intellectual Property Office on the same date of Oct. 8, 2004, the entire contents of which are incorporated herein by reference.

The present invention relates to a display device. More particularly, the present invention relates to a grayscale current generating circuit and an organic light emitting diode (herein referred to as OLED) display using the same, and a display panel and a driving method thereof.

In general, an OLED display is a display device that electrically excites fluorescent organic material for emitting light and displays an image by voltage programming or current programming N×M organic light emitting cells. An organic light emitting cell of the OLED display includes an anode (which may be made from indium tin oxide, or ITO), an organic thin film, and a cathode layer (which may be metal). The organic thin film has a multi-layer structure including an emitting layer (herein referred to as EML), an electron transport layer (herein referred to as ETL), and a hole transport layer (herein referred to as HTL) so as to balance electrons and holes to thereby enhance light emitting efficiency. Further, the organic thin film separately includes an electron injection layer (herein referred to as EIL) and a hole injection layer (herein referred to as HIL).

Methods of driving the organic light emitting cells having the foregoing configuration include a passive matrix method and an active matrix method employing a thin film transistor (herein referred to as TFT) or a metal-oxide semiconductor field-effect transmitter (herein referred to as MOSFET). In the passive matrix method, an anode and a cathode are formed crossing each other, and a line is selected to drive the organic light emitting cells. In the active matrix method, an indium tin oxide (herein referred to as ITO) pixel electrode is coupled to the TFT, and the light emitting cell is driven by a voltage maintained by capacitance of a capacitor. Herein, the active matrix method can be classified as a voltage programming method or a current programming method depending on the type of signals transmitted to the capacitor to distinctively control the voltage applied to the capacitor.

A pixel circuit according to a conventional voltage programming method has difficulties in expressing high-level gray scales due to deviations of threshold voltages VTHs of TFTs and/or mobilities of carriers of the TFTs, the deviations being generated as a result of a non-uniform manufacturing process of the TFTs. On the other hand, although currents and/or voltages supplied driving transistors in a plurality of pixel circuits may not be uniform, a pixel circuit employing a current programming method can provide panel uniformity as long as a current supplied from a current source to the pixel circuits is uniform.

When utilizing a display device by using the pixel circuit that employs the current programming method, a grayscale current generating circuit is required to convert grayscale data into a grayscale current to apply the grayscale current to the pixel circuit.

The above information disclosed in this Background of the Invention section is only for enhancement of understanding of the background of the invention and therefore, unless explicitly described to the contrary, it should not be taken as an acknowledgment or any form of suggestion that this information forms the prior art that is already known in this country to a person skilled in the art.

An embodiment of the present invention provides a grayscale current generating circuit and an organic light emitting diode (herein referred to as OLED) display using the same, and a display panel and a driving method thereof for outputting a grayscale current corresponding to a grayscale data.

An exemplary display device according to an embodiment of the present invention includes a display unit, a data driver, and a scan driver. In this embodiment, the display unit includes a plurality of data lines for transmitting a data current, a plurality of scan lines for transmitting a selection signal, and a plurality of pixel areas defined by the data lines and the scan lines. The data driver transforms a plurality of grayscale data into the data current and applies the data current to the data lines. The scan driver sequentially applies the selection signal to the plurality of scan lines. In this embodiment, the data driver includes a first current generator for generating a plurality of first currents and a plurality of digital/analog (herein referred to as D/A) converters. The D/A converters include a plurality of current sample/hold circuits for respectively sampling/holding the first currents and outputting a plurality of second currents corresponding to the sampled/held first currents in response to at least one of the plurality of grayscale data.

In one embodiment, the data driver further includes a shift register for sequentially delaying a first signal for as much as a first period and generating a plurality of the second signals.

In one embodiment, the plurality of the current sample/hold circuits store a first voltage corresponding to the plurality of the first currents in response to the second signals, and output the plurality of second currents corresponding to the first voltage in response to the at least one of the plurality of grayscale data.

In one embodiment, the plurality of the current sample/hold circuits output the plurality of second currents in response to respective bits of the at least one of the plurality of grayscale data.

In one embodiment, at least one of the current sample/hold circuits includes a transistor, a capacitor, a first switch, and a second switch. In this embodiment, the transistor includes a first electrode, a second electrode coupled to a power source, and a third electrode, and outputs a current corresponding to a voltage applied between the first electrode and the second electrode to the third electrode. The capacitor is coupled between the first and second electrodes of the transistor. The first switch allows the transistor to be diode-connected in response to a respective one of the second signals, and allows a respective one of the first currents to flow through the transistor. The second switch outputs a current flowing through the transistor in response to the at least one of the plurality of grayscale data.

In one embodiment, the number of the first currents generated by the first current generator is the same as the number of bits of the at least one of the plurality of grayscale data. An exemplary display device according to an embodiment of the present invention includes a display unit, a first shift register, a first latch, a grayscale current generator, and an output unit. In this embodiment, the display unit includes a plurality of data lines for transmitting a data current, a plurality of scan lines for transmitting a selection signal, and a plurality of pixel areas defined by the data lines and the scan lines. The first shift register sequentially delays a first signal for as much as a first period and generates a plurality of second signals. The first latch latches a plurality of the grayscale data in synchronization with the second signals and outputs the latched grayscale data. The grayscale current generator receives the plurality of the grayscale data and outputs the data current corresponding to the grayscale data. The output unit applies the data current output by the grayscale current generator to the plurality of the data lines.

In this embodiment, the grayscale current generator includes a bias current generator for generating a plurality of bias currents and a plurality of digital/analog (herein referred to as D/A) converters for using the plurality of the bias currents. The D/A converters include a plurality of current sample/hold circuits for respectively sampling/holding the plurality of the bias currents and output the bias currents in response to each bit of at least one of the plurality of grayscale data.

In one embodiment, the grayscale current generator further includes a second shift register for delaying a third signal for as much as a second period and generates a plurality of fourth signals, and the D/A converters use the bias-currents in synchronization with the fourth signals.

An exemplary display panel according to an embodiment of the present invention includes a display unit, a first current generator, and a plurality of current sample/hold circuits. In this embodiment, the display unit includes a plurality of pixels for displaying an image in response to an applied data current. The first current generator generates a plurality of first currents which are different from each other. Each of the plurality of current sample/hold circuits stores a first voltage corresponding to a respective one of the first currents, and outputs a second current corresponding to the first voltage in response to applied grayscale data.

In one embodiment, the first current generator generates the first currents in response to each bit of the grayscale data.

In one embodiment, the display panel further includes a shift register for delaying sequentially a first signal for as much as a first period and generating a plurality of a second signals. In one embodiment, at least one of the current sample/hold circuits includes a transistor, a capacitor, a first switch, and a second switch. The transistor includes a first electrode, a second electrode coupled to a power source, and a third electrode. The transistor outputs a current corresponding to a voltage applied between the first electrode and the second electrode to the third electrode. The capacitor is coupled between the first electrode and the second electrode of the transistor. The first switch allows the transistor to be diode-connected in response to a respective one of the second signals, and allows a respective one of the first current to flow through the transistor. The second switch outputs a current flowing through the transistor in response to the grayscale data.

In one embodiment, one of the current sample/hold circuit outputs the second current in response to a bit of the grayscale data.

According to an embodiment of the present invention, an exemplary grayscale current generating circuit for converting a digital grayscale data into a grayscale current and outputting the grayscale current includes a first current generator, a plurality of current sample/hold circuits, and a current summing unit. In this embodiment, the first current generator outputs a plurality of first currents which are different from each other. The plurality of current sample/hold circuits respectively sample/hold the first currents and output the sampled/held first currents in response to each bit of the grayscale data. The current summing unit adds up the first currents sampled/held respectively by the plurality of current sample/hold circuits and outputs the added up first currents as the grayscale current.

In one embodiment, the number of the current sample/hold circuits is same as the number of bits of the grayscale data.

In one embodiment, at least one of the current sample/hold circuits includes a transistor, a capacitor, a first switch, and a second switch. The transistor includes a first electrode, a second electrode coupled to a power source, and a third electrode, and outputs a current corresponding to a voltage applied between the first electrode and the second electrode to the third electrode. The capacitor is coupled between the first electrode and the second electrode of the transistor. The first switch allows the transistor to be diode-connected in response to a control signal, and allows a respective one of the first currents to flow through the transistor. The second switch outputs a current flowing through the transistor in response to the grayscale data.

According to an embodiment of the present invention, an exemplary display panel driving method for driving a display panel which includes a plurality of pixel circuits for displaying an image in response to an applied data current. In the method, a plurality of first currents, which are different from each other, are generated. The first currents are sampled, and a plurality of the first voltages corresponding to the first currents are stored respectively. A plurality of the second currents corresponding to the plurality of the first voltages are sampled/held in response to grayscale data. The second currents are added up, and the added up second currents are outputted as the data current.

In one embodiment, during the sampling/holding of the plurality of second currents, the second currents corresponding to the first voltages are output in response to each bit of the grayscale data.

In one embodiment, in the generating of the plurality of first currents, the first currents correspond to each bit of the grayscale data, and the first currents are generated to correspond in number to bits of the grayscale data.

An exemplary display device according to an embodiment of the present invention includes a display unit, a data driver, and a scan driver. In this embodiment, the display unit includes a plurality of data lines for transmitting a data current, a plurality of scan lines for transmitting a selection signal, and a plurality of pixel areas defined by the data lines and the scan lines. The data driver transforms a plurality of grayscale data into the data current and applies the data current to the data lines. The scan driver sequentially applies the selection signal to the plurality of scan lines. In this embodiment, the data driver includes a plurality of digital/analog (herein referred to as D/A) converter groups for receiving a plurality of first currents which are different from each other and outputs the data current corresponding to the grayscale data. The D/A converter group includes a first D/A converter for receiving the first currents and outputting the data current corresponding to the grayscale data, and a second D/A converter for receiving a first voltage corresponding to the first currents and outputting the data current corresponding to the grayscale data.

In one embodiment, the first D/A converter samples/holds the first currents and stores a second voltage corresponding to the first currents, and includes a plurality of first sample/hold circuits for outputting a second current corresponding to the second voltage in response to at least one of the plurality of grayscale data.

In one embodiment, at least one of the first sample/hold circuits includes a first transistor, a first switch, a second switch, a first capacitor, and a third switch. The first transistor includes a first electrode, a second electrode, and a third electrode, and outputs a current corresponding to a voltage applied between the first electrode and the second electrode to the third electrode. The first switch allows the first transistor to be diode-connected in response to a respective one of a plurality of second signals. The second switch transmits a respective one of the first currents to the first transistor in response to the respective one of the second signals. The first capacitor stores the second voltage corresponding to the respective one of the first currents. The third switch outputs at least a part of the second current corresponding to the second voltage in response to the at least one of the plurality of grayscale data.

In one embodiment, the second D/A converter includes a plurality of the second sample/hold circuits for storing a third voltage corresponding to the first currents and outputs a third current corresponding to the third voltage in response to at least another one of the plurality of grayscale data.

In one embodiment, at least one of the second sample/hold circuits includes a second transistor, a second capacitor, and a fourth switch. The second transistor includes a first electrode coupled to the first electrode of the first transistor, a second electrode, and a third electrode, and outputs a current corresponding to a voltage applied between the first electrode and the second electrode to the third electrode. The second capacitor is coupled between the first and second electrodes of the second transistor and stores the third voltage corresponding to the first currents. The fourth switch outputs at least a part of the third current corresponding to the voltage stored in the second capacitor in response to the at least another one of the plurality of grayscale data.

In one embodiment, the number of the first and the second sample/hold circuits are the same and are each also the same as the number of bits of the at least one and another one of the plurality of grayscale data, respectively; and the first and second sample/hold circuits respectively output the second and third currents in response to the bits of the at least one and another one of the plurality of grayscale data.

An exemplary display device according to an embodiment of the present invention includes a display unit, a first shift register, a first latch, a grayscale current generator, and an output unit. The display unit includes a plurality of data lines for transmitting a data current, a plurality of scan lines for transmitting a selection signal, and a plurality of pixel areas defined by the data lines and the scan lines. The first shift register sequentially delays a first signal for as much as a first period and generates a plurality of second signals. The first latch latches a plurality of the grayscale data in synchronization with the second signals and outputs the latched grayscale data. The grayscale current generator receives the plurality of the grayscale data and outputs the data current corresponding to the grayscale data. The output unit applies the data current output by the grayscale current generator to the plurality of the data lines.

In this embodiment, the grayscale current generator includes a bias current generator for generating a plurality of bias currents and a plurality of digital/analog (D/A) converter groups for using the plurality of the bias currents and outputting the data current corresponding to the grayscale data. One of the D/A converter groups includes a first D/A converter for receiving the bias currents and outputting the data current corresponding to the grayscale data, and a second D/A converter for receiving a first voltage corresponding to the bias currents and outputting the data current corresponding to the grayscale data.

In one embodiment, the grayscale current generator further includes a second shift register for delaying a third signal for as much as a second period and generating a plurality of fourth signals, and the first D/A converter uses the bias currents in response to the fourth signals.

In one embodiment, the first D/A converter includes a plurality of the first sample/hold circuits for sampling the bias currents in response to the fourth signals and outputs the sampled bias currents in response to at least one of the plurality of grayscale data. The second D/A converter includes a plurality of the second sample/hold circuits for receiving the first voltage corresponding to the bias currents and outputting a current corresponding to the first voltage in response to at least another one of the plurality of grayscale data.

An exemplary display panel according to an embodiment of the present invention includes a display unit, a first current generator, a plurality of first current sample/hold circuits, and a plurality of second current sample/hold circuits. The display unit includes a plurality of pixels for displaying an image in response to an applied data current. The first current generator generates a plurality of first currents which are different from each other. The plurality of first current sample/hold circuits respectively store a first voltage corresponding to the first currents, and respectively output a second current corresponding to the first voltage in response to a first grayscale data. The plurality of second current sample/hold circuits copy the first currents, store a second voltage corresponding to the first currents, and output a third current corresponding to the second voltage in response to a second grayscale data.

In one embodiment, the display panel further includes a shift register for delaying sequentially a first signal for as much as a first period and generating a plurality of the second signals.

In one embodiment, the first current sample/hold circuits store the first voltage corresponding to the first currents in response to the second signals. According to an embodiment of the present invention, an exemplary grayscale current generating circuit for transforming a digital grayscale data into a grayscale current and outputting the grayscale current includes a first current generator, a plurality of first current sample/hold circuits, and a plurality of second current sample/hold circuits. The first current generator outputs a plurality of first currents which are different from each other. The plurality of first current sample/hold circuits sample/hold the first currents and output a second current corresponding to the sampled/held first currents in response to each bit of a first grayscale data.

The plurality of second current sample/hold circuits copy the first currents and output a third current corresponding to the copied first currents in response to each bit of a second grayscale data.

In one embodiment, the number of the first and second sample/hold circuits are the same as the number of bits of the first and second grayscale data, respectively.

In one embodiment, at least one of the first sample/hold circuit includes a first transistor, a first switch, a second switch, a first capacitor, and a third switch. The first transistor includes a first electrode, a second electrode, and a third electrode, and outputs a current corresponding to a voltage applied between the first electrode and the second electrode to the third electrode. The first switch allows the first transistor to be diode-connected in response to a control signal. The second switch transmits a respective one of the first currents to the first transistor in response to the control signal. The first capacitor stores the first voltage corresponding to the respective one of the first currents. The third switch outputs at least a part of the second current corresponding to the first voltage in response to the first grayscale data.

In one embodiment, at least one of the second sample/hold circuits includes a second transistor, a second capacitor, and a fourth switch. The second transistor includes a first electrode, a second electrode, and a third electrode, and outputs a current corresponding to a voltage applied between the first electrode and the second electrode to the third electrode. The second capacitor is coupled between the first and second electrodes of the second transistor and stores a second voltage corresponding to the first currents. The fourth switch outputs at least a part of the third current corresponding to the second voltage stored in the second capacitor in response to the second grayscale data.

According to an embodiment of the present invention, an exemplary display panel driving method for driving a display panel comprising a plurality of pixel circuits for displaying an image in response to an applied data current. In the method, a) a plurality of first currents which are different from each other are sampled, and a plurality of first voltages corresponding respectively to the first currents are stored; b) the first currents are copied, and a plurality of second voltages corresponding to the first currents are stored respectively; c) a plurality of the second currents corresponding to the first voltages are output in response to a first grayscale data representing a grayscale of a first pixel among the plurality of the pixels; d) a plurality of third currents corresponding respectively to the second voltages are outputted in response to a second grayscale data representing a grayscale of a second pixel among the plurality of the pixels; and e) the second and third currents are respectively applied to the first and second pixels.

In one embodiment, in c), the second currents corresponding to the first voltages are output in response to each bit of the first grayscale data, and in d), the third currents corresponding to the second voltages are output in response to each bit of the second grayscale data.

In one embodiment, the number of the first currents is same as the number of bits of the first grayscale data, and the first currents correspond to each bit of the first grayscale data.

FIG. 1 is a top plan view of an OLED display according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a data driver according to an embodiment of the present invention.

FIG. 3 is a block diagram illustrating a grayscale current generator according to a first embodiment of the present invention.

FIG. 4 shows an exemplary current sample/hold circuit used for a digital/analog (D/A) converter shown in FIG. 3 .

FIG. 5 is a detailed circuit diagram of the D/A converter according to the first embodiment of the present invention.

FIG. 6 is a block diagram illustrating a grayscale current generator according to a second embodiment of the present invention.

FIG. 7 shows an exemplary current sample/hold circuit used for a D/A converter shown in FIG. 6 .

FIG. 8 is a circuit diagram illustrating a D/A converter group according to the second embodiment of the present invention.

Certain embodiments of the present invention will hereinafter be described in detail with reference to the accompanying drawings.

In the following description, when it is described that an element is coupled to another element, the element may be directly coupled to the other element or coupled to the other element through a third element. Like reference numerals designate like elements throughout the specification. In addition, in exemplary embodiments of the present invention, when it is described that a current is output from a first driver to a second driver, a direction of the current may differ according to a type of the first driver. In more detail, an output current of the first driver flows from the first driver to the second driver when the first driver is a source-type driver, and an output current flows from the second driver to the first driver when the first driver is a sink-type driver.

In the following description according to certain embodiments of the present invention, an organic light emitting diode display (hereinafter, OLED display) using an electro-luminescence of organic material will be exemplified as a display device.

FIG. 1 is a top plan view of an OLED display according to an embodiment of the present invention. As shown in FIG. 1 , the OLED display according to an embodiment of the present invention includes a substrate 1000 for forming a display panel. The substrate 1000 includes a display unit 100 on which an actual image is displayed and a peripheral part on which no image is displayed. On the peripheral part, a data driver 200 , and scan drivers 300 , 400 are formed.

The display unit 100 includes a plurality of data lines D 1 to D m , a plurality of scan lines S 1 to S n , a plurality of light emission scan lines E 1 to E n , and a plurality of pixels 110 . The data lines D 1 to D m are extended in a column direction, and are for transmitting a data current for representing an image to a pixel 110 . The scan lines S 1 to S n and the light emission scan lines E 1 to E n are extended in a row direction, and respectively are for transmitting a selection signal and a light emission signal to the pixel 110 . A pixel area is defined by one data line and one scan line.

The data driver 200 applies the data current (or a plurality of data currents) to the data lines D 1 to D m . The scan driver 300 sequentially applies the selection signal (or a plurality of selection signals) to the plurality of scan lines S 1 to S n , and the scan driver 400 sequentially applies the light emission control signal (or a plurality of light emission control signals) to the plurality of light emission scan lines E 1 to E n .

The data driver 200 and/or the scan drivers 300 , 400 may be directly built on the substrate 1000 , as a form of an integrated circuit. Alternatively, the drivers 200 , 300 , and/or 400 may be formed on the same layer of the substrate 1000 in which the data lines D 1 to D m , scan lines S 1 to S n , light emission scan lines E 1 to E n , and transistors of the pixels (or pixel circuits) are formed. Alternatively, the drivers 200 , 300 , and/or 400 may be formed on another separate substrate rather than the substrate 1000 , and the separate substrate may be coupled with the substrate 1000 . The drivers 200 , 300 , and/or 400 may be mounted as a chip on a tape carrier package (TCP), a flexible printed circuit (FPC), or a tape automatic bonding (TAB) attached and electrically coupled to the substrate 1000 .

FIG. 2 is a block diagram illustrating the data driver 200 according to an embodiment of the present invention.

As shown in FIG. 2 , the data driver 200 includes a shift register (or a first shift register) 210 , a latch (or a first latch) 220 , a grayscale current generator 230 , and an output unit 240 .

The shift register 210 sequentially shifts a start signal SP in synchronization with a clock signal Clk and outputs the start signal SP as a plurality of shifted start signals. The latch 220 latches a plurality of video signals in synchronization with the output signals of the shift register 210 , and outputs the video signals.

The grayscale current generator 230 receives the video signals output from the latch 220 , and generates grayscale currents I D1 to I Dm corresponding to the video signals.

The output unit 240 applies the grayscale currents I D1 to I Dm output form the grayscale current generator 230 to the data lines D 1 to D m , respectively. The output unit 240 may be formed as a buffer circuit which is coupled with a terminal of the grayscale current generator 230 and the data lines D 1 to D m and is placed therebetween.

Referring now to FIGS. 3 , 4 and 5 , a grayscale current generator according to a first embodiment of the present invention will be described. For better understanding and ease of description, the video signal is assumed to be grayscale data of six (6) bits, but the present invention is not thereby limited.

FIG. 3 is a block diagram illustrating the grayscale current generator (e.g., the grayscale current generator 230 ) according to a first embodiment of the present invention.

As shown in FIG. 3 , the grayscale current generator (e.g., the grayscale current generator 230 ) according to the first embodiment of the present invention includes a shift register (or a second shift register) 231 , a bias current generator 232 , D/A converters DAC 1 to DAC m , and a latch (or a second latch) 233 . In FIG. 3 , the bias current generator 232 is illustrated as a sink-type driver.

The shift register 231 sequentially shifts a start signal (not shown) in synchronization with a clock signal (not shown) and outputs a plurality of shifted start signals SR 1 to SR m , so that the D/A converters DAC 1 to DAC m may sequentially receive bias currents I B1 to I B6 .

The bias current generator 232 generates the bias currents I B1 to I B6 corresponding to the number of bits of grayscale data, and outputs them to the D/A converters DAC 1 to DAC m . According to an embodiment of the present invention, the bias current I B2 is set to be substantially at two (2) times the bias current I B1 , and the bias currents I B3 to I B6 are respectively set to be substantially at four (4) times, eight (8) times, 16 times, and 32 times the bias current I B1 .

The D/A converters DAC 1 to DAC m convert the grayscale data into analog currents I out1 to I outm in synchronization with the output signals SR 1 to SR m of the shift register 231 . The D/A converters DAC 1 to DAC m include as many current sample/hold circuits as the number of bits of the grayscale data. The 6 current sample/hold circuits included in one D/A converter respectively sample/hold the bias currents I B1 to I B6 , and output the sampled/held currents in response to each bit of the grayscale data.

FIG. 4 is showing a current sample/hold circuit of the DAC 1 which samples/holds a current corresponding to a first bit of the grayscale data, according to the first embodiment of the present invention.

As shown in FIG. 4 , the current sample/hold circuit includes a transistor M 11 , a capacitor C 11 , and switches SW 11 , SW 12 , SW 13 .

The transistor M 11 is formed of a MOS transistor of a P-type channel (e.g., a PMOS), and a source of the transistor M 11 is coupled to a source voltage VDD. The capacitor C 11 is coupled between a gate and the source of the transistor M 11 .

The switch SW 11 is coupled between a drain and the gate of the transistor M 11 , and is turned on in response to the output signal SR 1 of the shift register 231 .

The switch SW 12 is coupled between an output terminal of the bias current generator 232 and the drain of the transistor M 11 , and is turned on in response to the output signal SR 1 of the shift register 231 .

The switch SW 13 is coupled between the drain of the transistor M 11 and the output terminal of the D/A converter DAC 1 , and is turned on in response to the first bit of the grayscale data.

Accordingly, when the output signal SR 1 is input from the shift register 231 , to turn on the switch SW 11 , the transistor M 11 is set to be diode-connected. Then switch SW 12 is turned on, and the bias current I B1 is transmitted to the transistor M 11 . Therefore, a voltage corresponding to the bias current I B1 is stored in the capacitor C 11 .

Thereafter, the grayscale data is applied to the switch SW 13 , and the switch SW 13 is turned on when the first bit of the grayscale data is given to be 1. Then, a current corresponding to the voltage stored in the capacitor C 11 flows to the output terminal of the D/A converter DAC 1 through the transistor M 11 . When the first bit of the grayscale data is given to be 0, the switch SW 13 is turned off, and the current from the transistor M 11 is cut off.

This current sample/hold circuit described above is formed as many times as the number of bits of the grayscale data. The first to sixth bits of the grayscale data are applied to a switch (e.g., the switch SW 13 ) of each current sample/hold circuit, so that the grayscale currents I D1 to I Dm corresponding to the 6-bit grayscale data may be outputted.

FIG. 5 is a circuit diagram for the D/A converter according to the first embodiment of the present invention, and shows representatively the D/A converter DAC 1 among the D/A converters DAC 1 to DAC m .

The D/A converter DAC 1 includes 6 current sample/hold circuits. Each current sample/hold circuit samples/holds a respective one of the bias currents I B1 to I B6 , and outputs the bias currents I B1 to I B6 to the output terminal in response to the bits of the grayscale data.

In more detail, when the output signal SR 1 is applied from the shift register 231 , switches SW 11 to SW 61 of the 6 current sample/hold circuits are turned on, transistors M 11 to M 61 are diode-connected, switches SW 12 to SW 62 are turned on, and the bias currents I B1 to I B6 flow through the transistors M 11 to M 61 . Therefore, voltages corresponding to the bias currents I B1 to I B6 are respectively stored in capacitors C 11 to C 61 .

When each bit of grayscale data is applied to the 6 switches SW 13 to SW 63 of the current sample/hold circuits, each of the 6 current sample/hold circuits outputs a current corresponding to the voltages stored in a respective one of the capacitors C 11 to C 61 in response to the grayscale data.

For example, when the grayscale data is given to be 001010, the switches SW 23 , and SW 43 of the second and the fourth current sample/hold circuits are turned on, and currents I out1 [ 1 ], and I out1 [ 3 ] corresponding to the voltages stored in the capacitors C 21 and C 41 are output.

While the output signals SR 1 to SR m from the shift register 231 are sequentially applied to a plurality of the D/A converters DAC 1 to DAC m , a plurality of the grayscale data are applied to the corresponding D/A converters DAC 1 to DAC m , and the D/A converters DAC 1 to DAC m sequentially output the currents corresponding to the grayscale data in synchronization with the output signals SR 1 to SR m of the shift register.

In the D/A converter according DAC 1 to an embodiment of the present invention, the bias current generator 232 generates the 6 bias currents I B1 to I B6 corresponding to each bit of the grayscale data, and outputs the 6 bias currents I B1 to I B6 to the 6 current sample/hold circuits. Therefore, a deviation of a the holding current due to the characteristics of the transistors M 11 to M 61 can be less than a comparison example for inputting one bias voltage or bias current and holding a plurality of currents which are different from each other.

That is, in the comparison example, by using one bias voltage or one bias current and controlling channel widths and channel lengths of six transistors included in the current sample/hold circuits, the respective current sample/hold circuits may sample and/or hold different currents. However, in the comparison example, a desired current may not be held due to the deviations of the six transistors.

Therefore, according to an embodiment of the present invention, characteristics of transistors M 11 to M 61 included in the current sample/hold circuits are set to be substantially the same. The bias current generator 232 generates a plurality of bias currents and transmits the plurality of bias currents to the current sample/hold circuits, so that the difference in the currents due to the deviations of the transistors M 11 to M 61 can be prevented and/or compensated.

However, in the grayscale current generator according to the first embodiment of the present invention, a sampling interval for each of the D/A converters DAC 1 to DAC m may be excessively short because the bias current generator 232 needs to generate the bias currents I B1 to I B6 and to sequentially apply the bias currents to D/A converters DAC 1 to DAC m . In more detail, while the selection signals are sequentially applied to the scan lines S 1 to S n , the output unit (or latch) 233 needs to apply data currents to the data lines D 1 to D m . So, during a horizontal period, all the D/A converters DAC 1 to DAC m have to sample/hold the bias currents I B1 to I B6 , and output grayscale currents corresponding to the grayscale data to the output unit 233 .

Therefore, there occurs a possibility that a current sample/hold circuit included in the D/A converter would hold a current even when the current sample/hold circuit has not sufficiently charged the voltage corresponding to a respective one of the bias currents I B1 to I B6 in a pre-allocated interval.

In an enhancement of the first embodiment, a grayscale current generator (e.g., grayscale current generator 230 ) according to a second embodiment of the present invention divides the D/A converters DAC 1 to DAC m into a plurality of groups, and D/A converters belonging to a certain group are controlled to perform a sampling/holding in substantially simultaneous time, so that a time for sampling may be assured.

Hereinafter, referring to FIG. 6 to FIG. 8 , the grayscale current generator (e.g., the grayscale current generator 230 ) according to the second embodiment of the present invention will be described.

FIG. 6 is a block diagram illustrating the grayscale current generator according to the second embodiment of the present invention.

As shown in FIG. 6 , the grayscale current generator (e.g., the grayscale current generator 230 ) according to the second embodiment of the present invention is different from the grayscale current generator according to the first embodiment of the present invention in that the second embodiment divides a plurality of the D/A converters DAC 1 to DAC m into at least two groups to transmit the bias currents.

The output signals SR 1 to SR i of the shift register 231 are applied to one of a plurality of D/A converters included in each group, and the bias current I B1 to I B6 are transmitted to the D/A converter to which the output signal of shift register 231 is applied.

In more detail, as shown in FIG. 6 , when two D/A converters (e.g., DAC 1 and DAC 2 ) are set to be one group 234 , the output signals SR 1 to SR i of the shift register 231 may be applied to the first D/A converter DAC 2i-1 (e.g., DAC 1 or DAC m-1 ) included in each group, the D/A converter DAC 2i-1 receives the bias currents I B1 to I B6 , and the D/A converter DAC 2i (e.g., DAC 2 or DAC m ) receives the voltage corresponding to the bias currents I B1 to I B6 .

Accordingly, an enable period of the output signals of the shift register 231 according to the second embodiment of the present invention can effectively increase to become substantially two times that of the output signals of the shift register 231 according to the first embodiment of the present invention. Also, sampling period for the bias currents I B1 to I B6 of the D/A converter DAC 1 to DAC m of the second embodiment can effectively increase to become substantially two times the sampling period of the first embodiment.

Hereinafter, a configuration and an operation of the D/A converter of the grayscale current generator according to the second embodiment of the present invention will be described in more detail. For better understanding and ease, it is assumed that one D/A group includes two D/A converters, and the D/A converters DAC 1 and DAC 2 included in a first group will be described mainly as an example among a plurality of the D/A groups.

According to the second embodiment of the present invention, the D/A converter DAC 1 includes 6 current sample/hold circuits; one current sample/hold circuit is formed substantially equivalently as the current sample/hold circuit in FIG. 4 .

In other words, the current sample/hold circuit of the D/A converter DAC 1 includes a transistor M 11 , a capacitor C 11 , and switches SW 11 , SW 12 , SW 13 . The switches SW 11 and SW 12 are turned on in response to the output signal SR 1 of the shift register 231 , the capacitor C 11 stores a voltage corresponding to the bias current flowing through the transistor M 11 . The switch SW 13 is turned on in response to the grayscale data, and then a current corresponding to the voltage stored in the capacitor C 11 is output to the output terminal of the D/A converter DAC 1 .

The D/A converter DAC 2 includes 6 current sample/hold circuits; each current sample/hold circuit copies the bias current flowing in the current sample/hold circuit of the D/A converter DAC 1 , and stores a voltage corresponding to bias current.

FIG. 7 is a circuit diagram showing the current sample/hold circuit of the D/A converter DAC 2 according to the second embodiment of the present invention, and in more detail, illustrates the current sample/hold circuit holding a current corresponding to the first bit of the grayscale data.

As shown in FIG. 7 , the current sample/hold circuit of the D/A converter DAC 2 includes a transistor M 12 , a capacitor C 12 , and switch SW 14 .

A gate of the transistor M 12 is coupled to the gate of the transistor M 11 (not shown). A source of the transistor M 12 is coupled to the power source VDD. The capacitor C 12 is coupled between the gate and a source of the transistor M 12 , and stores a voltage corresponding to a current flowing through the transistor M 12 .

The switch SW 14 is coupled to a drain of the transistor M 12 , and is turned on in response to the first bit of the grayscale data.

According to this configuration, a voltage, which is substantially equivalent to the voltage applied to the gate of the voltage transistor M 1 , is applied to the gate of transistor M 12 , and a current, which is substantially equivalent to the bias current I B1 flowing through the transistor M 11 , may flow through the transistor M 12 .

Therefore, the voltage corresponding to the current flowing through the transistor M 12 is charged in the capacitor C 12 . In addition, when the switch SW 14 is turned on in response to the first bit of the grayscale data, a current corresponding to the voltage stored in the capacitor C 12 is output through the switch SW 14 .

As described above, when the current sample/hold circuit included in the D/A converter DAC 2 is coupled with the current sample/hold circuit included in the D/A converter DAC 1 , the D/A converters DAC 1 , DAC 2 perform substantially simultaneously sampling/holding the bias current.

In other words, a plurality of current sample/hold circuits included in one group perform substantially simultaneously sampling/holding, and output the sampled/held current in response to the applied grayscale data. Here, the grayscale data may be sequentially or simultaneously applied to the two D/A converters DAC 1 and DAC 2 .

FIG. 8 is a circuit diagram illustrating the D/A converters DAC 1 and DAC 2 included in a D/A converter group (e.g., the D/A converter group 234 ) according to the second embodiment of the present invention.

As shown in FIG. 8 , the bias currents I B1 to I B6 are respectively applied to the current sample/hold circuits of the D/A converter DAC 1 , and gates of transistors M 12 to M 62 of the D/A converter DAC 2 are coupled to gates of transistors M 11 to M 61 of the D/A converter DAC 1 , respectively.

Accordingly, a plurality of D/A converters DAC 2i-1 and DAC 2i included in one group substantially simultaneously sample the bias currents I B1 to I B6 , so that sampling time of the current sample/hold circuit may be increased. In addition, the bias current generator 232 sequentially transmits the bias current to each group, so that a deviation of bias currents transmitted to the D/A converters DAC 1 to DAC m may be reduced.

In other words, if the bias currents are transmitted to one D/A converter DAC 1 while voltages corresponding to the bias currents are transmitted to the other D/A converters DAC 2 to DAC m , the deviation of the bias currents transmitted to the D/A converters DAC 1 to DAC m may be increased due to the characteristic deviation of transistors included in the current sample/hold circuits.

Therefore, when the number of D/A converters included in one group is appropriately controlled, the sampling time of the current sample/hold circuit may be assured, and the deviation of the bias currents transmitted to the D/A converters may be reduced.

In view of the foregoing, a grayscale current generating circuit and an organic light emitting diode (OLED) display using the same, and a display panel and a driving method thereof have been described. The embodiments described above are exemplary embodiments which reflect a concept of the present invention. However, it should be understood that the present invention is not limited thereto, since various modification and/or variations may be readily understood by a person skilled in the art to be within the spirit and scope of the present invention.

For example, the circuits described in FIG. 4 and FIG. 7 are used for a current sample/hold circuit included in the D/A converter. However, the scope of the present invention is not limited to a specified current sample/hold circuit. Various current sample/hold circuits can be applied, which can sample the bias current in synchronization with the output signal of the shift register and output the sampled current in response to the grayscale data, or which can copy a current flowing in the current sample/hold circuit and output copied current in response to the grayscale data.

In addition, in FIG. 4 to FIG. 8 , it is described that the transistors of the current sample/hold circuit are P-type channel transistors (e.g., PMOS transistors), but a MOS transistor having an N-type channel (e.g., NMOS transistors) may be used, depending on the embodiments. Moreover, other types of active element which include three electrodes and transmit a current corresponding to a voltage applied between two electrodes to another electrode may be also used.

According to an embodiment of the present invention, a grayscale current generating circuit for outputting a grayscale current corresponding to a grayscale data and a display device using the same and a display panel and a driving method thereof may be provided.

By generating a plurality of the bias currents and applying them to a plurality of the current sample/hold circuits, a deviation of the holding currents due to a deviation of transistors used in the current sample/hold circuit may be reduced.

Furthermore, by dividing a plurality of the D/A converters into a plurality of groups and controlling the D/A converters included in one group to sample substantially simultaneously a bias current, sampling time of a current sample/hold circuit included in the D/A converters may be assured.

While the invention has been described in connection with certain exemplary embodiments, it is to be understood by those skilled in the art that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications included within the spirit and scope of the appended claims and equivalents thereof.