Signal driving circuits

The invention relates to driving circuits, and more particularly, to signal driving circuits with a precise output analog voltage level and high driving capability.

To reduce total module costs and time-to-market of display systems, “system-on-glass” technology of low temperature poly-Si (LTPS) TFTs offers a promising solution due to integration of driving circuit on glass. In conventional display systems, digital-to-analog conversion is the most important part of a signal driving circuit, such as a source/data driver. Typically, a digital-to-analog converter (DAC) requires a unit-gain analog buffer to improve driving capability thereof, as shown in FIG. 8A . However, because TFTs have poor performance, such as poor uniformity and high driving voltage, analog buffers composed of TFTs always have a large DC offset voltage, resulting in large difference between input and output analog voltage levels. If there is no analog buffer at the output of the DAC (as shown in FIG. 8B ), either the driving capability of the DAC is insufficient or the power consumption of R-string voltage reference circuit is high when the DAC is a resistive DAC (R-DAC).

The invention is directed to the broad concept of providing a signal driving circuit that selectively outputs a first analog voltage from a digital-to-analog converter without passing through an analog buffer, or a second analog voltage by an analog buffer according to the first analog voltage, to reduce DC offset, so as to obtain a precise output analog voltage level.

In another aspect, the present invention discloses embodiments of a driving circuit, in which a digital-to-analog converter (DAC) generates a first analog voltage according to digital data, and an output circuit selectively outputs either a second analog voltage, according to the first analog voltage, by an analog buffer or the first analog voltage to the load without passing through an analog buffer.

In a further aspect, the present invention discloses embodiments of a driving circuit, in which a first DAC generates a first analog voltage according to a first digital data and a first set of voltage levels, a first output circuit selectively outputs a second analog voltage by a first analog buffer according to the first analog voltage to a first load or the first analog voltage to the first load without passing through an analog buffer, a second DAC generates a third analog voltage according to a second digital data and a second set of voltage levels, and a second output circuit selectively outputs a fourth analog voltage by a second analog buffer according to the third analog voltage to a second load or the third analog voltage to the second load without passing through an analog buffer.

In another aspect, the present invention discloses embodiments of an electronic device, in which a signal driving circuit mentioned above and a display element are coupled to the signal driving circuit, wherein the display element is driven by the signal driving circuit.

The invention can be more fully understood by the subsequent detailed description and examples with reference made to the accompanying drawings, wherein:

FIG. 1A shows an embodiment of a signal driving circuit of the invention;

FIG. 1B shows another aspect of the embodiment of a signal driving circuit;

FIG. 2 is a timing chart of the signal driving circuit according to the embodiment;

FIG. 3A shows an embodiment of an analog buffer in accordance with one embodiment of the present invention;

FIG. 3B shows another embodiment of an analog buffer;

FIG. 4 shows the timing chart of the embodiment of the signal driving circuit with analog buffers illustrated in FIGS. 3A and 3B above;

FIG. 5A and FIG. 5B show the relationship between the input voltage of the output circuit and DC offset voltage during different time intervals according to simulation of the embodiments;

FIG. 6 is a schematic diagram of a signal driving circuit according to one embodiment of the invention;

FIG. 7 schematically shows an electronic device deploying a driving circuit shown in FIG. 6 ;

FIG. 8A shows digital-to-analog converters connected to analog buffers in a conventional driving circuit; and

FIG. 8B shows digital-to-analog converters without analog buffer in a conventional driving circuit.

FIG. 1A shows an embodiment of a signal driving circuit in accordance with one aspect of the present invention. The signal driving circuit 300 A comprises a voltage reference circuit 12 , three digital-to-analog converters (DACs) 14 R, 14 G and 14 B, and three output circuits 16 R, 16 G and 16 B. The signal driving circuit 300 A can be a portion of a source driver or a data driver in a display system, such as a liquid crystal display system or the like.

As shown in FIG. 1A , the DACs 14 R, 14 G and 14 B are coupled to the analog reference voltage levels V 0 , V 1 , . . . , V 61 , V 62 and V 63 provided from the voltage reference circuit 12 . In this case, the three DACs can be resistive DACs and the voltage reference circuit 12 can be a resistor string (R-string). The DAC 14 R is coupled to the reference voltage levels V 0 ˜V 63 and digital data R 0 ˜R 5 and generates an analog voltage VAR 1 to the output circuit 16 R according thereto. The DAC 14 G is coupled to reference voltage levels V 0 ˜V 63 and digital data G 0 ˜G 5 and generates an analog voltage VAG 1 to the output circuit 16 G according thereto. The DAC 14 B is coupled to the reference voltage levels V 0 ˜V 63 and digital data B 0 ˜B 5 and generates analog voltage VAB 1 to the output circuit 16 B according thereto.

The output circuits 16 R, 16 G and 16 B are coupled between the DACs 14 R, 14 G and 14 B and corresponding loads 17 R, 17 G and 17 B, and output voltages to the corresponding loads according to the analog voltage VAR 1 , VAG 1 and VAB 1 . The output circuit 16 R comprises three switching devices SWR 1 ˜SWR 3 , and an analog buffer 18 R. The switching device SWR 1 is coupled to the node N 1 R and the voltage such as Vee or Vdd in FIG. 3A , the switching device SWR 2 is coupled between the node N 1 R and output of the analog buffer 18 R. In this embodiment of the invention, the voltage Vee can be an appropriate voltage near to ground voltage, the voltage Vdd can be an appropriate voltage near to power voltage, such as Vdd and Vee shown in FIG. 3A for example. The switching device SWR 3 is coupled between the DAC 14 R and the load 17 R, and the analog buffer 18 R is coupled between the switching device SWR 2 and output of the DAC 14 R. The analog buffer 18 R generates an analog voltage VAR 2 according to the analog voltage VAR 1 , to increase the driving capability of the DAC 14 R when the switching SWR 2 is turned on.

The output circuit 16 G comprises three switching devices SWG 1 ˜SWG 3 , and an analog buffer 18 G. The switching device SWG 1 is coupled to the node N 1 G and the voltage (Vee/Vdd), the switching device SWG 2 is coupled between the node N 1 G and output of the analog buffer 18 G. The switching device SWG 3 is coupled between the DAC 14 G and the load 17 G, and the analog buffer 18 G is coupled between the switching device SWG 2 and output of the DAC 14 G. The analog buffer 18 G generates an analog voltage VAG 2 according to the analog voltage VAG 1 , to increase the driving capability of the DAC 14 G when the switching SWG 2 is turned on.

The output circuit 16 B comprises three switching devices SWB 1 ˜SWB 3 , and an analog buffer 18 B. The switching device SWG 1 is coupled to the node N 1 B and the voltage (Vee/Vdd), the switching device SWB 2 is coupled between the node N 1 B and output of the analog buffer 18 B. The switching device SWB 3 is coupled between the DAC 14 B and the load 17 B, and the analog buffer 18 B is coupled between the switching device SWB 2 and output of the DAC 14 B. The analog buffer 18 B generates an analog voltage VAB 2 according to the analog voltage VAB 1 , to increase the driving capability of the DAC 14 B when the switching SWB 2 is turned on.

The controller 50 controls the switching of the various switches. The controller 50 may be part of, or the switch control signal CS 1 may be provided by, the timing controller 510 found in the electronics device (see FIG. 7 ). In the embodiment, the switching device SWR 1 , SWG 1 and SWB 1 are optional and can be omitted based on the corresponding analog buffers 18 R, 18 G and 18 B.

FIG. 2 is a timing chart of the signal driving circuits 300 A and 300 B according to the embodiment. In the time intervals, the various switches are controlled by the controller 50 to function as follows.

During time interval PD 1 , all switches are turned off, except switching devices SWR 1 , SWG 1 and SWB 1 , which are turned on such that voltages at nodes N 1 R, R 1 G and N 1 B from a preceding cycle are discharged to the voltage Vee or precharged to the voltage Vdd. In the embodiment, the time interval PD 1 is optional and can be omitted based on the corresponding analog buffers 18 R, 18 G and 18 B.

During time interval PD 2 , all switches are turned off, except that switching devices SWR 2 , SWG 2 and SWB 2 , which are turned on such that the analog buffers 18 R, 18 G and 18 B are coupled between the corresponding DACs 14 R, 14 G and 14 B and the corresponding loads 17 R, 17 G and 17 B respectively to increase driving capability of the DACs 14 R, 14 G and 14 B. At the same time, the analog buffers 18 R, 18 G and 18 B generate the analog voltages VAR 2 , VAG 2 and VAB 2 to the loads 17 R, 17 G and 17 B respectively according to the voltages VAR 1 , VAG 1 and VAB 1 from the DACs 14 R, 14 G and 14 B. In this embodiment, the voltages VAR 2 , VAG 2 and VAB 2 generated by the analog buffers 18 R, 18 G and 18 B are essentially equal to the voltages VAR 1 , VAG 1 and VAB 1 from the DACs 14 R, 14 G and 14 B respectively.

During time interval PD 3 , all switches are turned off, except that switching devices SWR 3 , SWG 3 and SWB 3 are turned on such that the voltages VAR 1 , VAG 1 and VAB 1 from the DACs 14 R, 14 G and 14 B are output to the loads 17 R, 17 G and 17 B respectively without DC offset voltage caused by analog buffers, thereby increasing precision of analog output voltage level.

FIG. 1B shows a variation of the embodiment of a signal driving circuit. The signal driving circuit 300 B shown in FIG. 1B is similar to the circuit 300 A in FIG. 1A , except for voltage reference circuit 12 ″.

As shown in FIG. 1B , unlike the voltage reference circuit 12 in the driving circuit 300 A, the voltage reference circuit 12 ″ provides reference voltages RV 0 ˜RV 63 , GV 0 ˜GV 63 and BV 0 ˜BV 63 to the DACs 14 R, 14 G and 14 B respectively. The DAC 14 R is coupled to the reference voltage levels VR 0 ˜VR 63 and digital data R 0 ˜R 5 and generates an analog voltage VAR 1 to the output circuit 16 R according thereto. The DAC 14 G is coupled to the reference voltage levels GV 0 ˜GV 63 and digital data G 0 ˜G 5 and generates an analog voltage VAG 1 to the output circuit 16 G according thereto. The DAC 14 B is coupled to the reference voltage levels BV 0 ˜BV 63 and digital data B 0 ˜B 5 and generates an analog voltage VAB 1 to the output circuit 16 B according thereto. Namely, the DACs 14 R, 14 G and 14 B generate the analog voltages VAR 1 , VAG 1 and VAB 1 according to different sets of reference voltages, for gamma correction.

The signal driving circuit 300 B can be a portion of a source driver or a data driver in an OLED display system, and the voltage reference circuit 12 ″ can be three resistor strings (R-strings). Operations of the output circuits 16 R˜ 16 B shown in FIG. 1B are similar to those shown in FIG. 1A , and thus are omitted for simplification.

FIG. 3A shows an embodiment of an analog buffer in accordance with one aspect of the present invention. The analog buffer 18 comprises a first source follower 10 A, a switching circuit 20 A, and a second source follower 30 A.

As shown in FIG. 3A , the first source follower 10 A is a P-type source follower coupled between power voltages Vdd and Vee. The first source follower 10 A comprises two transistors M 1 and M 2 , three switching devices S 1 A, S 1 B and S 3 A, a capacitor C 1 , and a transistor biased by a bias voltage Va. The switching circuit 20 A is coupled between the first and second source followers 10 A and 30 A. The switching circuit 20 A comprises three switching devices S 3 B, S 3 C and S 4 A, and a capacitor C 2 . The second source follower 30 A is an N-type source follower, coupled to the switching circuit 20 A. The second source follower 30 A comprises a transistor M 3 , a switching device S 2 , and a transistor M 5 biased by the bias voltage Va. In this embodiment, the current provided by the transistor MS can be N times that provided by the transistor M 4 , increasing driving capability. The controller 50 also controls switching of the various switches. The controller 50 may be part of, or the switch control signals CS 2 may be provided by, the timing controller 510 found in the electronic device (see FIG. 7 ).

FIG. 4 is a timing chart of the signal driving circuit 300 A employing the analog buffers 18 as shown in FIG. 3A . Referring to FIGS. 1A and 3A , the various switches are controlled by the controller 50 to function as follows.

During time interval t 1 –t 2 (PD 1 ), all switches are turned off, except that switching devices SWR 1 , SWG 1 and SWB 1 in output circuits 16 R, 16 G and 16 B shown in FIG. 1A and the switching device S 1 A and S 1 B in each analog buffer 18 R, 18 G and 18 B shown in FIG. 3A are turned on. Due to turning on of the switching devices SWR 1 , SWG 1 and SWB 1 , voltages at the nodes N 1 R, N 1 G and N 1 B from a preceding cycle are discharged to the power voltage Vee. Further, because the switching devices S 1 A and S 1 B in each analog buffer 18 R, 18 G and 18 B are turned on, a voltage is stored in the capacitor C 1 to turn on the transistor M 2 .

During time interval t 2 –t 3 , the switching devices SWR 1 , SWG 1 and SWB 1 in output circuits 16 R, 16 G and 16 B and the switching devices S 1 A and S 1 B are turned off. The transistor M 2 remains on due to the voltage stored in the capacitor C 1 .

time interval t 3 –t 4 (PD 4 ), the switching devices S 2 , S 3 A, S 3 B and S 3 C in each analog buffer are turned on such that the first and second source followers 10 A and 30 A are both enabled. Accordingly, the first source follower 10 A regulates a voltage of VAR 1 +|Vgsp| at the node N 1 in the analog buffer 18 R. The node N 2 is then charged to the voltage of VAR 1 +|Vgsp| a voltage of |Vgsn| is stored in the capacitor C 2 . Similarly, the first source follower 10 A regulates a voltage of VAG 1 +|Vgsp| at the node N 1 in the analog buffer 18 G. The node N 2 is then charged to the voltage of VAG 1 +|Vgsp|, a voltage of |Vgsn| is stored in the capacitor C 2 . Similarly, the first source follower 10 A regulates a voltage of VAB 1 +|Vgsp| at the node N 1 in the analog buffer 18 B. The node N 2 is then charged to the voltage of VAB 1 +|Vgsp|, a voltage of |Vgsn| is stored in the capacitor C 2 . In this embodiment, the V gs of the transistors M 1 and M 3 are normalized by adjusting M 1 and M 3 size, namely |Vgsp|=|Vgsn|.

time interval t 4 –t 5 , the switching devices S 3 A, S 3 B and S 3 C in each analog buffer are turned off such that the first source follower 10 A is disabled to conserve power.

time interval t 5 –t 6 (PD 2 ), the switching device S 4 A is turned on such that the second source follower 30 A in the analog buffer 18 R outputs a voltage VAR 2 identical to the input voltage VAR 1 according to the input voltage from the switching devices S 4 A and the voltage (|Vgsn|) stored capacitor C 2 . The output voltage VAR 2 regulated by the transistor M 3 is identical to the input voltage VAR 1 because the |Vgsn| of the transistor M 3 is compensated by voltage stored in the capacitor C 2 . Similarly, the second source follower 30 A in the analog buffer 18 G also outputs a voltage VAG 2 identical to the voltage VAG 1 , and the second source follower 30 A in the analog buffer 18 B also outputs a voltage VAB 2 identical to the voltage VAB 1 . In the same time interval, the switching devices SWR 2 , SWG 2 and SWB 2 are turned on such that the voltages VAR 2 , VAG 2 and VAB 2 are output to the loads 17 R, 17 G and 17 B respectively.

During time interval t 6 –t 7 , the switching devices S 2 and S 4 A are turned off such that the second source follower 30 A in each analog buffer 18 R, 18 G and 18 B is disabled to conserve power.

During time interval t 7 –t 8 (PD 3 ), all switches are turned off, except that the switching devices SWR 3 , SWG 3 and SWB 3 in output circuits 16 R, 16 G and 16 B shown in FIG. 1A such that the voltages VAR 1 , VAG 1 and VAB 1 from the DACs 14 R, 14 G and 14 B are output to the loads 17 R, 17 G and 17 B respectively without DC offset voltage caused by analog buffers, thereby increasing precision of analog output voltage level. The cycle above repeats from t 1 to t 8 , in accordance with the timing chart of FIG. 4 .

FIG. 3B shows another embodiment of an analog buffer. The analog buffer 18 ″ comprises a first source follower 10 A′, a switching circuit 20 A′, and a second source follower 30 A′. As shown in FIG. 3B , unlike the previous embodiment, the first source follower 10 A′ is an N-type source follower coupled between the power voltages Vdd and Vee. The second source follower 30 A′ is a P-type source follower, coupled to the switching circuit 20 A′.

The first source follower 10 A′ comprises two transistors M 1 and M 2 , three switching devices S 1 A, S 1 B and S 3 A, a capacitor C 1 , and a transistor M 4 biased by a bias voltage Va. The switching circuit 20 A′ is coupled between the first and second source followers b 1 A′ and 30 A′. The switching circuit 20 comprises three switching devices S 3 B, S 3 C and S 4 A and a capacitor C 2 . The second source follower 30 A′ is a P-type source follower, coupled to the switching circuit 20 A′. The second source follower 30 A′ comprises a transistor M 3 , a switching device S 2 , and a transistor M 5 biased by the bias voltage Va. In this embodiment, the current provided by the transistor M 5 can be N times that provided by the transistor M 4 , for increased driving capability.

FIG. 4 is also the timing chart of the signal driving circuit 300 A employing three analog buffers 18 ″ as shown in FIG. 3B .

During time interval t 1 –t 2 , all switching devices are turned off, expect that the switching devices SWR 1 , SWG 1 and SWB 1 in output circuits 16 R, 16 G and 16 B shown in FIG. 1A , and the switching devices S 1 B and S 1 B in each analog buffer 18 R, 18 G and 18 B shown in FIG. 3B . Due to turning on of the switching devices SWR 1 , SWG 1 and SWB 1 , the voltages at the nodes N 1 R, N 1 G and N 1 B from a preceding cycle are charged to the power voltage Vdd. Further, because the switching devices S 1 A and S 1 B in each analog buffer 18 R, 18 G and 18 B are turned on, a voltage is stored in the capacitor C 1 to turn on the transistor M 2 .

time interval t 2 –t 3 , the switching devices SWR 1 , SWG 1 and SWB 1 in output circuits 16 R, 16 G and 16 B and the switching devices S 1 A and S 1 B are turned off. The transistor M 2 remains on due to the voltage stored in the capacitor C 1 .

time interval t 3 –t 4 (PD 4 ), the switching devices S 2 , S 3 A, S 3 B and S 3 C in each analog buffer are turned on such that the first and second source followers 10 A′ and 30 A′ are both enabled. Accordingly, the first source follower 10 A′ regulates a voltage of VAR 1 −|Vgsn| at the node N 4 . The node N 5 is then charged to the voltage of VAR 1 −|Vgsn| due to turning on of the switching device S 3 B, and a voltage of |Vgsp| is stored in the capacitor C 2 . Similarly, the first source follower 10 A′ regulates a voltage of VAG 1 −|Vgsn| at the node N 4 in the analog buffer 18 G. The node N 5 is then charged to the voltage of VAG 1 −|Vgsn|, a voltage of |Vgsp| is stored in the capacitor C 2 . Similarly, the first source follower 10 A regulates a voltage of VAB 1 −|Vgsn| at the node N 4 in the analog buffer 18 B. The node N 5 is then charged to the voltage of VAB 1 −|Vgsn|, a voltage of |Vgsp| is stored in the capacitor C 2 . In this embodiment, the V gs of the transistors M 1 and M 3 are normalized by adjusting M 1 and M 3 size, namely |Vgsp|=|Vgsn|.

time interval t 4 –t 5 , the switching devices S 3 A, S 3 B and S 3 C are turned off in each analog buffer such that the first source follower 10 A′ is disabled to conserve power.

time interval t 5 –t 6 (PD 2 ), the switching devices S 4 A and S 4 B are turned on such that the second source follower 30 A′ in analog buffer 18 R outputs a voltage VAR 2 identical to the input voltage VAR 1 according to the input voltage from the switching devices S 4 A and the voltage stored capacitor C 2 . The output voltage VAR 2 regulated by the transistor M 3 is identical to the input voltage VAR 1 because the |Vgsp| of the transistor M 3 can be compensated by voltage stored in the capacitor C 2 . Similarly, the second source follower 30 A′ in the analog buffer 18 G also outputs a voltage VAG 2 identical to the voltage VAG 1 , and the second source follower 30 A′ in the analog buffer 18 B also outputs a voltage VAB 2 identical to the voltage VAB 1 . In the same time interval, the switching devices SWR 2 , SWG 2 and SWB 2 are turned on such that the voltages VAR 2 , VAG 2 and VAB 2 are output to the loads 17 R, 17 G and 17 B respectively.

time interval t 6 –t 7 , the switching devices S 2 and S 4 A are turned off such that the second source follower 30 A′ in each analog buffer is disabled to conserve power.

During time interval t 7 –t 8 (PD 3 ), all switches are turned off, except that the switching devices SWR 3 , SWG 3 and SWB 3 in output circuits 16 R, 16 G and 16 B shown in FIG. 1A such that the voltages VAR 1 , VAG 1 and VAB 1 from the DACs 14 R, 14 G and 14 B are output to the loads 17 R, 17 G and 17 B respectively without DC offset voltage from analog buffers, thereby increasing precision of analog output voltage level.

FIG. 5A shows the relationship between the input voltage Vin of the output circuit and DC offset voltage after turning on the switching devices SWR 2 , SWG 2 and SWB 2 according to simulation of the embodiments of FIGS. 3A and 3B .

During this period (PD 2 ), the signal driving circuit utilizes analog buffers to output analog voltages to the corresponding loads, improving the driving capability of the DACs under a small DC offset voltage. As shown in FIG. 5A , the DC offset voltage of the analog buffers of the embodiments is less than 10 mV, in which the input voltage Vin of output circuit is the output voltage VAR 1 , VAG 1 or VAB 1 of the DACs 14 R, 14 G or 14 B.

FIG. 5B shows the relationship between the input voltage Vin and DC offset voltage after turning on the switching devices SWR 3 , SWG 3 and SWB 3 according to simulation of the embodiments of FIGS. 3A and 3B . In this period (PD 3 ), the signal driving circuit directly outputs analog voltages from DACs to the corresponding loads without DC offset voltage from analog buffers, thereby increasing precision of analog output voltage level. As shown in FIG. 5B , the DC offset voltage of output circuit of the embodiments is less than 0.1 mV, wherein the input voltage Vin is the output voltage VAR 1 , VAG 1 or VAB 1 of the DACs 14 R, 14 G or 14 B.

Because the signal driving circuit of the embodiments of the invention outputs analog voltages through analog buffers and directly from the DACs to the corresponding loads in turn, they improve the driving capability and precision of analog output voltage level at the same time.

FIG. 6 is a schematic diagram of a driver 450 according to various embodiments of the invention. As shown in FIG. 6 , the driver 450 can comprise shift registers 310 , a sampling circuit 320 , a latching circuit 330 , the digital-to-analog conversion circuit 340 comprising a plurality of digital-to-analog converters 14 as shown in FIG. 1A or 1 B, and the output stage 350 comprising a plurality of output circuits 16 as shown in FIG. 1A or 1 B. The shift registers 310 have a plurality of stages equal in number to columns of pixels in a display panel (not shown). The sampling circuit 320 samples data on a data bus (not shown) synchronous with sampling pulses output successively from the shift registers 310 . The latch circuit 330 holds and latches the sampled data during a horizontal period, and the DAC 340 converts the latched data to analog signals. The output stage 350 drives the columns of pixels in a display panel according to the analog signals from the digital-to-analog conversion circuit 340 and control signals from external controller. The driver 450 can be a source driver or a data driver in a display system, such as a liquid crystal display system or the like.

FIG. 7 schematically shows an electronic device 600 deploying a driving circuit 300 described above. The display panel 400 can be a liquid crystal display element, a plasma display element, an organic light emitting display element, or a cathode ray tube element. The electronic device 600 may be a portable device such as a PDA, notebook computer, tablet computer, cellular phone, or a display monitor device, etc. Generally, the electronic device 600 includes a housing 500 , a timing controller 510 , the display panel 400 and a driving circuit 300 , etc. Further, the timing controller 510 is operatively coupled to the signal driving circuit and provides control signals to the driving circuit 300 . The driving circuit 300 is operatively coupled to the display panel 400 and provides analog voltage to drive the display panel 400 , and the display panel 400 displays images.

While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.