Pipelined analog-to-digital converter having interleaved sample-and-hold circuits coupled in common

The present application claims priority from Japanese patent application No. 2004-255299 filed on Sep. 2, 2004, the content of which is hereby incorporated by reference into this application.

1. Field of the Invention

The present invention relates to a semiconductor integrated circuit device and more particularly to a technology effectively utilized, for example, for a preprocessing LSI (AFE: Analog Front End) for a camera provided with Pipelined A-D conversion circuit.

2. Description of Related Art

Pipeline A-D conversion circuits are disclosed, for example, in Japanese Unexamined Patent Publication No. Hei 08 (1996)-337989 and in Japanese Unexamined Patent Publication No. 2000-013232.

[Patent Document 1] Japanese Unexamined Patent Publication No. Hei 08 (1996)-337989

[Patent Document 2] Japanese Unexamined Patent Publication No. 2000-013232

Based on Patent Document 1 above, the pipelined A-D conversion circuit illustrated in FIG. 20 was considered prior to the invention as claimed in the application concerned. The A-D converter in FIG. 20 is a pipelined A-D converter (hereafter, referred to as “ADC”) of nine-stage construction. The first stage STG 1 and the last stage STG 9 have a resolution of 3 bits, and the other stages STG 2 to STG 8 have a resolution of 1.5 bits. Each stage comprises a sub-ADC and a sample-and-hold amplifier (hereafter, referred to as “S/H amplifier). The S/H amplifiers are responsible for the functions of D/A converter (hereafter, referred to as “DAC”) subtracter, and double gain amplifier. Input is converted into a digital signal by the sub-ADC 1 in the first stage STG 1 . Its output is the digital output of the first stage, and further the higher-order 1.5 bits are also used as input to the sub-DAC 1 in the first stage STG 1 . A residual signal obtained by subtracting the output of the DAC 1 from the input to the ADC 1 is amplified and doubled, and is passed to the second stage STG 2 . The lower-order 1.5 bit output of the sub-ADC 1 in the first stage STG 1 is passed to the second stage STG 2 , and is used as input to the sub-DAC in the second stage STG 2 .

In the second stage STG 2 , the result of conversion of the signal amplified at the first stage STG 1 into the digital signal by the sub-ADC 2 is passed to an output circuit. This also makes input to the DAC 3 in the third stage STG 3 . To the sub-DAC 2 in the second stage STG 2 , the lower-order 1.5 bits of the output of the sub-ADC 1 in the first stage STG 1 are inputted. A residual signal obtained by subtracting the output of the sub-DAC 2 from the amplifier output of the first stage STG 1 is amplified and doubled, and is passed to the third stage STG 3 . The same operation as in the second stage STG 2 is performed in the third and following stages, and the output of ADCs are sequentially determined from higher-order bits. Since the last stage STG 9 need not pass a signal to the next stage, it is composed only of a 3-bit sub-ADC. In ordinary pipelined ADCs, the output of each sub-ADC is inputted to the sub-DAC in the same stage. In the above method, meanwhile, the input to the sub-DAC in each stage is determined by the sub-ADC in the preceding stage. Thus, the timing of DAC-subtracter-amplifier portions can be separated from the timing of the sub-ADCs; therefore, the critical path is shortened, and speed enhancement can be accomplished.

Based on Patent Document 2 above, the pipelined A-D conversion circuit illustrated in FIG. 21 was considered prior to the invention as claimed in the application concerned. With respect to the ADC illustrated in FIG. 20 , the first stage STG 1 and the last stage STG 9 are of 3 bits, and the stages between them are of 1.5 bits. In the ADC in FIG. 21 , all the stages are of n bits, and each stage is so constructed that it has two sets of sub-DACs and two sets of S/H amplifiers. The ADCs perform interleave operations in which, when either S/H amplifier is performing a sampling operation, the other performs a holding operation. Thus, the speed of amplifiers is mitigated, and lowering of power is accomplished.

One of means for enhancing the accuracy by the ADC technology described in Patent Document 1 is to increase the number of pipelined stages. By adding another stage, the accuracy can be enhanced by one bit. However, there is a problem. Increase in the number of pipelined stages leads to increased power consumption. Another method is to enhance the resolution per stage; however, this case also involves a problem. Since the load capacity of amplifiers is increased, it is required to increase the consumption current of amplifiers for ensuring speed. To reduce power consumption, it is required to reduce the amplifier current, which accounts for a large percentage of the power consumption of ADCs. This involves speed reduction. According to the ADC technology described in Patent Document 2, all the stages are provided with two sets of S/H circuits and two sets of DACs. Interleave operations occur in which, when either is performing a sampling operation, the other performs a holding operation is performed. Thus, the speed of amplifiers is mitigated, and lowering of power is accomplished. However, interleave operations involve problems. Since two types of signal paths are created, a difference is produced between their outputs due to variation in element or the like, and this degrades the accuracy.

An object of this invention is to provide a semiconductor integrated circuit device provided with a pipelined A-D conversion circuit in which high accuracy and low power consumption are accomplished. The above and other objects and novel features of this invention will be apparent from the description in this specification and accompanying drawings.

The following is a brief description of the gist of the representative elements of the invention disclosed in this application: a semiconductor integrated circuit device is provided with a pipelined A-D conversion circuit that is series-connected with an input terminal to which analog signals to be converted are inputted and has a plurality of stages. The stages other than the first stage connected with the input terminal through at least one stage, including the first stage that receives input signals from the input terminal, are constructed as follows: each of the other stages is comprised of two or more sample and hold circuits and amplifiers connected in common with the two or more sample and hold circuits. The two or more sample and hold circuits are caused to perform interleave operations.

High accuracy can be maintained and power consumption can be reduced by interleave operations limited to downstream stages in which accuracy is not required.

FIG. 1 is a block diagram illustrating an embodiment of a pipelined A-D converter according to this invention.

FIG. 2 is an explanatory drawing explaining the accuracy required in each stage of the ADC illustrated in FIG. 1 .

FIG. 3 is a circuit diagram illustrating an embodiment of an interleaved S/H amplifier for use in a pipelined A-D converter according to this invention.

FIG. 4 is a drawing illustrating the operation timing of the S/H amplifier in FIG. 3 .

FIG. 5 is a block diagram illustrating another embodiment of interleaved stages for use in a pipelined A-D converter according to this invention.

FIG. 6 is a drawing illustrating the operation timing of the stages in FIG. 5 .

FIG. 7 is a block diagram illustrating a further embodiment of interleaved stages for use in a pipelined A-D converter according to this invention.

FIG. 8 is a drawing illustrating the operation timing of the stages in FIG. 7 .

FIG. 9 is a block diagram illustrating an embodiment of an interleaved 1.5-bit sub-ADC for use in this invention.

FIG. 10 is a drawing illustrating the operation timing of the sub-ADC in FIG. 9 .

FIG. 11 is a block diagram illustrating another embodiment of a pipelined A-D converter according to this invention.

FIG. 12 is a circuit diagram illustrating an embodiment of an uninterleaved S/H amplifier for use in a pipelined A-D converter according to this invention.

FIG. 13 is a drawing illustrating the operation timing of the S/H amplifier in FIG. 12 .

FIG. 14 is a block diagram illustrating an embodiment of an uninterleaved 1.5-bit sub-ADC for use in this invention.

FIG. 15 is a circuit diagram illustrating an embodiment of a voltage comparator for use in this invention.

FIG. 16 is a drawing illustrating the operation timing of the voltage comparator in FIG. 15 .

FIG. 17 is a circuit diagram illustrating an embodiment of a differential amplifier used in an S/H amplifier for use in this invention.

FIG. 18 is a circuit diagram illustrating an embodiment of a voltage comparator used in a sub-ADC for use in this invention.

FIG. 19 is a block diagram illustrating an embodiment of a camera preprocessing LSI to which this invention is applied.

FIG. 20 is a block diagram of a pipelined A-D conversion circuit considered based on Patent Document 1 prior to this invention.

FIG. 21 is a block diagram of a pipelined A-D conversion circuit considered based on Patent Document 2 prior to this invention.

FIG. 1 is a block diagram illustrating an embodiment of a pipelined A-D converter according to this invention. The A-D converter in this embodiment is an ADC of 10-stage construction. The first stage STG 1 has a resolution of 4 bits; the last stage STG 10 has a resolution of 3 bits; and the other stages STG 2 to STG 9 have a resolution of 1.5 bits. Each stage consists of a sub-ADC and an S/H amplifier. Like the stage STG 1 illustrated in the figure as an example, the S/H amplifiers are responsible for the functions of DAC, subtracter, and quadruple gain amplifier. Like the stage STG 2 or STG 4 illustrated in the figure as an example, they are responsible for the functions of DAC, subtracter, and double gain amplifier. Input is converted into a digital signal by the sub-ADC 1 in the first stage STG 1 . Its output makes the digital output of the first stage STG 1 . Further, the higher-order 2.5 bits of the 4-bit output are inputted to the sub-DAC 1 in the first stage, and the lower-order 1.5 bits are inputted to the sub-DAC 2 in the second stage. Further, they are inputted to the sub-ADC 2 in the second stage, and a reference corresponding to this digital value is selected. A residual signal obtained by subtracting the output of the DAC 1 from the input to the sub-ADC 1 is amplified and quadrupled, and is passed to the second stage STG 2 .

The second stage STG 2 passes the result of conversion of the signal amplified at the first stage STG 1 into a digital signal by the sub-ADC 2 to an output circuit. This also makes input to the DAC 3 in the third stage STG 3 . To the sub-DAC 2 in the second stage STG 2 , the lower-order 1.5 bits of the output of the sub-ADC 1 in the first stage STG 1 are inputted. A residual signal obtained by subtracting the output of the sub-DAC 2 from the amplifier output of the first stage STG 1 is amplified and doubled, and is passed to the third stage STG 3 . The same operation as in the second stage STG 2 is performed in the third and following stages, and the output of ADCs are sequentially determined from higher-order bits. Since the last stage STG 9 need not pass a signal to the next stage, it is composed only of a 3-bit sub-ADC. The output signals of the stages STG 1 to STG 10 are inputted to an encoder/correction circuit, from which a digital signal comprising 14 bits is outputted.

In ordinary pipelined ADCs, the output of each sub-ADC is inputted to the sub-DAC in the same stage. In a pipelined A-D converter in this embodiment, meanwhile, the input to the sub-DAC in each stage is determined by the sub-ADC in the preceding stage. As described later with reference to FIG. 9 , selection of a desired reference voltage for the sub-ADC in each stage is determined by the sub-ADC in the preceding stage. Thus, the timing of DAC-subtracter-amplifier portions can be separated from the timing of the sub-ADCs; therefore, the critical path is shortened, and speed enhancement can be accomplished. This embodiment is a pipelined ADC of 10-stage construction. As mentioned above, the first stage STG 1 is of 4 bits; the second to ninth stages STG 2 to STG 9 are of 1.5 bits; and the last stage STG 10 is of 3 bits. The fourth stage STG 4 and the following stages are interleaved. In interleaving, in general, a plurality of signal paths, for example, ADC 41 and ADC 42 and DAC 41 and DAC 42 , are created; therefore, a difference is produced between the outputs of the paths due to variation in element or the like, and this degrades the accuracy. As mentioned above, however, the fourth stage STG 4 and the following stages are interleaved, and thus degradation in accuracy due to variation in elements or the like can be made negligible.

FIG. 2 is an explanatory drawing explaining the required accuracy in each stage with the 14-bit ADC in FIG. 1 taken as an example. As illustrated in the figure, the required accuracy is lowered in more downstream stages. More specific description will be given. In the first stage STG 1 , an accuracy of 14 bits is required. In the second stage STG 2 , the higher-order 4 bits are removed, and thus the accuracy is lowered to 11 bits. Hereafter, the accuracy is lowered in decrements of 1.5 bits as the stage goes downstream. In the fourth stage STG 4 , as mentioned above, the accuracy can be reduced to so low a value as 9 bits. Only the fourth stage STG 4 and the following stages where the accuracy requirement is mitigated are interleaved. Thus, degradation in accuracy is avoided and the power consumption is lowered. In the first stage STG 1 to the third stage STG 3 where bit accuracy is required, degradation in accuracy due to variation in element or the like has influence. In these stages, therefore, interleaving is avoided, and priority is given to accuracy. Thus, both high accuracy and low power consumption can be accomplished at the same time.

FIG. 3 is a circuit diagram illustrating an embodiment of an interleaved S/H amplifier for use in a pipelined A-D converter according to the present invention. In this embodiment, interleaving is implemented as follows: switch portions are shared between the amplifier main body AMP and the inputs d 0 to d 2 of a DAC, and two sets of capacitors are provided and switched by the switches. The amplifier main body AMP is a complete differential amplifier, and has two sets of capacitors C 1 to C 4 and C 5 to C 8 that sample and hold input signals, each set comprising four capacitors. First plates of the capacitors C 1 and C 3 and C 5 and C 7 are connected with the positive input end (+) of the complete differential amplifier AMP through switches. First plates of the capacitors C 2 and C 4 and C 6 and C 8 are connected with the negative input end (−) of the complete differential amplifier AMP through switches.

FIG. 4 is a drawing illustrating the operation timing of the S/H amplifier in FIG. 3 . Clock signals φsod and φhev, and clock signals φsev and φhod are respectively signals in phase, and clock signals φsod and φhod, and clock signals φsev and φhev are respectively signals in opposite phase. The character s in φsod and φsev indicates sampling pulse, and the character h in φhod and φhev indicates hold pulse. The characters od in φsod and φhod indicate an odd number of interleave, and the characters ev in φsev and φhev indicate even number of interleaved samples.

During sampling on the odd-numbered side (clock signal φsod=1 (high level), and clock signal φhod=0 (low level)), the second plates of the capacitors C 1 and C 3 are supplied with a positive input signal Vi+; the second plates of the capacitors C 2 and C 4 are supplied with a negative input signal Vi−. The input ends (+, −) of the complete differential amplifier AMP are biased with a desired voltage VRT.

During sampling on the even-numbered side (clock signal φsev=1 (high level), clock signal φhev=0 (low level)), the second plates of the capacitors C 5 and C 7 are supplied with a positive input signal Vi+; the second plates of the capacitors C 6 and C 8 are supplied with a negative input signal Vi−. The input ends (+, −) of the complete differential amplifier AMP are biased with a desired voltage VRT.

During a hold operation on the odd-numbered side (clock signal φsod=0 (low level), clock signal φhod=1 (high level)), a selection is made with respect to the second plates of the capacitors C 1 and C 2 : they are connected with a different reference voltage VRT or VRB, or connected together. Meanwhile, the second plates of the capacitors C 3 and C 4 are respectively connected with the negative output end (−) and with the positive output end (+) of the complete differential amplifier.

During a hold operation on the even-numbered side (clock signal φsev=0 (low level), clock signal φhev=1 (high level)), a selection is made with respect to the second plates of the capacitors C 5 and C 6 : they are connected with a different reference voltage VRT or VRB, or connected together. Meanwhile, the second plates of the capacitors C 7 and C 8 are respectively connected with the negative output end (−) and with the positive output end (−) of the complete differential amplifier.

During hold on the odd-numbered side (clock signal φsod=0, clock signal φhod=1), the connecting state of the second plate of each of the capacitors C 1 and C 2 is selected from among the following three: (a) VRT, VRB, (b) short-circuiting, and (c) VRB, VRT. The DAC function is thereby implemented.

During a hold operation on the even-numbered side (clock signal φsev=0, clock signal φhev=1), the connecting state of the second plate of each of the capacitors C 5 and C 6 is selected from among the following three: (a) VRT, VRB, (b) short-circuiting, and (c) VRB, VRT. The DAC function is thereby implemented.

The electric charges stored in the capacitors C 1 and C 2 during sampling on the odd-numbered side are respectively transferred to the capacitors C 3 and C 4 in accordance with the connecting state selected during hold. Thus, subtraction and amplification are carried out at the same time. Similarly, the electric charges stored in the capacitors C 5 and C 6 during sampling on the even-numbered side are respectively transferred to the capacitors C 7 and C 8 in accordance with the connecting state selected during a hold operation. Thus, subtraction and amplification are carried out at the same time.

In the S/H amplifier in this embodiment, the speed of the amplifier is mitigated and lowering of power is accomplished by performing interleave operations. In interleave operations, when either (odd-numbered side or even-numbered side) is performing sampling operations, the other (even-numbered side or odd-numbered side) performs holding operations. That is, when the upper capacitors C 1 to C 4 are connected with the amplifier main body AMP and carry out amplification, the lower capacitors C 5 to C 8 are disconnected from the amplifier main body AMP and start sampling. This operation is alternately performed, and as a result, the amplifier AMP constantly carries out amplification. The amplification time is double that of an uninterleaved S/H amplifier. Thus, the speed of the amplifier can be reduced to half, and the consumption current can be reduced.

FIG. 5 is a block diagram illustrating another embodiment of interleaved stages for use in a pipelined A-D converter according to this invention. Unlike the example illustrated in FIG. 1 , this embodiment uses sub-ADCs in common. Thus, the circuit can be simplified. As illustrated in the timing chart in FIG. 6 , however, the comparator of the sub-ADC starts sampling when the S/H amplifier is performing holding operations. Thus, the comparator of the sub-ADC starts sampling when the S/H amplifier is performing holding operations, and as a result, the output of the S/H amplifier is caused to largely fluctuate. To settle this, it is required to increase the current of the S/H amplifier.

FIG. 7 is a block diagram illustrating a further embodiment of interleaved stages for use in a pipelined A-D converter according to this invention. This embodiment corresponds to the embodiment illustrated in FIG. 1 , and the comparators of the sub-ADCs are also interleaved. Thus, as illustrated in the timing chart in FIG. 8 , the hold period of the S/H amplifiers and the sampling period of the comparators are matched with each other, and increase in the current of the S/H amplifiers can be avoided. This interleaving causes the comparators to operate at half speed. Therefore, the current of the comparators can be reduced to half or less, and increase in current due to increase of comparators can be suppressed. That is, the sub-ADC 41 ( 51 ) and the sub-ADC 42 ( 52 ) operate at opposite phases, and each of them alternately samples and compares signals, and transmits the result of comparison to the next stage. The sub-ADC 41 and the sub-ADC 42 operate at speeds equivalent to half of the clock frequency. For this reason, the working speed is reduced to half as compared with cases where only one sub-ADC is provided as in the example illustrated in FIG. 5 , and thus the power consumption can be lowered. When the S/H amplifiers are in a hold period, switching between comparing operation and sampling operation does not take place in the sub-ADCs, and thus there is no influence on the output of the S/H amplifiers.

FIG. 9 is a block diagram illustrating an embodiment of an interleaved 1.5-bit sub-ADC for use in a pipelined A-D converter according to this invention. FIG. 10 is a drawing illustrating its operation timing. The sub-ADC in this embodiment comprises: a circuit in which the voltage between reference voltages VRT and VRB is divided by ladder resistors formed by connecting resistors in series, and desired reference voltages are generated; switches that select a desired reference voltage from among the generated reference voltages and take them out; four voltage comparators that compare the reference voltage taken out with the differential input signals (Vi+, Vi−) for magnitude; and a decoder that selects the output of the comparator 1 and the comparator 2 and the output of the comparator 3 and the comparator 4 , respectively, by a selector 1 and a selector 2 , and decodes them to the next stage.

The comparator 1 and the comparator 2 , and the comparator 3 and the comparator 4 operate at opposite phases, respectively. The comparator 1 and the comparator 3 , and the comparator 2 and the comparator 4 respectively alternately repeat sampling and comparison of signal input to perform interleave operations. Since each of the comparators 1 to 4 operates at speed equivalent to half of the clock frequency, the power consumption can be lowered.

FIG. 17 is a circuit diagram illustrating an embodiment of a differential amplifier used in an S/H amplifier for use in this invention. The differential amplifier in this embodiment is a complete differential amplifier that has VIN 1 and VIN 2 as input signals, and V 01 and V 02 as outputs. The differential amplifier comprises the first stage of a folded cascode amplifier, an output stage, a common mode feedback amplifier, and a common mode sense circuit. Terminal VCMI is for bias voltage that determines the output center of the differential amplifier, and terminals VSHBN 1 , VSHBN 2 , VSHBP 1 , and VSHBP 2 are for bias voltage applied to the current source for the differential amplifier.

The first stage of the differential amplifier is constituted in folded cascode type. It comprises: n-channel MOSFETs MN 71 and MN 72 to whose gates input signals VIN 1 and VIN 2 are inputted; an n-channel MOSFET MN 7 as a current source provided between their common source and the ground potential VSS of the circuit; p-channel MOSFETs MP 71 and MP 72 as current source loads placed between drains and supply voltage VDD; p-channel MOSFETs MP 6 and MP 8 ; p-channel MOSFETs MP 60 and MP 80 ; n-channel MOSFETs MN 60 and MN 80 ; and n-channel MOSFETs MN 6 and MN 8 .

The output stage of the differential amplifier comprises: n-channel MOSFETS MN 61 and MN 81 to whose gates the outputs o 3 and o 4 of the first stage are inputted; and p-channel MOSFETs MP 61 , MP 81 , MP 62 , and MP 82 that make current source loads. The output stage outputs output signals V 01 and V 02 . N-channel MOSFETs MN 41 , MN 42 , and MN 4 and p-channel MOSFETs MP 41 and MP 42 constitute a common mode feedback amplifier that determines the output center of the differential amplifier. N-channel MOSFETs MN 43 and MN 44 and capacitors C 3 and C 4 constitute a common mode sense circuit that detects the common mode voltage of the differential amplifier output.

When clock signal VSMPL is at high level, the common mode sense circuit short-circuits outputs V 01 and V 02 by the n-channel MOSFETs MN 43 and MN 44 , and stores the sensed common mode voltages in the capacitors C 3 and C 4 . N-channel MOSFETs MN 91 and MN 92 and capacitors C 1 and C 2 are a circuit for phase compensation. The n-channel MOSFETs MN 91 and MN 92 in the phase compensation circuit are biased with voltage generated by n-channel MOSFETs MN 9 , MN 90 , MP 9 , and MP 90 .

FIG. 18 is a circuit diagram illustrating an embodiment of a voltage comparator used in a sub-ADC for use in this invention. The voltage comparator in this embodiment comprises a differential amplifier, a latch amplifier, a latch circuit, and an output circuit. It has the following terminals: input VIN 1 and VIN 2 , output VOUTP and VOUTN, clock VAZCLK, VSLT, and VSLTB, and bias VADCOMP. Inputs VIN 1 and VIN 2 are combined at capacitors C 1 and C 2 and inputted to the input terminals in 1 and in 2 of the differential amplifier. The differential amplifier comprises: n-channel MOSFETs mn 11 and mn 12 , n-channel MOSFET mn 1 as a current source, and p-channel MOSFETs mp 11 and mp 12 and n-channel MOSFETs mn 13 and mn 14 as loads. The differential amplifier outputs output signals o 1 and o 2 to the latch amplifier.

The latch amplifier has the output signals o 1 and o 2 inputted. It comprises n-channel MOSFETs mn 21 , mn 22 , mn 2 , mn 23 , and mn 24 , and p-channel MOSFETs mp 21 , mp 22 , and mp 2 , and outputs output signals o 3 and o 4 to the latch circuit.

The latch circuit has the output signals o 3 and o 4 inputted, and comprises: n-channel MOSFETs mn 31 , mn 32 , and mn 3 and p-channel MOSFETs mp 31 , mp 32 , and mp 3 . The output circuit comprises n-channel MOSFETs mn 41 and mn 42 and p-channel MOSFETs mp 41 and mp 42 , and outputs output signals VOUTP and VOUTN.

When signal VAZCLK is at a high level, the differential amplifier has in 1 and o 1 and in 2 and o 2 short-circuited by the respective MOSFETs mn 13 and mn 14 , and performs an auto-zero operation. The latch amplifier operates as follows: when signal VSLT is at a low level, the p-channel MOSFET mp 2 is brought into on state; when signal VSLTB is at a high level, the n-channel MOSFETs mn 23 and mn 24 are brought into on state. Thus, it amplifies the output signals o 1 and o 2 of the differential amplifier, and outputs output signals o 3 and o 4 . The latch circuit operates as follows: when signal VSLTB is at low level, the p-channel MOSFET mp 3 is brought into on state; when signal VSLT is at a high level, the n-channel MOSFET mn 3 is brought into on state. At this time, it latches the inputs o 3 and o 4 , and outputs VOUTP and VOUTN through the output circuit comprising a CMOS inverter circuit.

FIG. 11 is a block diagram illustrating another embodiment of a pipelined A-D converter according to this invention. This embodiment is a pipelined ADC with a resolution of m bits, whose number of pipelined stages is n. Each stage has an arbitrary resolution of o 0 to on. The sub-ADC in each stage is of an arbitrary number of bits of a 0 to an, and the sub-DAC in each stage is of an arbitrary number of bits of d 0 to dn. The S/H amplifier of the sub-ADC in an arbitrary stage of the second and following stages is caused to perform interleave operations.

In the example illustrated in FIG. 1 , the sub-ADCs in the intermediate stages are so set that their number of digitized bits is 1.5 bits. The present invention is not limited to this constitution, and an arbitrary number of bits may be adopted as in the example illustrated in FIG. 11 . The amplification factor of the amplifiers in the S/H amplifiers is not limited to double, and it may be varied to, for example, G 0 to Gk according to the number of bits in digital conversion and the constitution of sub-DACs.

The reference voltage generation circuit in the sub-ADC can be implemented by the following constitution: as in the above embodiment, a plurality of resistors are connected in series between two different types of voltage sources; a switch that is opened or closed according to a digital signal is provided at each junction point between two resistors. The number of types of reference voltage taken out of the junction point is equal to a number obtained by multiplying the number of levels of digital signals by the number of comparators required for A-D conversion. (Examples of the number of levels of digital signals are 3 for 1.5 bits and 4 for 3.2 bits.) (Examples of the number of comparators required for A-D conversion are 2 for 1.5 bits and 3 for 2 bits.)

FIG. 12 is a circuit diagram illustrating an embodiment of an uninterleaved S/H amplifier for use in a pipelined A-D converter according to the present invention. FIG. 13 is a drawing illustrating its operation timing. That is, it is used as the S/H amplifier in the second or third stage. In the figure, symbols Vi+ and Vi− respectively denote positive and negative input analog signals; symbols Vo+ and Vo− respectively denote positive and negative output analog signals; symbols C 11 to C 14 denote capacitors for carrying out subtraction and holding operation; symbol AMP denotes a complete differential operational amplifier; symbols d 0 , d 1 , and d 2 denote input pulses corresponding to the three levels of input digital signals of 1.5 bits (any one is brought into a high level (“1”) and the others are brought into a low level (“0”); symbol φs denotes a sampling pulse; and symbol φh denotes a hold pulse.

D-A conversion and the operation of sampling input analog signals Vi+ and Vi− are carried out by switches supplied with input pulses do, d 1 , and d 2 , a switch supplied with sampling pulse φs, and capacitors. The input pulses d 0 , d 1 , and d 2 and the sampling pulse φs are in phase with each other. The hold pulse φh is in opposite phase thereto, and when this pulse is at a high level (“1”), subtraction and hold operation are carried out. In order that the output analog signals Vo+ ad Vo− are double the input analog signals Vi+ and Vi−, the capacitors C 11 , C 13 , C 12 , and C 14 are so set that C 11 =C 13 and C 12 =C 14 . As mentioned above, this circuit operates by switching each capacitor; therefore, it can be designated as switched capacitor type.

FIG. 14 is a block diagram illustrating an embodiment of an uninterleaved 1.5-bit sub-ADC for use in the present invention. The sub-ADC in this embodiment comprises: a circuit in which the voltage between reference voltages VRT and VRB is divided by ladder resistors formed by connecting resistors in series, and desired reference voltages are generated; switches that select a desired reference voltage from among the generated reference voltages and take them out; two voltage comparators 1 and 2 that compare the reference voltage taken out with the differential input signals (Vi+, Vi−) for magnitude; and a decoder that receives output signals, and decodes them to the next stage.

FIG. 15 is a circuit diagram illustrating an embodiment of a voltage comparator for use in this invention. Voltages vrt 0 , vrt 1 , and vrt 2 formed by such ladder resistors as illustrated in FIG. 14 are used to compare those corresponding to the outputs d 0 to d 2 of the sub-ADC in the preceding stage with input voltages (Vi+, Vi−) for magnitude. More specific description will be given. A reference voltage vrt 0 , vrt 1 , or vrt 2 to be compared is selected in correspondence with the outputs d 0 to d 2 of the sub-ADC in the preceding stage. The result of comparison of the selected voltage with the input voltages (Vi+, Vi−) is outputted as either a high level or a low level by the comparator. The comparator output is passed to the encoder/correction circuit through the latch amplifier and the latch circuit. Further, it is decoded and passed to the next stage so that it is used as input to the sub-ADC and DAC in the next stage.

The comparator in this embodiment is one designated as chopper type. The differential voltage between the analog signals Vi+ and Vi− and the reference voltage is stored in capacitors C 15 and C 16 by three types of switches. These switches include: switches supplied with control pulses φin for sampling input analog signals Vi+ and Vi−; a group of switches for selecting the reference voltages vrt 0 , vrt 1 , and vrt 2 ; and switches supplied with auto-zero pulses φaz for setting initial conditions. Subsequently, the positive or negative of the voltage is determined by the complete differential amplifier, and comparison operation is thereby performed. The comparison output is amplified by the latch amplifier for the enhancement of sensitivity of comparison.

As illustrated in the timing chart in FIG. 16 , the comparators 1 and 2 in FIG. 14 operate as follows: first, input signals Vi+ and Vi− are respectively sampled in the capacitors C 15 and C 16 by switches that are turned on by pulse φin. At this time, the input and output of the differential amplifier are short-circuited by switches that are turned on by pulse φaz, and the input and output ends are brought into self-bias voltage. Next, the pulses φin and φaz of signals are varied, and the switches are turned off. Instead, predetermined reference voltages are selected and inputted to the capacitors C 15 and C 16 by input pulses φs 0 , φs 1 , and φs 2 that are determined according to the levels of digital signals do to d 2 . Then, input voltages are compared with the reference voltages.

FIG. 19 is a block diagram illustrating an embodiment of a camera preprocessing LSI to which this invention is applied. A pixel signal formed by an image sensor, such as CCD, is sampled as follows: its feedthrough portion representing the black level that serves as the basis for such a pixel signal as illustrated in the drawing of sensor signal waveform in FIG. 19 is sampled by an S/H amplifier. Its signal portion that is a signal formed by the image sensor illustrated in the drawing of sensor signal waveform in FIG. 19 and represents the difference from the feedthrough portion is double sampled by a CDS (Correlated Double Sampling) amplifier. In this embodiment, the signal is digitized with an ADC (14 bits) according to this invention in the stage preceding a PGA (Programmable Gain Amplifier) comprising an analog circuit for the reduction of power consumption. Further, the output of the ADC (14 bits) is amplified by a factor of appropriate gain with the PGA (Programmable Gain Amplifier). The resulting digital signal output is processed at a DSP.

Signals may be processed by a digital signal processing circuit, such as the DSP, that processes this digital signal, in place of the PGA. Thus, the PGA may be omitted from the camera preprocessing LSI chip. When the signal portion is at black level, its voltage is ideally equal to that of the feedthrough portion; however, their voltages do not agree with each other due to the offset of the CCD. Therefore, the black level clamp signal is fed back to the S/H amplifier portion and corrected there. In this embodiment, the power consumption is reduced by interleaving the downstream side of the pipeline A-D converter, and the analog PGA is replaced with the digital PGA. As a result, the power consumption can be significantly reduced, or can be significantly reduced by omission of the PGA in the analog circuit.

In the pipelined A-D converter according to this invention, interleaving is implemented on the downstream side where the accuracy is mitigated. Therefore, degradation in accuracy can be suppressed, and the accuracy can be enhanced. In addition, the S/H amplifiers and sub-ADCs are interleaved, and the speed can be thereby reduced to half. Therefore, the consumption current can be reduced. The power of the ADC that accounts for most of the power consumption of such a camera preprocessing LSI (AFE) as mentioned above can be reduced without sacrificing the accuracy. Therefore, the accuracy of the AFE can be enhanced and further the power consumption can be significantly reduced. The S/H amplifier is interleaved by sharing switch portions between the amplifier main body of the S/H amplifier and the inputs d 0 to d 2 of the DAC, and providing two sets of capacitors. As a result, the amplifier constantly carries out amplification. If the sample time and the hold time are equal to each other, the amplification time is double that of an uninterleaved S/H amplifier. Thus, the speed of the amplifier can be reduced to half. The speed of an amplifier is in proportion to the self conductance gm of the input transistor of the amplifier, and gm is in proportion to the square root of the current. When the speed is reduced to half, therefore, the current is reduced to ¼.

Up to this point, concrete description has been given to the invention made by the present inventors based on the embodiments. However, the present invention is not limited to these embodiments, and various modifications may be made without departing from the spirit and scope thereof. For example, in the constitution illustrated in FIG. 21 , two sets of ADCs may be provided so that they are alternately operated when interleaved. Thus, the speed of the amplifiers constituting the ADCs can be reduced to half, and the current can be reduced to ¼. This invention can be utilized in a wide range of applications, including analog front end ICs for portable devices with cameras, digital still cameras, and digital video cameras with a high-accuracy and high-speed pipelined A-D converter built therein, and the like.