Drive circuit for a fluorescent lamp with a diagnosis circuit, and method for diagnosis of a fluorescent lamp

The present invention relates to a drive circuit for a fluorescent lamp, and to a method for diagnosis of a fluorescent lamp.

In order to assist understanding of the invention which will be explained in the following text, the basic design and method of operation of an electronic ballast which is used to drive a fluorescent lamp, and its method of operation, will first of all be explained with reference to FIGS. 1 to 3 . One such ballast is described, by way of example, in EP 1 066 739 B1, in U.S. Pat. No. 5,973,943 or in U.S. Pat. No. 6,617,805 B2.

The ballast has a half-bridge with a first semiconductor switching element Q 1 and a second semiconductor switching element Q 2 , whose load paths are connected in series between terminals K 1 , K 2 between which a DC voltage Vb is applied. This DC voltage Vb is produced (in a manner which is not illustrated in any more detail), for example, by means of a generally known power factor correction circuit (Power Factor Controller PFC) from a mains AC voltage. This DC voltage Vb has a normal amplitude value of 400 V.

The half-bridge circuit Q 1 , Q 2 uses this DC voltage Vb to produce a voltage V 2 with a pulsed signal waveform at an output K 3 . The two semiconductor switching elements are driven in a pulsed manner by a drive circuit 20 via drive signals S 1 , S 2 in order to produce this pulsed voltage V 2 . This drive is intended to minimize switching losses, such that the two switching elements Q 1 , Q 2 are never switched on at the same time, and such that both switching elements are switched off for a predetermined time period at the same time during a switching process. The frequency with which the two switching elements are driven in a pulsed manner and at which the pulsed voltage V 2 is produced is dependent, inter alia, on the burning state of the fluorescent lamp 10 that is supplied by the circuit and, once the lamp is burning, is, for example, 40 kHz. This frequency is adjusted by the drive circuit in a fundamentally known manner. Signal inputs via which the drive circuit receives information about the burning status of the lamp, and apparatuses for production of such signals, are not illustrated in the figures, for clarity reasons. The figures likewise do not show circuit components for supplying voltage to the drive circuit.

The fluorescent lamp 10 is connected in parallel with a resonant capacitor C 1 which is part of a resonant tuned circuit. This resonant tuned circuit which, in addition to the resonant capacitor C 1 , has a resonant inductance L 1 connected in series with the resonant capacitor C 1 , is connected to one output K 3 of the half-bridge Q 1 , Q 2 and is supplied by the pulsed supply voltage V 2 . A blocking capacitor C 2 which is connected in series with the resonant tuned circuit L 1 , C 1 is used to filter out the DC voltage component from the pulsed supply voltage V 2 , thus resulting in an AC voltage with an approximately square or trapezoidal signal waveform across the arrangement with the resonant tuned circuit L 1 , C 1 and the fluorescent lamp 10 . The amplitude of this AC voltage is approximately half the magnitude of the DC voltage that is applied to the half-bridge Q 1 , Q 2 .

After being started, the fluorescent lamp 10 behaves like a voltage-dependent resistance. A voltage which is dropped across the lamp 10 after it has been started has a waveform which approximates to a sinusoidal curve.

Before the lamp 10 is started, the lamp electrodes 11 , 12 must be preheated to an emission temperature. For this purpose, the supply voltage V 2 is produced at a higher frequency than after starting, thus resulting in a voltage V 10 which is less than a burning voltage on the lamp 10 . After the end of the preheating phase, the drive frequency of the half-bridge circuit Q 1 , Q 2 is reduced in order to reach a burning voltage, which is sufficient for the lamp to burn, and thus to start the lamp.

In order to preheat the lamp electrodes 11 , 12 , the lamp may be connected in the resonant tuned circuit in various ways. In the example shown in FIG. 1 , the current in the resonant tuned circuit L 1 , L 2 flows through the electrodes 11 , 12 , in order to preheat them. In the example shown in FIG. 2 , auxiliary inductances Lh 1 , Lh 2 are provided for preheating of the electrodes 11 , 12 , are inductively coupled to the resonant inductance L 1 and are respectively connected to one of the electrodes 11 , 12 in order to preheat them.

The arrangement with the resonant tuned circuit L 1 , C 1 and the fluorescent lamp 10 can be connected, with reference to FIGS. 1 and 2 , between the output K 3 of the half-bridge circuit Q 1 , Q 2 and a reference ground potential GND, or with reference to FIG. 3 between the output K 3 of the half-bridge circuit Q 1 , Q 2 and the center tap of a capacitive voltage divider C 4 , C 5 which is connected between the input terminals K 1 , K 2 .

A snubber capacitor C 3 is connected in parallel with the load path of the second semiconductor switching element Q 2 of the half-bridge circuit, with the object of allowing zero voltage switching operation (ZVS) of the two semiconductor switching elements Q 1 , Q 2 .

Fluorescent lamps have a finite life. Towards the end of this life, when the lamp is worn, the emission capability of the lamp electrodes 11 , 12 , which emit electrons into a fluorescent gas during operation, falls. As these electrons move from the metal of the electrodes 11 , 12 into the gas discharge, this normally actually results in a sufficiently large amount of heat being produced to keep the electrodes 11 , 12 at the temperature that is required for emission. If these emission conditions deteriorate as a result of wear, then a greater voltage drop occurs on the electrodes, and this leads to a larger amount of heat being produced, and to poorer lamp efficiency. While relatively old lamp types were normally able to withstand locally greater power loss without damage owing to their larger dimensions, this greater power loss and the greater amount of heat that is produced resulting from it in the case of relatively new lamp types, for example in the case of lamps with a diameter of ⅝″, can in the extreme lead to the glass surrounding the lamp melting. It is therefore necessary to identify the end of the life of fluorescent lamps in good time, in order to avoid such damage.

When the end of the life of a lamp is reached, the voltage V 10 across the lamp rises. One of the two electrodes 11 , 12 will normally wear earlier than the other, so that the lamp voltage V 10 becomes unbalanced, that is to say one of the positive or negative half-cycles has a greater amplitude than the respective other half-cycle. Based on this knowledge, it is known for the wear of a fluorescent lamp to be detected by forming the arithmetic mean value of the lamp voltage and comparing this with zero. If this arithmetic mean value differs by more than a predetermined amount from zero, thus indicating an unbalanced lamp voltage, it is assumed that the end of life has been reached.

Methods such as these, in which the arithmetic mean value of the lamp voltage is evaluated for wear detection, are described by way of example in U.S. Pat. No. 5,808,422 or EP 0 681 414 A2. These methods make use of the fact that the arithmetic mean value of the lamp voltage V 10 plus half the supply voltage Vb is dropped on the blocking capacitor c 2 , and can thus be measured and monitored relatively easily.

The known methods have the disadvantage that their implementation requires a comparatively large number of components, which cannot be integrated.

The aim of the present invention is thus to provide a drive circuit for a fluorescent lamp, which allows reliable diagnosis of wear of the fluorescent lamp, and which can be largely integrated, and to provide a method for diagnosis of a fluorescent lamp.

The drive circuit according to the invention for at least one fluorescent lamp has the following features:

a half-bridge circuit for production of a supply voltage, a resonant tuned circuit which is coupled to the half-bridge circuit and to which the at least one fluorescent lamp can be connected, a diagnosis circuit with a resistance element which is coupled to the resonant tuned circuit, at least one current/voltage converter which is connected to the resistance element and produces at least one measurement voltage from a current flowing through the resistance element, and an evaluation circuit which is connected to the current/voltage converter and is supplied with the at least one measurement voltage.

The method according to the invention for diagnosis of at least one fluorescent lamp, which has connections for application of a periodic operation voltage, with the method comprising the following method steps:

production of at least one periodic unipolar signal which is dependent on the operating voltage, determination of a first and a second peak value of the periodic signal, comparison of the peak values or comparison of in each case one peak value with a value which is derived from the respective other peak value in order to produce a wear signal as a function of the comparison result.

The subject matter of the invention also relates to a drive circuit for at least one fluorescent lamp, which has the following features:

a half-bridge circuit for production of a supply voltage, a resonant tuned circuit which is coupled to the half-bridge circuit and to which the at least one fluorescent lamp can be connected, a direct-current path which contains the resistance element and can be closed by an intact lamp filament in the fluorescent lamp and to which a detector circuit is connected for detection of a direct current flowing through the direct-current path.

The present invention will be explained in more detail in the following text using exemplary embodiments and with reference to the figures.

FIG. 1 shows a first drive circuit for a fluorescent lamp according to the prior art.

FIG. 2 shows a second drive circuit for a fluorescent lamp according to the prior art.

FIG. 3 shows a third drive circuit for a fluorescent lamp according to the prior art.

FIG. 4 shows a drive circuit according to the invention for a fluorescent lamp with a diagnosis circuit which has a resistance element, a current/voltage converter and an evaluation circuit.

FIG. 5 shows a first exemplary embodiment of an evaluation circuit which produces a wear signal.

FIG. 6 shows waveforms of selected signals which occur in the evaluation circuit shown in FIG. 5 .

FIG. 7 shows a modification of the evaluation circuit shown in FIG. 5 .

FIG. 8 shows a diagnosis circuit with an evaluation circuit according to a second exemplary embodiment.

FIG. 9 shows waveforms of selected signals which occur in the evaluation circuit shown in FIG. 8 .

FIG. 10 shows an implementation example of a current/voltage converter.

FIG. 11 shows a further implementation example of a diagnosis circuit.

FIG. 12 shows waveforms of selected signals which occur in the diagnosis circuit shown in FIG. 11 .

FIG. 13 shows one exemplary embodiment of a drive circuit, which has a direct-current path with a detector circuit connected to the direct-current path.

FIG. 14 shows a further exemplary embodiment of a drive circuit, which has a direct-current path with a detector circuit connected to the direct-current path.

Unless stated to the contrary, identical reference symbols denote identical circuit components and signals with the same meaning in the figures.

FIG. 4 shows an exemplary embodiment of a drive circuit according to the invention for a fluorescent lamp 10 . This drive circuit has a half-bridge circuit, which has already been explained in the introduction, with a first and a second semiconductor switching element Q 1 , Q 2 , whose load paths are connected in series between input terminals K 1 , K 2 , to which a DC voltage Vb is applied. A resonant tuned circuit with a resonant inductance L 1 and a resonant capacitor C 1 is connected to an output K 3 of the half-bridge circuit, which is formed by a node that is common to the load paths of the two semiconductor switching elements Q 1 , Q 2 . The fluorescent lamp 10 is in this case connected in parallel with the resonant capacitor C 1 . The fluorescent lamp 10 and the resonant tuned circuit L 1 , C 1 are connected in the example in a corresponding manner to the known circuit shown in FIG. 1 , but can also, of course, be connected in a corresponding manner to the circuit shown in FIG. 2 . That connection of the lamp 10 which is remote from the half-bridge could likewise be connected to the reference ground potential GND via a capacitive voltage divider, in contrast to the illustration shown in FIG. 4 .

A blocking capacitor C 2 is connected between the resonant tuned circuit L 1 , C 1 and the half-bridge circuit Q 1 , Q 2 and filters out any DC component from the voltage V 2 that is produced by the half-bridge circuit Q 1 , Q 2 and has a pulsed signal waveform. A so-called snubber capacitor C 3 is optionally connected in parallel with the load path of the second semiconductor switching element Q 2 and, in a manner which has been known for a long time, allows zero voltage operation of the two semiconductor switching elements Q 1 , Q 2 , that is to say allows each of these two semiconductor switching elements Q 1 , Q 2 to be switched at times at which the voltage across the load path of these two semiconductor switching elements Q 1 , Q 2 is equal to zero. The use of a snubber capacitor such as this has been known for a long time, and has already been described in U.S. Pat. No. 5,973,943, which was explained in the introduction.

A control circuit 21 is provided in order to drive the semiconductor switching elements Q 1 , Q 2 in the half-bridge circuit and produces drive signals S 1 , S 2 for the semiconductor switching elements such that these two semiconductor switching elements Q 1 , Q 2 are driven in a pulsed manner, with a time offset between them. In this case, the two semiconductor switching elements Q 1 , Q 2 are driven in such a way that they are never switched on at the same time, and such that the two semiconductor switching elements Q 1 , Q 2 are preferably switched off for a predetermined time period at the same time during a switching phase. The frequency at which the half-bridge Q 1 , Q 2 is driven in a pulsed manner is dependent on the respective operating state of the fluorescent lamp 10 , and is about 40 kHz once the fluorescent lamp is burning. This frequency may be 65 kHz or more during a preheating phase. The duty cycle of the drive signals S 1 , S 2 , that is to say the ratio between the times at which they are switched on and the drive period duration is, for example, about 45%.

According to the invention, the described drive circuit has a diagnosis circuit 30 with a resistance element R 1 , which is connected to the resonant tuned circuit L 1 , C 1 , in the example to the resonant capacitor C 1 . A current/voltage converter 31 is connected to this resistance element R 1 and converts a current 11 flowing through the resistance element R 1 to at least one voltage measurement signal V 31 , which is supplied to an evaluation circuit 32 , connected downstream from the current/voltage converter 31 . This evaluation circuit 32 provides a diagnosis signal S 30 which is supplied to the control circuit 21 for the half-bridge circuit. In this case, the control circuit 21 is designed to interrupt the drive to the half-bridge Q 1 , Q 2 and thus the supply to the fluorescent lamp 10 or, if appropriate, not to start it at all if the diagnosis signal S 30 indicates a faulty operating state, which will be explained later.

It should be noted that the control circuit 21 and the current/voltage converter 31 as well as the evaluation circuit 32 for the diagnosis circuit 30 may be integrated in a common semiconductor chip. The control circuit 21 and the diagnosis circuit 30 are illustrated as separate blocks in FIG. 4 only to assist understanding.

Furthermore, the control circuit 21 may of course have any desired further functionalities in addition to the functions already explained, by way of example as described for control circuits in the documents explained in the introduction, relating to the prior art.

As is also evident on the basis of the exemplary embodiments which will be explained in the following text, the diagnosis circuit 30 can largely be integrated. Only the resistance element R 1 is an external component, which cannot be integrated in a semiconductor chip.

In the drive circuit according to the invention, a current I 1 flowing through the resistance element R 1 is proportional to a lamp voltage V 10 that is applied across the lamp 10 , with the mathematical sign of this current I 1 changing with the frequency of the lamp voltage V 10 , which is approximately sinusoidal once the fluorescent lamp 10 is burning.

The current/voltage converter 31 is designed to produce at least one unipolar measurement voltage V 31 , which is related to a reference ground potential GND, that is to say a measurement voltage V 31 which is either exclusively positive or is exclusively negative, from this current I 1 with a changing mathematical sign, the amplitude of which measurement voltage V 31 varies corresponding to the amplitude of the measurement current I 1 flowing through the resistance element R 1 .

With reference to FIG. 6 a , by way of example, this current/voltage converter 31 is designed to produce a positive measurement voltage V 31 , which has an AC voltage component, which is proportional to the measurement current I 1 or to the lamp voltage V 10 , and which has a positive DC component or offset VR with respect to the reference ground potential GND. The offset value VR is in this case just reached by the measurement signal V 31 when the lamp voltage V 10 is zero, or when the measurement current I 1 is zero.

In order to produce the measurement signal V 31 , the offset VR is, by way of example, supplied as a DC voltage from a reference voltage source to the current/voltage converter, which forms the measurement signal V 31 by addition of the reference voltage and of a voltage value which is proportional to the measurement current I 1 .

FIG. 5 shows a first exemplary embodiment of an evaluation circuit which is used to diagnose possible wear of the fluorescent lamp 10 on the basis of the measurement signal V 31 that is derived from the lamp voltage V 10 , and to produce a wear signal as the diagnosis signal S 30 . The diagnosis signal is, for example, a two-value signal, which assumes a first signal level on detection of wear, and a second signal level otherwise.

The evaluation circuit 32 is supplied at one input with the measurement signal V 31 which is related to the reference ground potential GND. A signal whose magnitude corresponds to the DC component/offset VR of the voltage measurement signal V 31 is also available in the evaluation circuit 32 . This signal is applied to a number of nodes, which are annotated with “VR”, in the evaluation circuit 32 .

The evaluation circuit 32 has a first peak value detector D 11 , C 11 with a first diode D 11 and a first capacitive storage element C 11 , which are connected in series with a first switch S 11 between the input and offset potential VR. A first control signal KS 31 is provided in order to drive the first switch S 11 , is produced by a first comparator K 31 by comparison of the measurement signal V 31 with the offset potential VR, and assumes a high level when the amplitude of the measurement signal V 31 is greater than the offset potential VR. A second control signal KS 31 ′, which is complementary to this first comparison signal K 31 , is produced from the first control signal K 31 by means of an inverter INV 11 . The waveform of the first comparison signal K 31 is illustrated in FIG. 6 b , for the measurement signal V 31 that is illustrated in FIG. 6 a.

The time periods during which the voltage signal V 31 is greater than the offset VR are referred to in the following text as positive half-cycles of the voltage signal V 31 , while the time periods during which the voltage signal V 31 is less than the offset VR are referred to in the following text as negative half-cycles.

The first capacitive storage element C 11 is charged via the first rectifier element D 11 during positive half-cycles at the voltage signal V 31 when the first switch S 11 is closed to a value which corresponds to the positive amplitude ΔV+ of the AC voltage component of the measurement voltage V 31 minus the conducting-state voltage of the diode D 11 . The following explanation treats this conducting-state voltage of the diode D 11 as being negligible, so that it is assumed that the capacitor is charged to the positive amplitude ΔV+ during the positive half-cycle. A first comparison signal V 11 is applied to a node N 11 which is common to the detector element D 11 and to the storage capacitance C 11 , with respect to a reference ground potential GND at the end of the positive half-cycle, which first comparison signal V 11 corresponds to the sum of the positive amplitude value ΔV+ and the offset potential, such that:

V 11 =VR+ΔV+   (1).

This first comparison signal is also referred to in the following text as the positive peak value signal since, in addition to the constant additive component VR, it contains the information about the positive amplitude ΔV+. At the end of the positive half-cycle, this signal V 11 corresponds to the maximum value of the voltage signal V 31 . ΔV+ denotes the magnitude of the positive amplitude, and is also referred to in the following text as the positive amplitude value.

The evaluation circuit 32 has a second peak path detector with a second diode D 21 and a second storage capacitance C 21 , which is connected in series with a second switch S 21 between a node for the offset potential VR and the input. The second diode D 21 is in this case connected in the opposite direction to the first diode D 11 in order to charge the second storage capacitance C 21 —ignoring the conducting-state voltage of the diode D 21 —during a negative half-cycle of the measurement voltage V 31 to a value which corresponds to the negative amplitude ΔV− of the measurement voltage V 31 . A second comparison signal V 21 is applied to a node, which is common to the second diode D 21 and to the second capacitive storage element C 21 , with respect to the reference ground potential GND, for which second comparison signal V 21 at the end of the negative half-cycle:

V 21 =VR−ΔV−   (2).

This signal is also referred to in the following text as the negative peak value signal. Its amplitude at the end of the negative half-cycle corresponds to the minimum value of the voltage signal V 31 . ΔV− denotes the magnitude of the negative amplitude, and is also referred to in the following text as the negative amplitude value.

The second switch S 21 is driven by the second comparison signal KS 31 ′, in order to switch this second switch S 21 on during the negative half-cycle of the comparison voltage V 31 .

The voltage which is present across the first storage capacitance C 11 at the end of a positive half-cycle corresponds to the positive amplitude ΔV+ of the AC voltage component of the measurement voltage V 31 with respect to the offset potential, and is thus a measure of the lamp voltage V 10 during the positive half-cycle. The voltage which is present across the second storage capacitance C 21 at the end of the negative half-cycle corresponds to the amplitude ΔV−, which is negative with respect to the offset potential VR, of the AC voltage component of the measurement voltage V 31 , and is thus a measure of the amplitude of the lamp voltage V 10 during the negative half-cycle. In order to compare these amplitude values with one another and in this way to make it possible to diagnose possible wear, the evaluation circuit 32 has an assessment unit 33 , which produces the diagnosis signal S 30 .

This assessment unit 33 is fundamentally designed such that it reduces the voltage ΔV+ across the first capacitive storage element C 11 after the end of the positive half-cycle, and compares a reduced voltage ΔV+′, which results from this—and which is referred to in the following text as the reduced positive amplitude value—with the voltage ΔV− which occurs across the second capacitive storage element C 21 during the negative half-cycle. Furthermore, the assessment unit reduces the voltage ΔV− across the second capacitive storage element C 21 after the end of the negative half-cycle, and compares a reduced voltage ΔV−′, which results from this—and which is referred to in the following text as the reduced negative amplitude value with the voltage ΔV+ which occurs across the first capacitive storage element C 11 during the positive half-cycle. Wear is in this case identified when the positive amplitude value ΔV+ is less than the reduced negative amplitude value ΔV−′, or when the negative amplitude value ΔV− is less than the reduced positive amplitude value ΔV+′.

In the exemplary embodiment, the assessment unit 33 has a first additional capacitive storage element C 31 , which can be connected in parallel with the first capacitive storage element C 11 by means of a third switch S 31 . Those connections of the capacitors C 11 , C 31 which face away from the third switch S 31 are short-circuited, and are connected to offset potential VR via the first switch S 11 . The third switch S 31 is driven by the second control signal KS 31 ′ in order to connect the first additional capacitor C 31 in parallel with the first capacitive storage element C 11 during the negative half-cycle, with the first switch S 11 being open during this time period.

In a corresponding manner, the assessment unit 33 has a second additional capacitive storage element C 41 , which can be connected in parallel with the second storage capacitance C 21 by means of a fourth switch S 41 . Those connections of the capacitors C 21 , C 41 which face away from the fourth switch are short-circuited, and are connected to the offset potential VR via the second switch. The fourth switch S 41 is driven by the first comparison signal KS 31 in order to short-circuit the second capacitive storage element C 21 and the second further capacitive storage element C 41 during the positive half-cycles of the measurement voltage V 31 . The second switch S 21 is open during these half-cycles.

The method of operation of the assessment unit 33 will be explained in the following text with reference to the waveforms shown in FIGS. 6 c and 6 d . In this case, FIG. 6 c shows the waveforms of the first peak potential V 11 at the node N 11 , which is common to the diode D 11 and the capacitive storage element C 11 , of the first peak value detector and of a first comparison potential V 31 at the node which is common to the first capacitor C 11 and the first further capacitor C 31 . FIG. 6 d shows the waveform of the second peak potential V 21 at the node which is common to the diode D 21 and the capacitive storage element C 21 of the second peak value detector, and of the second comparison potential V 4 at the node which is common to the second capacitive storage element C 21 and the second further capacitive storage element C 41 .

With reference to FIGS. 5 and 6 c , the potential V 11 at the first peak value detector D 11 , C 11 rises during the positive half-cycles when the first switch S 11 is closed and the third switch S 31 is open to the maximum value of the comparison voltage V 3 , which corresponds to the sum of the offset potential VR and the positive amplitude value ΔV+. The first further capacitive storage element C 31 is connected between the two connections for the offset potential VR during this positive half-cycle, so that this capacitive storage element C 31 is discharged.

At the start of the negative half-cycle, the first switch S 11 is opened, and the third switch S 31 is closed. This leads to the first capacitive storage element C 11 being partially discharge. Assuming that the magnitude of the voltage across the first capacitive storage element C 11 at the end of the positive half-cycle corresponds to the magnitude of the positive amplitude ΔV+, the reduced positive amplitude value ΔV+′ is produced across the parallel circuit from the two capacitive storage elements C 11 , C 31 after closing of the third switch S 31 and after exchange of charge has occurred, for which:

Δ V+′=C 11/( C 11 +C 31 )·Δ V+=k 1 ·ΔV+   (3).

The reduced positive amplitude value ΔV+′ thus results from the positive amplitude ΔV+ by multiplication by a factor k 1 <1.

In order to make it possible to compare this reduced positive amplitude value ΔV+′ with the negative amplitude value ΔV−, a third comparison signal V 3 is produced, for which:

V 3 =VR−ΔV+′   (4).

After the opening of the first switch S 11 and the closing of the third switch S 31 , as a result of which the node N 11 of the first peak value detector is at the offset potential VR, this signal V 3 is produced between the node which is common to the capacitors C 11 , C 31 and the reference ground potential GND. The waveform of this third comparison signal V 3 is shown by dashed lines in FIG. 6 c . During the positive half-cycle, when the first switch S 11 is closed, this comparison signal V 3 corresponds to the offset potential VR.

After the first switch S 11 has been opened and the third switch S 31 has been closed, this third comparison signal V 3 first of all falls to a value which corresponds to the offset potential VR minus the positive amplitude value ΔV+, with the comparison signal V 3 rising to the value indicated in (4) owing to the discharging of the first storage capacitance C 11 as the negative half-cycle progresses further.

The comparison of the negative amplitude value ΔV− with the reduced positive amplitude value ΔV+′ is carried out by means of a first comparator K 11 , which compares the second comparison signal or the negative peak value signal V 21 =VR−ΔV− with the third comparison signal V 3 =VR−ΔV+′. A comparison of these two signals, which each have the magnitudes ΔV+′ and ΔV− with a negative mathematical sign and an additive component VR, which is in each case the same, makes it possible to draw a direct conclusion relating to the ratio between the negative signal value ΔV− and the reduced positive signal value ΔV+′. If the second comparison value V 21 is greater than the third comparison value V 3 , then the negative amplitude value ΔV− is less than the reduced positive amplitude value ΔV+′, which is interpreted as a fault. The output signal KS 11 from the first comparator K 11 then assumes a high level, which is stored in a first flipflop FF 11 at the end of the negative half-cycle, with a high level that results from this at the output of the first flipflop FF 11 leading via an OR gate OR 11 to a high level of the wear signal S 30 that is produced at the output. The wear signal thus assumes a high level when the positive amplitude value ΔV+ of the AC component of the signal V 31 is greater than the negative amplitude value ΔV− by more than a factor (C 11 +C 31 )/C 11 .

The second capacitive storage element C 21 is charged during the negative half-cycle of the comparison voltage V 3 to a voltage which corresponds to the negative amplitude ΔV− of the AC component of the voltage signal V 31 .

At the start of the positive half-cycle, the second switch S 21 is opened, and the fourth switch S 41 is closed. This leads to the second capacitive storage element C 21 being partially discharged. Assuming that the magnitude of the voltage across the second capacitive storage element C 21 at the end of the negative half-cycle corresponds to the magnitude of the negative amplitude ΔV−, the reduced negative amplitude value ΔV−′ is produced after closing of the fourth switch S 41 and the subsequent charge exchange across the parallel circuit formed by the two capacitive storage elements C 21 , C 41 , for which negative amplitude value ΔV−′:

Δ V−′=C 21/( C 21 +C 41)·Δ V−=k 2 ·ΔV−   (5).

The reduced negative value ΔV−′ thus results from the negative amplitude ΔV− by multiplication by a factor k 2 <1.

In order to make it possible to compare this reduced negative amplitude value ΔV−′ with the positive amplitude value ΔV+, a fourth comparison signal V 4 is produced, for which:

V 4 =VR+ΔV−′   (6).

After opening of the second switch S 21 and closing of the fourth switch S 41 , as a result of which the node N 21 of the second peak value detector is at the offset potential VR, this signal V 4 is produced between the node which is common to the capacitors C 21 , C 41 and the reference ground potential GND. The waveform of this fourth comparison signal V 4 is represented by dashed lines in FIG. 6 d . During the negative half-cycle, when the second switch S 21 is closed, this comparison signal V 4 corresponds to the offset potential VR.

After the opening of the second switch S 21 and the closing of the fourth switch S 41 , this fourth comparison signal V 4 initially rises to a value which corresponds to the offset potential VR plus the negative amplitude value ΔV−, with the comparison signal V 4 falling to the value indicated in (6) as a result of the discharging of the second storage capacitance C 21 as the positive half-cycle progresses further.

The comparison of the positive amplitude value ΔV+ with the reduced negative amplitude value ΔV−′ is carried out by means of a second comparator K 21 , which compares the first comparison signal or the positive peak value signal V 11 =VR+ΔV+ with the fourth comparison signal V 4 =VR+ΔV−′. A comparison of these two signals, which respectively have the magnitudes ΔV+′ and ΔV− with a positive mathematical sign, and an additive component VR which is in each case the same makes it possible to draw a direct conclusion on the ratio between the positive signal value ΔV+ and the reduced negative signal value ΔV−′. If the fourth comparison value V 4 is greater than the first comparison value V 11 , then the positive amplitude value ΔV+ is less than the reduced negative amplitude value ΔV−′, which is interpreted as a fault. The output signal KS 21 then the second comparator K 21 then assumes a high level, which is stored in a second flipflop FF 21 at the end of the positive half-cycle, with a high level which results from it at the output of the second flipflop FF 21 leading via the OR gate OR 11 to a high level of the wear signal S 30 which is produced at the output. The wear signal thus assumes a high level when the negative amplitude value ΔV− of the AC component of the signal V 31 is greater than the positive amplitude value ΔV+by more than a factor (C 21 +C 41 )/C 21 .

In the evaluation circuit 32 illustrated in FIG. 5 , the voltage which is present across the first capacitive storage element C 11 at the end of the positive half-cycle does not correspond entirely to the positive amplitude ΔV+, but is reduced in comparison to this amplitude by the value of the conducting-state voltage of the first diode D 11 . In a corresponding manner, the voltage across the second capacitive storage element C 21 at the end of the negative half-cycle does not correspond entirely to the negative amplitude ΔV−, but is reduced by the magnitude of the conducting-state voltage of the second diode D 21 in comparison to the magnitude of this negative amplitude ΔV−.

FIG. 7 shows a modification of the evaluation circuit 32 as shown in FIG. 5 , in which this problem is avoided. In this evaluation circuit, the first capacitive storage element C 11 is connected via the first switch S 11 to an increased offset potential VR+, which is greater than the offset potential by a fraction of a diode voltage. The reason for this will be described briefly in the following text:

To a first approximation, the diode voltages of D 11 and D 21 cancel one another out when compared at the inputs of the comparators K 11 and K 21 . To a second approximation, however, this results in an error because, for example, the diode voltage from D 21 is produced weighted by the factor 1 at the input of K 11 , while the diode voltage of D 11 is produced at the comparator input weighted by the factor C 11 /(C 11 +C 31 ). C 11 is thus charged to a voltage which is reduced by a fraction of a diode voltage, that is to say VR+ must be somewhat greater than VR.

Furthermore, the second capacitive storage element C 21 in this exemplary embodiment is connected via the second switch S 21 to a reduced offset potential VR−, which is less than the offset potential VR by a fraction of a diode voltage.

FIG. 8 shows a further exemplary embodiment of the diagnosis circuit according to the invention. This diagnosis circuit has a current/voltage converter 31 which produces two voltages V 311 , V 312 , one of which in each case represents the positive half-cycle of the measurement current I 1 or the lamp voltage V 10 , and one of which in each case represents the negative half-cycle of the measurement current I 1 or the lamp voltage V 10 . This current/voltage converter 31 is designed with respect to the waveforms shown in FIGS. 9 a to 9 c to produce the first voltage signal V 311 such that it assumes a predetermined offset value VR 2 during negative half-cycles of the measurement current I 1 , and such that it falls below this offset value VR 2 during positive half-cycles of the measurement current I 1 , with the waveform of the first voltage signal V 311 being linearly dependent during the positive half-cycle on the positive half-cycle of the measurement current I 1 multiplied by the factor −1.

The second voltage measurement signal V 312 is produced by the current/voltage converter such that the second voltage signal V 312 assumes the offset value VR 2 during the positive half-cycle of the measurement current I 1 , and such that this voltage signal V 312 is linearly dependent during the negative half-cycle on a measurement current I 2 that has been shifted by the offset VR 2 .

FIG. 10 illustrates a circuitry implementation example of a current/voltage converter which produces measurement voltages V 311 , V 312 , as shown in FIGS. 9 b and 9 c , from the measurement current I 1 . This current/voltage converter has an inverter, which has a resistor R 21 , a transistor T 21 connected in series with the resistor R 21 , and a transistor T 11 connected as a diode. The first voltage V 311 can in this case be tapped off with respect to the reference ground potential GND at a node which is common to the load path of the transistor T 21 and the resistor R 21 . The transistors T 21 and T 11 in the exemplary embodiment are in the form of npn bipolar transistors and are connected to form a balanced circuit, whose input is driven by the measurement current I 1 . During the positive half-cycle of the measurement current I 1 , the transistor T 21 becomes more conductive as the measurement current I 1 increases, so that the measurement voltage V 311 decreases as the positive measurement current I 1 increases.

The current/voltage converter also has a series circuit with a further resistor R 11 and a further transistor T 31 . In this exemplary embodiment, the measurement I 1 is injected at the emitter of the further transistor T 31 . The further transistor T 31 is permanently biased by a drive voltage which is between the threshold voltage Vbe and twice the threshold voltage Vbe of the further bipolar transistor T 31 . This ensures that this further transistor T 31 is switched off during a positive half-cycle of the measurement current I 1 . During a negative half-cycle of the measurement current I 1 , the emitter potential of the further transistor T 31 falls, so that this transistor starts to conduct. The bias voltage means that the emitter potential of the further transistor T 31 cannot fall to values below the reference ground potential GND. The second measurement signal V 312 essentially follows the measurement current I 1 during the negative half-cycle of the measurement current I 1 .

It should be noted that MOS transistors may, of course, also be used instead of the bipolar transistors illustrated in FIG. 10 .

The evaluation circuit 32 in the exemplary embodiment of the diagnosis circuit shown in FIG. 8 has a first peak value detector with a first capacitive storage element C 12 and a first detector element D 12 , which are connected in series between a positive supply potential of Vcc and a first output OUT 311 of the current/voltage converter, at which the first voltage signal V 311 is produced. In a corresponding manner, a second peak value detector is provided with a second capacitive storage element C 22 and a second detector element D 22 , which are connected in series between the positive supply potential of Vcc and a second output OUT 312 of the current/voltage converter 31 , at which the second voltage signal V 312 can be tapped off.

An assessment unit 33 in the example has a first additional capacitive storage element C 32 which can be connected in parallel with the first capacitive storage element C 12 by means of a first switch arrangement S 32 A-S 32 D. The assessment unit 33 also has a second additional capacitive storage element C 42 , which can be connected in parallel with the second capacitive storage element C 22 by means of a second switch arrangement S 42 A-S 42 D. The switch arrangements S 32 A-S 32 D and S 42 A-S 42 D are in each case designed such that the additional capacitive storage elements C 32 , C 42 and the switch arrangements S 32 A-S 32 D and S 42 A-S 42 D, respectively, each form a bridge circuit, so that the capacitive storage elements C 32 , C 42 can be selectively connected in a first polarity direction or in a second polarity direction in parallel with the capacitive storage elements C 12 , C 22 . Polarity reversal of the further capacitive storage elements C 32 , C 42 is in this case always carried out after one half-cycle of the measurement current I 1 . With respect to the first switch arrangement, this means that the switches S 32 A, S 32 B are switched on during one half-cycle, while the switches S 32 C, S 32 D are switched off, and that the two switches S 21 A, S 32 B are switched off during a next half-cycle, while the two other switches S 32 C, S 32 D are switched on. In a corresponding manner, the switches S 42 A, S 42 B are jointly switched on by the second switch arrangement during one half-cycle, while the switches S 42 C, S 42 D are switched on, and the two other switches S 42 A, S 42 B are switched off, during the next half-cycle.

The switches in the two switch arrangements S 32 A-S 32 D and S 42 A-S 42 D are switched as a function of control signals S 22 , S 22 ′ which are produced by comparison of the voltage measurement signals V 311 , V 312 by means of a comparator K 22 . A first control signal KS 22 in this case corresponds to the output signal from the comparator, and the second control signal KS 22 ′ corresponds to the output signal from the comparator K 22 , inverted by means of an inverter INV 11 . In the exemplary embodiment, the first control signal KS 22 assumes a high level during the positive half-cycles of the measurement current I 1 and during the positive half-cycles of the lamp voltage V 10 , and assumes a low level during the negative half-cycles. Respectively opposite switches in the switch bridge arrangements S 32 A-S 32 D and S 42 A-S 42 D, that is to say the switches S 32 A, S 32 B in the first switch arrangement and S 42 A, S 42 B in the second switch arrangement, are driven, for example, by the first control signal KS 22 , while the other opposite switches, that is to say the switches S 32 C, S 32 D in the first switch arrangement and S 42 C, S 42 D in the second switch arrangement, are driven by the second control signal KS 22 ′.

The method of operation of the evaluation circuit 32 as shown in FIG. 8 will be explained in more detail in the following text with reference to the waveforms shown in FIG. 9 . FIG. 9 d shows the waveform of a potential V 12 at a common node N 12 in the first capacitive storage element C 12 , and in the first detector element D 12 of the first peak value detector. During the positive half-cycle of the measurement current I 1 , this potential V 12 is drawn to a value which corresponds to the minimum value of the first voltage signal V 311 with respect to the reference ground potential GND. This minimum value of the first voltage signal V 311 during the positive half-cycle corresponds to the offset value VR 2 minus an amplitude value ΔV 1 which is proportional to the positive amplitude of the measurement current I 1 . In the example, the offset value VR 2 corresponds to the positive supply voltage Vcc minus a diode voltage of the first diode D 21 . A further diode, which is connected between the supply potential Vcc and the current/voltage converter, provides compensation for the voltage drop across the diode, so that the maximum value of the voltage which occurs across the parallel circuit formed by the first capacitive storage element C 12 and the first further capacitive storage element C 32 corresponds to the first amplitude value ΔV 1 . Thus, at the end of the positive half-cycle:

V 12 =Vcc−ΔV 1  (7).

The amplitude value ΔV 1 is referred to in the following text as the positive amplitude. V 12 is referred to in the following text as the first comparison value.

At the start of the negative half-cycle of the measurement current I 1 , the polarity of the second capacitive storage element C 32 is reversed, thus resulting in the first capacitive storage element C 12 being partially discharged, and in the potential V 12 at the first node N 1 rising. The voltage ΔV 1 ′ which is produced after the charge exchange across the parallel circuit formed by the first capacitive storage element C 1 and the second further capacitive storage element C 32 , and which is referred to in the following text as the reduced positive amplitude value results from the positive amplitude value ΔV 1 during the positive half-cycle in accordance with the following relationship:

Δ V 1′=( C 12 −C 32 )/( C 12 +C 32 )·Δ V 1  (8),

so that the potential V 12 at the end of the negative half-cycle is:

V 12 =Vcc−ΔV 1′  (9).

The first further capacitor C 32 is in this case selected such that its capacitance is less than that of the first capacitor C 12 .

During the negative half-cycle of the measurement current I 1 , a peak voltage ΔV 2 is produced across the parallel circuit of the second capacitor C 22 and the second further capacitor C 42 which is proportional to the negative amplitude of the measurement current I 1 , and is referred to in the following text as the negative amplitude value. Thus, during the negative half-cycle, a second potential V 22 is produced at a node which is common to the second capacitor C 22 and the second diode D 22 , which potential V 22 corresponds to the supply potential Vcc minus this second amplitude ΔV 2 , so that, at the end of the negative half-cycle:

V 22 =Vcc−ΔV 2  (10).

The amplitude value ΔV 2 is referred to in the following text as the negative amplitude value. V 22 is referred to in the following text as the second comparison value.

At the start of a positive half-cycle, the polarity of the second additional capacitive storage element C 42 is reversed, so that the voltage which is produced across the parallel circuit formed by the second capacitor C 22 and the additional capacitor C 42 falls to a value ΔV 2 ′ for which, at the end of the positive half-cycle:

Δ V 2′=( C 22 −C 42 )/( C 22 +C 42 )·Δ V 2.  (11).

This value ΔV 2 ′ is referred to in the following text as the reduced negative amplitude value.

The second comparison value V 22 at the end of the positive half-cycle is then:

V 22 =Vcc−ΔV 2′  (12)

The second further capacitor C 42 is in this case selected such that its capacitance is less than that of the second capacitor C 22 .

In order to determine wear, the positive amplitude value ΔV 1 is compared with the reduced negative amplitude value ΔV 2 ′, and the negative amplitude value ΔV 2 is compared with the reduced positive amplitude value ΔV 1 ′, with wear being assumed when the respective reduced value ΔV 1 ′ or ΔV 2 ′ is greater than the respective peak value ΔV 2 or ΔV 1 .

For this comparison, the first and second comparison signals V 12 , V 22 are compared by means of a comparator K 12 . An output signal from the comparator is in this case stored in a first flipflop FF 12 at the end of the positive half-cycle, and is stored in an inverted form in a second flipflop FF 22 at the end of the negative half-cycle, with the output signals in the flip-flops FF 12 , FF 2 being supplied to an OR gate OR 12 , at whose output the wear signal S 30 is produced.

If the first comparison value V 12 at the end of the positive half-cycle is greater than the second comparison value V 22 , then, taking into account (7) and (12) as well as (11), this means that:

Vcc−ΔV 1 >Vcc−ΔV 2′=>

Δ V 1<( C 22 −C 42 )/( C 22 +C 42)·Δ V 2=>

Δ V 1 <k 3 ·ΔV 2  (13)

In this case, a high level is produced at the output of the comparator K 12 at the end of the positive half-cycle, and this is stored in the first flipflop FF 12 and leads to the wear signal S 30 having a high level.

If the second comparison value V 22 at the end of the negative half-cycle is greater than the first comparison value V 12 , then this means, taking into account (9) and (10) as well as (8), that:

Vcc−ΔV 2 >Vcc−ΔV 1′=>

Δ V 2<( C 12 −C 32 )/( C 12 +C 32 )·Δ V 1=>

Δ V 1 <k 4 ·ΔV 2  (14)

In this case, a low level is produced at the output of the comparator K 12 at the end of the negative half-cycle, which is inverted and is stored as a high level in the second flipflop FF 22 , and leads to the wear signal S 30 having a high level.

In both cases, the high level of the wear signal is thus produced when the respective amplitude ΔV 1 or ΔV 2 during one half-cycle is less by a factor k 3 , k 4 , which is less than 1, than the amplitude during the respective other half-cycle. The capacitances C 12 , C 22 , C 32 , C 42 are in this case preferably selected such that the factors k 3 , k 4 are in each case the same.

In summary, in this exemplary embodiment as well, one capacitor is charged during one half-cycle with a voltage which is proportional to the maximum amplitude of a voltage measurement signal V 311 , V 312 during this half-cycle. During the next half-cycle, the capacitor is partially discharged, and the comparison value which results from it is compared with the peak voltage occurring during this half-cycle across the other capacitor, in order to use this to generate a diagnosis signal which indicates possible wear of the lamp. In the exemplary embodiment shown in FIG. 8 , this diagnosis signal S 30 assumes a high level when such wear is detected, that is to say when the first amplitude ΔV 1 of the signal component which is proportional to the measurement current of the first voltage measurement signal V 311 is greater by more than a predetermined factor than the second amplitude ΔV 2 , or when this second amplitude ΔV 2 of the signal component which is proportional to the measurement current of the second voltage measurement signal V 312 is greater by more than a predetermined factor than the first amplitude ΔV 1 . These factors are in this case dependent, in the manner explained above, on the ratio of the respective parallel-connected capacitors C 12 , C 32 and C 22 , C 42 .

A further exemplary embodiment of a diagnosis circuit according to the invention is illustrated in FIG. 11 . This diagnosis circuit has a number of current/voltage converter units, which each produce positive output voltages V 43 , V 53 , V 83 , V 93 , which are either proportional to the instantaneous value of the input current I 1 during one half-cycle or are proportional to the maximum value of the amplitude of the input current I 1 during one half-cycle.

In this diagnosis circuit, the measurement current I 1 is supplied directly to an inverting input converter, which has an operational amplifier OP 13 and a resistor R 13 which is connected between the negative input and the output of the operational amplifier OP 13 . A voltage V 13 with respect to the reference ground potential GND is produced at the output of this operational amplifier OP 13 , whose waveform is illustrated in FIG. 12 in comparison to the waveform of the input current I 1 . This voltage V 13 is zero during positive half-cycles of the input current I 1 , and assumes a positive value during negative half-cycles of the input current I 1 , with the signal value being proportional to the signal value of the input current I 1 , multiplied by −1, during the negative half-cycle. This input converter OP 13 , R 13 thus carries out the function of an inverting half-wave rectifier.

The output signal from this input converter is supplied to an instantaneous value output stage OP 43 , which has an operational amplifier whose positive input is supplied with the voltage V 13 , and at whose output an instantaneous value signal V 43 is produced, which is zero during positive half-cycles of the input current I 1 , and which has positive values during negative half-cycles of this input current I 1 , which positive values are proportional to the input current I 1 , multiplied by −1, during the negative half-cycles.

Furthermore, a second instantaneous value output stage OP 53 is provided, which has an operational amplifier OP 53 whose positive input is supplied with the input current I 1 , and whose negative input is coupled to its output. A second instantaneous value voltage V 53 is produced at the output of this second instantaneous value output stage OP 53 , which is zero during the negative half-cycle of the input current I 1 and is proportional to the input current I 1 during the positive half-cycle.

The diagnosis circuit 32 also has first and second peak value detectors 34 , 35 , with the first peak value detector 34 being supplied directly with the input current I 1 , and with the second peak value detector being supplied with the output signal V 13 from the half-wave rectifier OP 13 , R 13 . The two peak value detectors 34 , 35 have a respective input amplifier OP 63 , OP 73 , to which the respective input signal I 1 or V 13 is supplied at its positive input, and whose outputs are followed by a respective diode D 63 , D 73 . The cathode connection of the diode D 63 , D 73 is in this case fed back to the negative input of the operational amplifier OP 63 , OP 73 . The operational amplifier OP 63 , OP 73 with the downstream diode D 63 , D 73 results in a peak value detection, so that a value is in each case produced at the cathode connection of the diode D 63 of the first detector 34 at the end of the positive half-cycle which is proportional to the maximum value of the measurement current I 1 during the positive half-cycle. At the end of the negative half-cycle, a positive voltage which is proportional to the amplitude of the measurement current I 1 during the negative half-cycle is produced at the cathode connection of the diode D 73 of the second detector 35 .

A capacitor C 83 , C 93 , which is used as a hold element, is in each case connected downstream from the diodes D 63 , D 73 in the two peak value detector units 34 , 35 , via a respective resistor R 83 , R 93 . A voltage which is produced across these capacitors C 83 , C 93 is amplified by means of an output amplifier OP 83 , OP 93 in order to produce a positive peak value signal V 83 and a negative peak value signal V 93 . The positive peak value signal V 83 is in this case proportional to the positive peak value of the input current I 1 during the positive half-cycle, and the negative peak value signal is proportional to the negative amplitude of the measurement current I 1 during the negative half-cycle. The positive peak value signal V 83 , which is determined during the positive half-cycle, is held during the negative half-cycle, with reference to FIG. 12 , while the negative peak value signal V 93 , which is determined during the negative half-cycle, is held during the positive half-cycle.

Switches are connected in parallel with the capacitors C 83 , C 93 , with the switch S 83 which is connected in parallel with the capacitor C 83 being closed for a short time at the start of a positive half-cycle, in order to discharge the capacitor C 83 before the next charging process. A switch S 93 , which is connected in parallel with the capacitor C 93 , is in each case closed for a short time at the start of a negative half-cycle, in order to charge the capacitor C 93 before the next charging process.

Drive signals for these two switches S 83 , S 93 may, for example, be derived by means of a comparator, which is not illustrated, by comparison of the instantaneous value signals V 43 and V 53 , in order to produce a square-mode signal with a rising flank at the start of a negative half-cycle, and with a falling flank at the start of a positive half-cycle. This comparator signal can be supplied to a first delay element (not illustrated), which closes the switch S 93 for a predetermined time period after a rising flank of the comparator signal, and closes the switch S 83 for a predetermined time period after a falling flank of the comparator signal.

Further assessment units, which further process the instantaneous value output signals V 43 , V 53 or the peak value output signals V 83 , V 93 , are not illustrated in FIG. 11 . This further processing can be carried out in a manner which has been known for a long time. In order, for example, to determine whether the positive amplitude of the input current I 1 differs significantly from the negative amplitude of the measurement current I 1 , the difference between the peak value output signals V 83 , V 93 could be determined in a simple manner, in order to produce an error signal if this difference exceeds a predetermined value, and to suppress further driving of the lamp.

The diagnosis circuit also has a lamp detector, which has a switch S 33 which is connected between the input IN and the reference ground potential GND. This switch S 33 is fitted in a manner that is not illustrated in any more detail on, for example, a lamp socket in which the lamp 10 is inserted, and is closed when no lamp is inserted in the socket. In this case, the measurement input IN is at the reference ground potential GND, as is identified by a comparator OP 33 which compares the potential at the measurement input with a further reference potential REF 33 in order to prevent the half-bridge circuit Q 1 , Q 2 and the lamp (which is not present) from being driven.

Furthermore, the information about the positive and negative amplitudes of the measurement current I 1 , which are proportional to the positive and negative amplitudes of the lamp voltage 10 , can be used in the control circuit 21 for the half-bridge circuit Q 1 , Q 2 to vary the drive frequency in order in particular to optimize the preheating phase and the lamp starting process. In principle, a procedure such as this is described in the German Patent Application, submitted on the same date, entitled “Verfahren zur Ansteuerung einer eine Leuchtstofflampe aufweisenden Last zur Optimierung des Zündvorgangs” [Method for driving a load which has a fluorescent lamp, in order to optimize the starting process] inventors: Michael Herfurth, Martin Feldtkeller, Antoine Fery.

FIGS. 13 and 14 show a further exemplary embodiment of a drive circuit and, respectively, of a lamp ballast for a fluorescent lamp. The resistance element R 1 is in this case part of a direct-current path, to which a detector circuit 40 is coupled for detection of a current flowing through the direct-current path. In the exemplary embodiment, the direct-current path runs from the connecting terminal K 1 for the half-bridge circuit Q 1 , Q 2 , to which a supply potential for the half-bridge circuit is applied, via a further resistance element R 2 , the resonant inductrance L 1 , the first lamp filament or lamp electrode 11 and the resistance element R 1 to a terminal for a reference ground potential Vcc, in which case this reference ground potential Vcc is, for example, a supply potential for the components of the detector circuit 40 and of the drive circuit 21 which drives the half-bridge circuit Q 1 , Q 2 . This direct-current path, which runs via the first lamp filament 11 in the fluorescent lamp 10 , is closed only when a fluorescent lamp 10 is inserted and when the first lamp filament 11 is intact, that is to say it is electrically conductive.

The detector circuit 40 has a current detector 44 , which is connected in the direct-current path and is coupled to an evaluation circuit 45 , which produces a first detector signal S 45 which is supplied to the control circuit 21 .

A first diode D 41 is preferably connected in the direct-current path in the detector circuit 40 and allows current to flow only in the direction shown for the current I 1 in FIG. 13 . In order to limit the voltage in the detector circuit 40 in the event of a current flowing in the opposite direction to this, a second diode D 42 is provided, and is connected between the reference ground potential GND and the node which is common to the resistance element R 1 and the first diode D 41 .

The direct-current path in conjunction with the detector circuit 40 is used to identify whether a fluorescent lamp 10 is present, and whether the lamp is intact. This drive circuit prevents the half-bridge circuit Q 1 , Q 2 from being driven by the control circuit 21 when the control circuit receives information via the first detector signal S 45 that the direct current flowing via the direct-current path is below a predetermined threshold, thus indicating that no fluorescent lamp 10 has been inserted, or that the fluorescent lamp 10 is not intact. The comparison threshold for the detected current is produced in the example by a threshold detector 45 , to which the current detector 44 is coupled.

The resistance elements R 1 , R 2 in the direct-current path are selected, by way of example, such that the direct current which flows through the direct-current path when an intact fluorescent lamp 10 is inserted is between about 20 μA and 200 μA.

The detector circuit 40 can be used in particular in conjunction with the already explained diagnosis circuit 30 , as is illustrated in FIG. 13 . In this case, a switch S 13 is connected between the resistance element R 1 and the other components, that is to say the current/voltage converter 31 and the evaluation circuit 32 for the diagnosis circuit 30 , as is also illustrated in FIG. 11 . This switch S 13 is likewise driven by the control circuit 21 . In this context, it should be noted that the control circuit 21 for the half-bridge circuit Q 1 , Q 2 , the diagnosis circuit 30 and the detector circuit 40 preferably form a common integrated control circuit for the lamp ballast, and are integrated in a common semiconductor chip.

The method of operation of the arrangement shown in FIG. 13 will be explained in the following text:

When the ballast is switched on, with DC voltage Vb being applied to the input terminals K 1 , K 2 , the half-bridge circuit Q 1 , Q 2 is initially not driven, and the switch S 13 is opened, driven by the control circuit 21 . As soon as the detector circuit 40 detects a direct current above the predetermined threshold flowing through the direct-current path, the control circuit 21 starts to drive the half-bridge circuit Q 1 , Q 2 , with the switch S 13 being closed after the start or in conjunction with the start of this drive, in order to subsequently carry out a diagnosis of possible wear of the fluorescent lamp, via the diagnosis circuit 30 .

If the evaluation circuit 32 in the diagnosis circuit 30 detects wear of the fluorescent lamp 10 , which is signaled to the control circuit 21 via the diagnosis signal S 30 , the drive to the half-bridge Q 1 , Q 2 is interrupted, in order to interrupt the voltage supply to the fluorescent lamp. In addition, the switch S 13 is opened again by the control circuit 21 , and the current flowing through the direct-current path is evaluated once again by the detector circuit 40 .

After an interruption in the drive to the half-bridge as a result of wear, the control circuit 21 uses the first detector signal S 45 to detect whether the current flowing through the direct-current path has risen after a delay time from zero to a positive value. The rise in this direct current from zero to a positive value which is above a predetermined threshold once a delay time has elapsed following the half-bridge having been switched off as a result of wear indicates that a user has replaced the fluorescent lamp, in which case the control circuit drives the half-bridge Q 1 , Q 2 again once such a lamp change has been detected.

The embodiment illustrated in FIG. 14 does not require a switch S 13 , with the detector circuit 40 being used without the components 31 , 32 of the diagnosis circuit 30 that detects the wear.

The detector circuit 40 can optionally include a reference voltage source REF 41 , a resistor R 41 connected in series with the reference voltage source REF 41 , and a further diode D 43 , with the series circuit comprising the reference voltage source REF 41 , the switch SW 41 , the resistor R 41 and the diode D 43 being connected between the reference ground potential GND and the resistance element R 1 . A second threshold value detector 46 is connected to the node which is common to the resistor R 41 and to the diode D 43 , and supplies a second detector signal S 46 to the control circuit 21 . The switch SW 41 is likewise driven in a manner that is not described in any more detail by the control circuit 21 , and is closed before the start of the half-bridge Q 1 , Q 2 , when the switch S 13 is opened. The node which is common to the diode D 43 and the resistor R 1 is then at a potential which corresponds at least to the reference potential REF 41 .

This node which is common to the diode D 43 and to the resistor R 1 represents an interface between the integrated control circuit with the components 21 , 30 , 40 and the “outside world”. If the manufacturer of the ballast connects this node to a reference ground potential GND, which is in fact done only when the manufacturer does not fit the resistance elements R 1 , R 2 in the circuit, then it is possible in this way to signal to the control circuit 21 that the resistance elements R 1 , R 2 are not fitted, and that the diagnosis circuit should not be used, overall. This information is signaled to the control circuit 21 via the second detector signal S 46 from the second threshold detector 46 , which evaluates the potential at the node which is common to the resistor R 41 and the diode D 43 .

The operation of the half-bridge is also enabled by the control circuit 21 when the diagnosis circuit is not in use, with the switch S 13 in this case not being closed.

The option that has been explained is worthwhile in the case of integrated control circuits, which can be used optionally for one or more lamps and which have a corresponding number of diagnosis circuits, in order to shut down those diagnosis circuits which are not required.