Boost converter with series switch

1. Field of the Invention

This invention relates to the field of switching voltage converters, and particularly to boost converters which employ a switch in series with the boost converter output.

2. Description of the Related Art

Switching voltage converters are well-known and widely-used to provide regulated output voltages. Such converters can be configured in a number of different ways; one configuration is known as a “boost” converter, which can provide an output voltage that is greater than the input voltage supplied to the converter.

A basic boost converter is shown in FIG. 1 a . An inductor L 1 is connected between the input voltage V in and a switching node 10 , and a switch—here implemented with a field-effect transistor (FET) MN 1 —is connected between switching node 10 and a circuit common point 12 . A diode D 1 is connected in series between node 10 and the converter's output at node 18 . MN 1 is part of a switching circuit 14 which includes a controller 16 that cycles MN 1 so as to periodically connect L 1 across input voltage V in . When MN 1 is turned on, the voltage at switching node 10 (V sw ) goes low and the current in L 1 ramps up in proportion to the voltage across it and inversely to its inductance. When MN 1 is turned off, V sw goes high until D 1 conducts, a point when the voltage across the inductor is reversed and the current in L 1 ramps down. When V sw is sufficiently positive, current is conducted via D 1 to a load capacitor C 1 at the converter's output node 18 to produce the converter's output voltage V out . A feedback circuit 22 provides a signal which varies with the voltage at node 18 to controller 16 , which adjusts the duty ratio of MN 1 so as to regulate the voltage at node 18 . C 1 is made large enough to average the current pulses from L 1 through D 1 and keep the load ripple voltage below some desired minimum.

A common problem in the application of this type of boost converter is that, although the switching of MN 1 can be stopped by a control signal (not shown), V out will not go to zero if V in is present. Instead, the path from V in through L 1 and D 1 to output node 18 will keep V out from falling much below V in . In some applications, such as powering the control electronics for an LCD display, this feedthrough is undesirable. In these cases, V out should remain substantially zero when V in is initially applied, until other electronics also powered from V in can be activated.

FIG. 1 b illustrates a known solution to this problem. A series switch, typically a PMOS FET MP 1 , is connected between node 18 and a node 20 . Node 18 is now an intermediate node, and node 20 becomes the converter's output node at which output voltage V out is provided. A second load capacitor C 2 would typically be connected between node 20 and circuit common. MP 1 is controlled with a switch control circuit 24 ; when switch control circuit 24 holds MP 1 's gate voltage close to its source voltage, the switch will be off, and output voltage V out can remain substantially zero, even though C 1 may be charged to V in . After V in is applied and other circuits powered by V in have reached some desired operating condition, switch control circuit 24 can drive the gate of MP 1 low, turning it on and connecting the voltage on C 4 to output node 20 . This makes V out approximately equal to either V in by way of L 1 and D 1 if switching has not been initiated, or to the boosted voltage present on C 4 by virtue of having started the boost converter switching.

This solution has a drawback, however. The voltage on C 1 is regulated by the feedback loop connected to node 18 . This works well when node 18 is the converter's output node, but when the series switch is added, some regulation is lost due to MP 1 's series resistance. Therefore, in order to maintain good load regulation, a device which may be unacceptably large is needed for MP 1 to minimize this resistance.

A switching voltage converter is presented which overcomes the problem noted above, by enabling the use of an NMOS FET as the series switch.

The present converter, typically a boost converter, includes an input node for receiving an input voltage V in and an output node at which the converter provides an output voltage V out . A switching circuit includes an inductor coupled between V in and a switching node, and a switch connected to control the voltage applied across the inductor. A diode is connected between the switching node and an intermediate node to which a load capacitor is connected. The switching circuit is arranged to cycle the switch and thereby produce a switching voltage V sw at the switching node; the switching can be controlled so as to regulate the voltage at the intermediate node.

An n-type transistor, preferably an NMOS FET, is employed as a series switch, with its drain coupled to the intermediate node and its source coupled to the output node. A charge pump is driven by the switching voltage V sw to provide a voltage V on at the NMOS FET's gate input sufficient to turn the FET on. A series switch controller is arranged to, in response to a control signal, hold the NMOS FET off such that output voltage V out is approximately zero regardless of the status of input voltage V in , or allow the NMOS device to be turned on by V on .

NMOS FETs have a lower channel resistance than a comparably sized and driven PMOS device. Thus, by implementing the series switch with an NMOS FET a lower resistance and/or smaller die size can be achieved.

Further features and advantages of the invention will be apparent to those skilled in the art from the following detailed description, taken together with the accompanying drawings.

FIG. 1 a is a schematic diagram of a known boost converter.

FIG. 1 b is a schematic diagram of a known boost converter with series switch.

FIG. 2 is a block/schematic diagram of a boost converter with series switch per the present invention.

FIG. 3 a is a schematic diagram of one possible implementation of a boost converter with series switch per the present invention.

FIG. 3 b is a schematic diagram of another possible implementation of a boost converter with series switch per the present invention.

FIG. 4 a is a schematic diagram of another possible implementation of a boost converter with series switch per the present invention.

FIG. 4 b is a schematic diagram of another possible implementation of a boost converter with series switch per the present invention.

The present invention may be useful with various switching voltage converter configurations, but is particularly advantageous when employed with a boost converter due to the inherent input voltage feedthrough problem described above. For simplicity, a boost converter application is used to illustrate the present invention, though the series switch arrangement described herein could be used with other converter types. It should also be noted that, though the exemplary embodiments herein are described and shown implemented with FETs, bipolar transistors could also be used.

A boost converter with series switch per the present invention is shown in FIG. 2 . As described above, an input voltage V in is connected to one terminal of inductor L 1 , the other terminal of which is connected to switching node 10 . A switch—here implemented with a field-effect transistor (FET) MN 1 , though other types of switching devices could also be used—is connected between switching node 10 and a circuit common point 12 ; common point 12 is typically ground, but could also be a non-zero potential. MN 1 is part of a switching circuit 14 which includes a controller 16 that cycles MN 1 so as to periodically connect L 1 across input voltage V in . Diode D 1 is connected between switching node 10 and an intermediate node 18 , and load capacitor C 1 is connected between node 18 and common point 12 . As noted above, when MN 1 is turned on, V sw goes low and the current in L 1 ramps up, and when MN 1 is turned off, V sw goes high until D 1 conducts, a point when the voltage across the inductor is reversed and the current in L 1 ramps down. Feedback circuit 22 provides a signal which varies with the voltage at intermediate node 18 to controller 16 , which adjusts the duty ratio of MN 1 so as to regulate the voltage at node 18 .

The present converter includes a switch 30 connected in series between intermediate node 18 and the converter's output node 20 at which output voltage V out is provided. Switch 30 is implemented with an n-type transistor: either an NMOS FET (MN 2 , as shown) or an NPN bipolar transistor. The transistor's drain (collector) is connected to intermediate node 18 , and its source (emitter) is connected to output node 20 . An NMOS FET has a lower channel resistance than a comparably sized and driven PMOS device as might have been used in prior art designs. Thus, by implementing series switch 30 with an NMOS FET as described herein, a lower resistance and/or smaller die size can be achieved.

However, a complication of using an NMOS switch is that, to turn the switch on, its gate must be driven more positive than its source. Since V out is to be driven as close as is practical to the voltage on C 1 , this means that the gate of MN 2 needs to be driven more positive than any other voltage available from the boost converter. This is accomplished with the use of a charge pump 34 , which is driven by the switching voltage V sw that appears at node 10 when MN 1 is cycled. Charge pump 34 can develop a voltage approaching twice V out to drive MN 2 ; this voltage (V on ) is applied to the gate of MN 2 .

The present converter also includes a series switch control circuit 36 , which pulls the gate of MN 2 low or releases the gate in response to a control signal (CONTROL). When it is desired that V out be zero, control circuit 36 holds the gate of MN 2 low such that MN 2 is turned off. When V out is to come up, control circuit 36 releases MN 2 's gate. When the boost converter switching has been initiated and V on has increased such that MN 2 's gate is sufficiently positive with respect to its source, MN 2 will be turned on and V out becomes approximately equal to the boosted voltage on C 1 . In this way, output voltage V out can be made to remain substantially zero when V in is applied, and then allowed to be brought up to the desired value at the appropriate time—such as after other electronics also powered from V in have been activated.

The converter preferably includes a capacitor C 2 connected between output node 20 and circuit common point 12 , to provide a capacitive source for fast load current spikes.

A schematic diagram illustrating one possible implementation of charge pump 34 and series switch control circuit 36 is shown in FIG. 3 a . Charge pump 34 comprises a capacitor C 3 connected between switching node 10 and a node 40 , a diode D 2 connected between node 40 and output node 20 , a capacitor C 4 connected between output node 20 and a node 42 , and a diode D 3 connected between nodes 40 and 42 . Node 42 is coupled to the gate of series switch transistor MN 2 via a resistor 44 . Series switch control circuit 36 is implemented with an NMOS FET MN 3 connected between the gate of MN 2 and circuit common point 12 , and driven by CONTROL—which may be a ground-referenced signal.

When V out is to be zero, turning on MN 3 with CONTROL connects the gate of MN 2 to circuit common point 12 , thereby turning it off (assuming that circuit common point 12 is less than or equal to V out ). If MN 1 is held off by controller 16 , MN 3 will also discharge any voltage on C 4 so that even if MN 3 is subsequently turned off, MN 2 will remain off. Moreover, the voltage at the node 40 end of C 3 will be approximately zero, while the switching node end of C 3 is charged to V in .

If, in this condition, switching of MN 1 is initiated, C 3 will drive D 2 with respect to V out , and assuming C 3 is small relative to C 2 and/or R L , C 3 will be discharged to almost zero, having approximately zero volts at both ends. When MN 1 is cycled off, L 1 drives switching node 10 positive, and C 3 will drive D 3 , forward biasing it and charging C 4 .

If C 3 is large relative to C 4 , then the resulting voltage across C 4 can be a large fraction of V in —the approximate voltage across C 3 —and after only a few switching cycles, C 4 can be charged to a voltage close to the peaks of V sw . If MN 3 is turned off, this voltage is applied to the gate of MN 2 by way of resistor 44 . Since the voltage across C 4 may rise to a level approximately equal to the output boost voltage, on C 1 , the addition of a breakdown diode Z 1 may be advisable to limit the gate-source voltage applied to MN 2 .

If C 3 is small relative to C 4 , the amount of charge deposited in C 3 during each boost cycle will only make a small change in voltage across C 4 . As a result, the gate voltage of MN 2 will rise slowly, allowing a gradual pickup of the output load on C 1 . This may be desirable to limit inrush current through L 1 to the load as the boost converter is started.

A schematic diagram illustrating another possible implementation for the present switching converter is shown in FIG. 3 b . This configuration provides an alternative connection for diode D 2 —its anode is connected to intermediate node 18 rather than to C 4 —which may be used to precharge C 4 . In this arrangement, there is a path from V in to resistor 44 by way of L 1 , D 1 , D 2 , and D 3 . If, after power is applied to V in , MN 3 is turned off, MN 2 will be turned on by the voltage on C 4 . C 4 will be bootstrapped by its connection to V out , so that as V out rises D 3 may become reverse-biased and MN 2 can clamp V out to the voltage at the top of C 1 . C 4 will be discharged through resistor 44 , but only until it reaches the breakdown voltage of Z 1 (if present), whereafter it will only slowly discharge due to leakage. This arrangement can be used to pre-bias V out to just below V in before starting the boost converter. Once the converter starts, charge pump 34 will operate to restore any charge lost to leakage.

FIG. 3 b also shows an alternate connection for feedback circuit 22 . This connection allows the converter to regulate the load voltage, rather than the intermediate voltage on C 1 . This connection is desirable to improve load regulation by reducing the closed loop output impedance of the circuit to the load. Note that, when the feedback circuit is configured as shown in FIG. 3 b , MN 3 must be switched off so that the load can be reflected back to C 1 before the boost raises this intermediate voltage excessively, which could damage MN 1 and MN 2 . In the case where V out is precharged by turning on MN 2 before the boost converter, this should not be a problem, but using this feedback circuit connection in a circuit like that shown in FIG. 3 a would require that MN 3 be turned off before or within a few cycles of the time the converter is started.

Note that, for the charge pump of FIG. 3 b , there is a DC path from V in to the gate of series switch MN 2 , via L 1 , D 1 , D 2 , D 3 and resistor 44 . When MN 3 is on, MN 2 is held off, but when MN 3 is off, V in is conveyed to the gate of MN 2 and will start to drive the load. In contrast, for the charge pump of FIG. 3 a , there is no DC path from V in to MN 2 's gate. Thus, MN 3 can be turned on to set an off state and then turned off, and MN 2 will remain off until driven by the charge pump when the converter is started.

With the exception of inductor L 1 , diode D 1 , and capacitors C 1 and C 2 , the components of a switching converter in accordance with the present invention—including charge pump 34 , series switch 30 , and switch control circuit 36 —may be integrated on a common substrate. However, high voltage diodes (e.g., D 2 , D 3 ) and large capacitor values (e.g., C 1 , C 2 ) may be difficult and/or costly to include in the integrated circuit. FIG. 4 a shows an alternate version of the charge pump circuit specially adapted for integration with the boost converter. In junction isolated integrated circuits, most junctions which might be used as diodes also share another junction which diverts current from one of the desired junction terminals to a third terminal. Transistors are often used in the “diode connection” to avoid this problem. However the resulting diode-like structure is limited by the base-emitter reverse breakdown voltage of the transistors. In FIG. 4 a , D 2 is replaced by Q 1 , a diode-connected NPN, and D 3 is replaced by Q 2 , a diode-connected PNP. Resistor 44 and C 4 of the previous figures are removed and their functions taken over by device properties and sizing. A resistor 50 is added in series with C 3 to limit peak current in charge pump 34 , a feature that can be added to the other versions shown but is more important in a fully integrated version. All the components of this circuit except for L 1 , C 1 , C 2 , D 1 and presumably the load can readily be integrated on several types of IC processes, and included as part of a boost converter IC.

Because of their direct connections to Z 1 , the base-emitter voltage to which Q 1 and Q 2 can be driven is controlled by Z 1 , which is selected to have a breakdown voltage (less a forward diode drop) lower than that of Q 1 or Q 2 . Resistor 50 limits the peak currents to which these components can be driven, permitting them to be of minimum size.

When MN 1 is on, C 3 is charged with respect to V out through Q 1 . When MN 1 goes off and switching node 10 is driven positive by L 1 , the charge on C 3 is transferred to the gate circuit of MN 2 by Q 2 . If C 3 is sufficiently large, the charge will raise the voltage of MN 2 's gate by an amount sufficient to turn MN 2 on with the first pulse.

However, in order to be a low resistance switch, MN 2 will be a relatively large device having a large gate capacitance. If C 3 is small compared to this capacitance, the entire charge on C 3 will make only a small change in the gate voltage of MN 2 . After a number of cycles this will be sufficient to raise MN 2 's gate voltage beyond the threshold and MN 2 will start to turn on and raise V out toward the C 1 voltage. As it does so, the drain-gate capacitance of MN 2 will tend to reduce the gate-source voltage of MN 2 , and this charge must be replaced by C 3 . In effect, the voltage boosting action of the charge pump with large capacitors can be replaced by a drive current limited by the MN 1 switching voltage, the switching frequency, and C 3 . This current drives the gate of MN 2 until the rate of rise of its source results in an equal current out of the drain-gate capacitance. At this point, the rate of rise of V out will be limited by the current-limited charge pump. So, by choosing C 3 to have a value significantly less than the gate capacitance of MN 2 , the rate of rise of voltage V out can be controlled, and thereby the surge of current to charge the load and its capacitor can be easily limited. In effect, the gate capacitance of MN 2 replaces or eliminates the need for C 4 of the previous figures.

Once MN 2 's gate-source voltage reaches the breakdown voltage of Z 1 , MN 2 will clamp V out to C 1 , and continued charge pulses from C 3 will be diverted to Z 1 .

This circuit can automatically turn on V out when the boost converter starts. If MN 3 is turned on when V in , is first applied, for example by a power-on reset function, the gate of MN 2 will be driven to zero, and V out will be off even though C 1 may be charged to near V in . Once the voltages equilibrate and MN 3 is released, MN 2 will remain off until the boost switching is initiated. Then, as MN 1 switches to boost the C 1 voltage, MN 2 will come on slowly connecting V out to C 1 .

C 3 need have only enough capacitance to overcome the parasitic capacitance of Q 1 , Q 2 , and connecting wiring, while it swings their junctions to greater than the Z 1 voltage when driven by MN 1 . For a faster rise of V out , C 3 can be made proportionately larger, but most values will be very small (sub pF) and eminently integrable.

Q 1 and Q 2 could both be NPNs or PNPs, made from whichever transistor type is most compact in the IC process selected. However, by using two different transistor types (as shown), the above-mentioned parasitic device capacitance is limited to base-emitter capacitance, which will in general be the minimum attainable.

If the capacitance of C 3 will be selected to be much larger than the parasitic limit, a further simplification is possible; this is shown in FIG. 4 b . Here, Z 1 is made to be part of charge pump 34 , as well as MN 2 's gate voltage limiter. When C 3 drives negative, Z 1 is forward biased and takes the place of Q 1 to charge C 3 . As C 3 is driven positive, Q 2 becomes forward-biased, driving the MN 2 gate positive until it reaches the voltage limit set by Z 1 . It will often be the case that the parasitic capacitance of Z 1 to substrate or other nodes will be much larger than that of Q 1 , and the inclusion of Q 1 as in FIG. 4 a allows this capacitance to be part of the large capacitance at the gate of MN 2 . But if this is not an issue, the simpler circuit of FIG. 4 b can be used.

While particular embodiments of the invention have been shown and described, numerous variations and alternate embodiments will occur to those skilled in the art. Accordingly, it is intended that the invention be limited only in terms of the appended claims.