Electro-luminescence display device and driving method thereof

This application claims the benefit of the Korean Patent Application No. P2004-79539 filed on Oct. 6, 2004, which is hereby incorporated by reference.

1. Field of the Invention

The invention relates to an electro-luminescence display device, and more particularly, to a current-driven type electro-luminescence display device.

2. Description of the Related Art

Various flat panel display devices having a lightweight and a compact size have replaced a cathode ray tube (CRT). The flat panel display devices include a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), an electro-luminescence (EL) display, an organic light emitting display (OLED) and so on.

The OLED is classified into a passive matrix and an active matrix. The active matrix OLED includes a thin film transistor, whereas the passive matrix has no thin film transistor. The active matrix OLED (AMOLED) is more suitable for a display device having a large size and a high resolution. The OLED is a self-luminous display device which electrically excites a fluorescent organic compound to emit light. It operates at low voltage and is thinner than other flat display devices. Further, the OLED has excellent characteristics such as a wide viewing angle and a rapid response speed. The OLED is currently in use for various devices, such as a hand phone, a car navigation, a hand PC and etc.

FIG. 1 is a circuit diagram illustrating a pixel structure of a current-driven type electro-luminescence display device of the related art. Referring to FIG. 1 , the current-driven type electro-luminescence display device 100 includes an electro-luminescence (“EL”), a switch part 10 and a data line. The EL forms a pixel in accordance with the current strength. The switch part 10 includes switches S/W 1 , S/W 2 and S/W 3 and controls the current supplied to the EL. The data line DATA and first and second scan lines Scan 1 , Scan 2 supply a signal to the switch part 10 .

The first switch S/W 1 includes a drain that is connected to the data line DATA and a gate that is connected to the first scan line Scan 1 . The second switch S/W 2 has a gate that is connected to the first scan line Scan 1 and a drain that is connected to a source of the first switch S/W 1 . A storage capacitor Cstg is arranged between a high potential voltage VDD and a source of the second switch S/W 2 . A drive transistor D-TFT has a gate that is connected between the storage capacitor Cstg and the source of the second switch S/W 2 and a source that is connected to the high potential voltage VDD. The third switch S/W 3 includes a gate that is connected to the second scan line Scan 2 and the source is connected to a drain of the drive transistor D-TFT. The EL is connected between a drain of the third switch S/W 3 and a ground GND.

FIG. 2 illustrates a drive waveform for the electro-luminescence display device 100 of FIG. 1 . In an interval A of FIG. 2 , a low voltage applies to the first scan line Scan 1 . The first switch S/W 1 and the second switch S/W 2 are turned on. When the first and second switches S/W 1 , S/W 2 are turned on, the drive transistor D-TFT forms a diode connection. The current sinks to the data line DATA through the drive transistor D-TFT.

In an interval B, the first and second switches S/W 1 and S/W 2 are turned-off and the drive transistor D-TFT is turned on by a storage capacitor Cstg. The third switch S/W 3 is turned on with a low voltage supplied to the second scan line Scan 2 so that a current corresponding to a designated data value flows in the EL for one frame period.

FIG. 3 illustrates parasitic capacitors which are hidden in the electro-luminescence display device 100 . A first parasitic capacitor C 1 is formed between the gate and source of the second switch S/W 2 . A second parasitic capacitor is formed between the source of the second switch S/W 2 and the source of the third switch S/W 3 . A third parasitic capacitor C 3 is formed between the gate and the source of the third switch S/W 3 . Due to the influence of the parasitic capacitors C 1 , C 2 and C 3 , when the first switch and the second switch S/W 1 , S/W 2 are turned off, a DC voltage offset is generated and a kickback effect occurs. The kickback effect occurs in particular where the first and second switches S/W 1 , S/W 2 are turned off and the third switch S/W 3 is turned on.

Referring to FIG. 4 , a kickback voltage develops in the first parasitic capacitor C 1 by as much as ΔVp1 in a direction of increasing the gate voltage of the drive transistor D-TFT. A kickback voltage also develops in the third parasitic capacitor C 3 by as much as ΔVp2 in a direction of decreasing the gate voltage of the drive transistor D-TFT. As a result, the kickback voltage may not be entirely cancelled and a voltage difference by “D” is generated. The voltages ΔVp1 and ΔVp2 are computed with the following equation (2):

Δ ⁢ ⁢ Vp ⁢ ⁢ 1 = C ⁢ ⁢ 1 C ⁢ ⁢ 1 + C ⁢ ⁢ 2 + C ⁢ ⁢ 3 + Cstg × Δ ⁢ ⁢ Vgs ⁢ ⁢ 1 ( Equation ⁢ ⁢ 1 ) Δ ⁢ ⁢ Vp ⁢ ⁢ 2 = C ⁢ ⁢ 2 + C ⁢ ⁢ 3 C ⁢ ⁢ 1 + C ⁢ ⁢ 2 + C ⁢ ⁢ 3 + Cstg × Δ ⁢ ⁢ Vgs ⁢ ⁢ 3 ( Equation ⁢ ⁢ 2 )

where ΔVgs1 is a change amount of a threshold voltage between the gate and the source of the first switch S/W 1 , and ΔVgs3 is a change amount of a threshold voltage between the gate and the source of the third switch S/W 3 .

The kickback effect may result in a non-uniformity of a picture quality. A displayed picture appears inconsistent and uneven in accordance with its characteristics. Accordingly, there is a need of a current-driven type electro-luminescence display device which provides an improved uniformity of a picture quality.

By way of introduction only, an electro-luminescence display device includes a plurality of column lines, a plurality of first row lines, and a plurality of second row lines. The plurality of first row lines intersect the column lines and a first scan signal is supplied thereto. The plurality of second row lines intersects the column lines and a second scan signal is supplied thereto. The second scan signal is later than the first scan signal. Organic light emitting devices are formed at pixel areas. The pixel areas are defined by the column lines and the first and second row lines. The electro-luminescence display device includes at least two drive switches and a compensation circuit which operates to be complementary to each other with the drive switch. The compensation circuit operates to compensate a kickback voltage generated upon a voltage change of the first row line. In one embodiment, the compensation circuit operates to generate an offset kickback voltage upon a voltage change of the second row line.

A driving method of an electro-luminescence display device includes installing a kickback compensation circuit adjacent a drive switches, and compensating a kickback voltage which is generated upon a voltage change of the first row line by use of the kickback compensation circuit.

The following detailed description of the embodiments reference the accompanying drawings, in which:

FIG. 1 is a circuit diagram representing a pixel area of a related art current-driven type electro-luminescence display device;

FIG. 2 illustrates a drive waveform for the electro-luminescence display device of FIG. 1 ;

FIG. 3 illustrates parasitic capacitors in the electro-luminescence display device of FIG. 1 ;

FIG. 4 is a chart illustrating a voltage change in connection with the electro-luminescence display device of FIG. 3 ;

FIG. 5 is a block diagram of a current-driven type electro-luminescence display device;

FIGS. 6A and 6B are circuit diagrams representing a pixel structure in the electro-luminescence display device of FIG. 5 ;

FIG. 7 illustrates a signal flow via a first scan line;

FIG. 8 illustrates a signal flow via a second scan line;

FIG. 9 illustrates parasitic capacitors in connection with the pixel structure of FIG. 6A ; and

FIG. 10 illustrates a voltage change amount in connection with the parasitic capacitors of FIG. 9 .

FIG. 5 is a block diagram illustrating a current-driven type electro-luminescence display device 500 . Referring to FIG. 5 , the current-driven type electro-luminescence display device 500 includes m×n numbers of pixels which are arranged in a matrix pattern. A pixel area is formed between m numbers of data lines DL 1 to DLm and n numbers of first and second scan lines Scan 11 to Scan 1 n and second scan lines Scan 21 to Scan 2 n . A data drive circuit 72 supplies a data to the data lines DL 1 to DLm and a scan drive circuit 73 sequentially supplies a scan signal to the first and second scan lines Scan 11 to Scan 1 n , Scan 21 to Scan 2 n.

A pixel structure of the current-driven type electro-luminescence display device 500 will be described in detail in conjunction with FIGS. 6A and 6B . Referring to FIG. 6A , the pixel structure includes a data line DL, first and second scan lines Scan 1 and Scan 2 and a drive switch 80 to drive pixels. The drive switch 80 includes a storage capacitor Cstg.

The drive switch 80 includes a first switch S/W 1 , a second switch S/W 2 , a third switch S/W 3 , a fourth switch S/W 4 and a storage capacitor. In the first switch S/W 1 , a drain is connected to the data line DL and a gate is connected to the first scan line Scan 1 . In the second switch S/W 2 , a gate is connected to the first scan line Scan 1 and a drain is connected to a source of the first switch S/W 1 . In the third switch S/W 3 , a gate is connected to the second scan line Scan 2 and a drain is connected to the source of the second switch S/W 2 . The storage capacitor Cstg is arranged between a high potential voltage VDD and a source of the third switch S/W 3 . The drive switch 80 includes a drive transistor D-TFT of which a gate is connected between the storage capacitor Cstg and the source of the third switch S/W 3 . A source of the drive transistor D-TFT is connected to the high potential voltage VDD. The driver switch 80 further includes a fourth switch S/W 4 of which a gate is connected to the second scan line Scan 2 and a source is connected to the drain of the drive transistor D-TFT. An EL is connected between a drain of the fourth switch S/W 4 and a ground GND. The source and the drain of the third switch S/W 3 are connected to each other. With that arrangement, the third switch S/W 3 may be equivalent to a capacitor as shown in FIG. 6B .

The drive transistor D-TFT operates in a self compensation method which compensates a voltage by itself with the storage capacitor Cstg. The storage capacitor Cstg is connected between the gate and the source of the transistor D-TFT. Accordingly, in the current-driven type electro-luminescence display device 500 , a current corresponding to a designated data value equally flows in each EL regardless of the characteristics change of the drive transistor device of an adjacent pixel. Further, such data value is sustained for one frame period after the first and second switches S/W 1 , S/W 2 are turned off by charging a data voltage in the storage capacitor Cstg.

A driving method of the current-driven type electro-luminescence display device will be described in conjunction with FIGS. 6A to 8 . As noted above, FIG. 2 illustrates the drive waveform for use with the electro-luminescence display device. In the A period, the high potential voltage VDD applies to the first scan line Scan 1 . The first and second switches S/W 1 , S/W 2 are turned on as shown in FIG. 7 . At this time, a high potential voltage VDD is charged in the storage capacitor Cstg and a current subsequently flows through a path formed by the first and second switches S/W 1 and S/W 2 . The voltage sinks at the data line through the first switch S/W 1 via the drive transistor D-TFT by as much as the potential difference between the high potential voltage VDD and the voltage which remains in the storage capacitor Cstg. For example, electric charge stored in the storage capacitor Cstg is 2V and the high potential voltage VDD is 10V. The remaining voltage, i.e., 8V flows through the drive transistor D-TFT and the voltage sinks to the data line through the first switch S/W 1 .

In the B period, the high potential voltage VDD flows in the EL through the fourth switch S/W 4 as shown in FIG. 8 and at this moment, the designated current activates the EL for operation. While the voltage supplied to the first scan line Scan 1 is changed from a low voltage to a high voltage, the voltage supplied to the second scan line Scan 2 is changed from the high voltage to the low voltage. Accordingly, the first and second switches S/W 1 , S/W 2 are turned off and the third and fourth switches S/W 3 , S/W 4 are turned on. The second scan signal operates to activate the drive switch later than the first scan signal. The high, potential voltage VDD is supplied to the EL through the drive transistor D-TFT via the fourth switch S/W 4 for a period except for the A period within one frame period. The designated current flows in the EL from the high potential voltage VDD.

FIG. 9 illustrates parasitic capacitors of the current-driven type electro-luminescence display device. Referring to FIG. 9 , the parasitic capacitors includes a first parasitic capacitor C 1 , a second parasitic capacitor C 2 , a third parasitic capacitor C 3 and a fourth parasitic capacitor C 4 . The first parasitic capacitor C 1 is formed between the gate and the source of the second switch S/W 2 . The second parasitic capacitor C 2 is formed between the source of the second switch S/W 2 and the source of the fourth switch S/W 4 . The third parasitic capacitor C 3 is formed between the source of the second switch S/W 2 and the second scan line Scan 2 . A fourth parasitic capacitor C 4 is formed between the gate and the source of the fourth switch S/W 4 .

When the first and second switches S/W 1 , S/W 2 are turned off, a kickback effect is generated by the first parasitic capacitor C 1 in a direction of increasing the gate voltage of the drive transistor D-TFT. This kickback effect cancels off another kickback effect which is generated by the third and fourth parasitic capacitors C 3 , C 4 in a direction of decreasing the gate voltage of the drive transistor D-TFT as a whole. The kickback voltage is generated in the first parasitic capacitor C 1 by as much as ΔVp1 in a direction of increasing the gate voltage of the drive transistor D-TFT. The kickback voltage is also generated in the third parasitic capacitor C 3 by as much as ΔVp3 in a direction of decreasing the gate voltage of the drive transistor D-TFT. Further, the kickback voltage occurs in the fourth parasitic capacitor C 4 by as much as ΔVp4 in a direction of decreasing the gate voltage of the drive transistor D-TFT. The kickback voltage is cancelled off as a whole, as shown in FIG. 10 . The third switch S/W 3 may be determined to be a value that may cancel off the kickback effect which is generated with the first and second switches S/W 1 , S/W 2 .

The kickback voltage represented by ΔVp1, ΔVp3 and ΔVp4 are computed with the following equations:

Δ ⁢ ⁢ Vp ⁢ ⁢ 1 = C ⁢ ⁢ 1 C ⁢ ⁢ 1 + C ⁢ ⁢ 2 + C ⁢ ⁢ 3 + C ⁢ ⁢ 4 + Cstg × Δ ⁢ ⁢ Vgs ⁢ ⁢ 1 ( Equation ⁢ ⁢ 3 ) Δ ⁢ ⁢ Vp ⁢ ⁢ 3 = C ⁢ ⁢ 3 C ⁢ ⁢ 1 + C ⁢ ⁢ 2 + C ⁢ ⁢ 3 + C ⁢ ⁢ 4 + Cstg × Δ ⁢ ⁢ Vgs ⁢ ⁢ 3 ( Equation ⁢ ⁢ 4 ) Δ ⁢ ⁢ Vp ⁢ ⁢ 4 = C ⁢ ⁢ 2 + C ⁢ ⁢ 4 C ⁢ ⁢ 1 + C ⁢ ⁢ 2 + C ⁢ ⁢ 3 + C ⁢ ⁢ 4 + Cstg × Δ ⁢ ⁢ Vgs ⁢ ⁢ 4 ( Equation ⁢ ⁢ 5 )

wherein ΔVgs1 is a change amount of a threshold voltage between the gate and the source of the first switch S/W 1 , ΔVgs3 is a change amount of a threshold voltage between the gate and the source of the third switch S/W 3 , and ΔVgs4 is a change amount of a threshold voltage between the gate and the source of the fourth switch S/W 4 .

As described above, the current-driven type electro-luminescence display device may prevent the kickback effect of various sizes. Accordingly, the current supplied to the EL may be uniform and the picture quality defect may be prevented. As a result, an overall picture quality may substantially improve.

Although the present invention has been explained by the embodiments shown in the drawings described above, it should be understood to the ordinary skilled person in the art that the invention is not limited to the embodiments, but rather that various changes or modifications thereof are possible without departing from the spirit of the invention. Accordingly, the scope of the invention shall be determined only by the appended claims and their equivalents.