Non-volatile memory structure and method of fabricating non-volatile memory

This application claims the priority benefit of Taiwan application serial no. 94102599, filed on Jan. 28, 2005. All disclosure of the Taiwan application is incorporated herein by reference.

1. Field of the Invention

The present invention relates to a method of fabricating a memory device. More particularly, the present invention relates to a non-volatile memory structure and a method of fabricating a non-volatile memory.

2. Description of the Related Art

Non-volatile memory is a type of writable and erasable data that can be retained even after power to the device is cut off. In addition, non-volatile memory occupies a small volume and has a fast accessing speed with low power consumption. Moreover, since the data can be erased in a block-by-block mode, the operating speed is fast. Therefore, non-volatile memory has become one of the most popular memory devices in personal computers and other electronic equipment.

A typical non-volatile memory comprises a plurality of memory cells. Each memory cell has a tunneling layer, a floating gate, an inter-gate dielectric layer and a control gate layer sequentially stacked over each other. In general, the larger the gate coupling ratio (GCR) between the control gate layer and the floating gate layer, the lower the operating voltage needed to operate the memory. Consequently, manufacturers are striving hard to increase the capacitance of the inter-gate dielectric layer so that the gate coupling ratio can be increased. One way of increasing the capacitance of the inter-gate dielectric layer is to increase the overlapping area between the control gate layer and the floating gate layer. However, as the level of integration continues to increase, line width of the devices is getting smaller. Since there is very little space for increasing the overlapping area between the control gate layer and the floating gate layer, the performance of the memory device is ultimately affected.

Accordingly, at least one objective of the present invention is to provide a method of fabricating a non-volatile memory capable of increasing the gate coupling ratio and improving device performance.

To achieve this and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of fabricating a non-volatile memory. First, a substrate having a tunneling layer and a floating gate layer thereon is provided. A mask layer is formed on the floating gate layer. The mask layer has a plurality of openings that expose a portion of the floating gate layer. Then, a portion of the floating gate layer is removed from the openings to form sunken regions on the floating gate layer. An inter-gate dielectric layer is formed on the floating gate layer. After that, a control gate layer is formed on the inter-gate dielectric layer. Finally, the mask layer and the floating gate layer under the mask layer are removed.

The present invention also provides a method of fabricating a non-volatile memory. First, a tunneling layer is formed on a substrate and then a floating gate layer is formed on the tunneling layer. Next, a mask layer is formed on the floating gate layer. The mask layer has first openings that expose a portion of the floating gate. After that, a portion of the floating gate layer is removed from the first openings to form sunken regions in the floating gate layer. An inter-gate dielectric layer is formed over the floating gate layer. Then, a control gate layer is formed on the inter-gate dielectric layer to fill the first openings. A cap layer is formed on the control gate layer. Next, the mask layer and the floating gate layer under the mask layer are removed to form second openings. A dielectric layer is formed on the sidewalls of the second openings. Finally, a select gate layer is formed inside the second openings.

According to the preferred embodiment of the present invention, the step of removing a portion of the floating gate layer to form sunken regions includes carrying out an oxidation so that the exposed floating gate layer reacts with oxygen to form an oxide layer and then removing the oxide layer. The method of removing the oxide layer includes performing a wet etching process.

According to the preferred embodiment of the present invention, after forming the control gate layer over the inter-gate dielectric layer but before removing the mask layer and the floating gate layer under the mask layer, further includes performing a thermal oxidation process to form an oxide layer on the surface of the exposed control gate layer.

According to the preferred embodiment of the present invention, after removing the mask layer and the floating gate layer under the mask layer, further includes forming a dielectric layer on the sidewalls of the floating gate layer, the inter-gate dielectric layer and the control gate layer. Then, a select gate layer is formed inside the sunken hole. The method of forming the dielectric layer includes performing a high-temperature oxidation process.

According to the preferred embodiment of the present invention, the tunneling layer can be a dielectric material such as a silicon oxide layer. The floating gate layer, the control gate layer and the select gate layer can be a conductive material such as polysilicon or doped polysilicon. Furthermore, the mask layer can be a material, such as silicon nitride, having an etching selectivity that differs from the floating gate layer. In addition, the inter-gate dielectric layer can be a silicon oxide layer or an oxide/nitride/oxide composite stack, for example.

The present invention utilizes sunken regions on the surface of the floating gate layer to increase the capacitance of the inter-gate dielectric layer between the floating gate layer and the control gate. Hence, the gate-coupling ratio between the floating gate layer and the control gate is increased. As a result, device performance is improved and the voltage needed to operate the device is reduced.

It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

FIGS. 1A through 1F are schematic cross-sectional views showing the steps for fabricating a non-volatile memory according to one preferred embodiment of the present invention.

Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

FIGS. 1A through 1F are schematic cross-sectional views showing the steps for fabricating a non-volatile memory according to one preferred embodiment of the present invention.

As shown in FIG. 1A , the method of fabricating a non-volatile memory in the present invention includes forming a tunneling layer 102 and a floating gate layer 104 sequentially over a substrate 100 . The substrate 100 can be a silicon substrate, for example. The tunneling layer 102 can be a dielectric material including silicon oxide or other charge tunneling material, for example. The tunneling layer 102 is formed, for example, by performing a thermal oxidation process or other suitable process. Furthermore, the floating gate layer 104 can be a conductive material including polysilicon, doped polysilicon or other suitable material. The method of forming the floating gate layer 104 includes performing a chemical vapor deposition process or other suitable process.

A mask layer 106 is formed on the floating gate layer 104 . The mask layer 106 has openings 108 that expose a portion of the floating gate layer 104 . The mask layer 106 can be a material such as silicon nitride or other suitable material having an etching selectivity that differs from the floating gate layer 104 . The method of forming the mask layer 106 includes depositing mask material to form a mask material layer (not shown) on the floating gate layer 104 and then forming a patterned photoresist layer 110 over the mask material layer. Using the patterned photoresist layer 110 as a mask, the mask material layer is etched. Finally, the patterned photoresist layer 110 is removed to form a structure as shown in FIG. 1B .

Next, referring to the structure in FIG. 1B , sunken regions are formed on the surface of the floating gate layer 104 exposed by the openings 108 . For example, an oxidation process is carried out so that oxygen can react with the silicon material on the floating gate layer 104 to form a silicon oxide layer 112 . After removing the silicon oxide layer 112 , sunken regions are formed on the surface of a floating gate layer 104 a as shown in FIG. 1C . The method of removing the silicon oxide layer 112 includes performing a wet etching process using hydrofluoric acid solution as the etchant, for example.

Note that other etching process could be used to form sunken regions on the surface of the floating gate layer aside from the aforementioned process. In other words, the oxidation and etching process described in the aforementioned embodiment should be regarded as an example only and should by no means limit the method of forming sunken regions on the floating gate layer as such.

As shown in FIG. 1D , an inter-gate dielectric layer 114 is formed on the floating gate layer 104 a . The inter-gate dielectric layer 114 is a silicon oxide layer, an oxide/nitride/oxide composite stack or other suitable material layer, for example.

Then, a control gate material layer 116 is formed on the inter-gate dielectric layer 114 . The control gate material layer 116 can be a conductive material such as polysilicon, doped polysilicon or other suitable material. In addition, the method of forming the control gate material layer 116 includes, for example, performing a chemical vapor deposition process of other suitable process.

As shown in FIG. 1E , the control gate material layer 116 outside the openings 108 is removed to form control gate layers 116 a . The method of removing the control gate material layer 116 includes performing a chemical mechanical polishing operation or an etching back process using the inter-gate dielectric layer 114 as a polishing stop or etching stop layer.

Next, an oxidation process is carried out to form an oxide layer 118 on the exposed control gate layer 116 a . The oxidation process is a thermal oxidation process, for example. For example, if the control gate layer 116 a is a polysilicon layer, then the oxide layer 118 formed after the oxidation process is a silicon oxide layer. The oxide layer 118 serves as a cap layer to protect the underlying film layer in a subsequent operation.

As shown in FIG. 1F , the mask layer 106 and the floating gate layer 104 a under the mask layer 106 are removed so that the inter-gate dielectric layer 114 and the oxide layer 118 above the mask layer 106 are also removed. Hence, a stack layer 120 comprising a floating gate layer 104 b , an inter-gate dielectric layer 114 a , a control gate layer 116 a and an oxide layer 118 a is formed. The method of removing the mask layer 106 and the floating gate layer 104 a includes performing an etching process, for example.

In one embodiment, a dielectric layer 122 is also formed on the sidewalls of the stack layer 120 . The dielectric layer 122 is a silicon oxide layer or other suitable material layer formed, for example, by performing a high-temperature oxidation (HTO) or other suitable process. After that, a conductive layer 124 is formed on the dielectric layer 122 , the original location of the removed mask layer 106 , the floating gate layer 104 a , the inter-gate dielectric layer 114 and the oxide layer 118 . In particular, the dielectric layer 122 may serve as an inter-gate dielectric layer that provides a path for the movement of electric charges in a memory erase operation. In addition, the conductive layer 124 may serve as a select gate.

In summary, the present invention utilizes sunken regions on the surface of the floating gate layer to increase the capacitance of the inter-gate dielectric layer between the floating gate layer and the control gate. Therefore, the gate-coupling ratio between the floating gate layer and the control gate is increased. Ultimately, device performance is improved and the voltage needed to operate the device is reduced.

It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.