Semiconductor memory device having controller with improved current consumption

1. Field of the Invention

The present invention relates to a semiconductor memory device in which current consumption is reduced in a read operation, and more specifically, to a semiconductor memory device in which the current consumed in a column address counter and a latch in the read operation can be reduced.

2. Discussion of Related Art

FIG. 1 is a functional block diagram illustrating the configuration of a DDR SDRAM in the prior art.

A control logic 10 includes a command decoder 20 and a mode register 30 . A clock enable signal CKEn, a clock signal CK, a clock bar signal /CK, a chip select signal /CSn, a write enable signal /WE, a column address strobe signal /CAS and a row address strobe signal /RAS are input to the control logic 10 . Further, block select addresses BA 0 , BA 1 and addresses A 0 to A 13 are input to the control logic 10 through an address register 40 . The command decoder 20 generates read, write and precharge commands, etc. according to an input signal. The mode register 30 generates a CAS latency value and a burst length value according to an input address. A row address multiplexer 60 generates a row address according to an input address and also generates the row address according to an address outputted from a refresh counter 50 .

A bank row address latch and decoder 90 outputs a bank select signal for selecting a memory bank, and is controlled by means of a bank control logic 70 . A column decoder 130 generates a column address according to input addresses. A column address counter and latch 80 generates a plurality of column addresses for a burst operation if an address is received, and provides the generated column addresses to the column decoder 130 . The column address counter and latch 80 also generates a signal col 0 that divides even and odd regions of a memory bank. A bank memory array 100 is composed of a plurality of memory banks. The memory banks are selected according to a bank select signal. Each of the memory banks consists of a plurality of cells, which are selected according to a row address and a column address. A I/O gating DM mask logic 120 controls the input of data to the memory banks. Data write is controlled according to a data mask signal.

The data of the memory banks are amplified in a sense amplifier 110 and then latched in a read latch 140 via the I/O gating DM mask logic 120 . The data latched in the read latch 140 is transferred to a driver 170 according to the operation of a multiplexer 150 . The data is synchronized to DQS data from a DQS generator 180 and then outputted to an external chipset.

The data from the external chipset is input to a receiver 200 in synchronism with external DQS data. The data from the receiver 200 is stored in an input register 210 and input to the write FIFO and driver 190 . The data from the write FIFO and driver 190 is written into a corresponding cell through the I/O gating DM mask logic 120 and the sense amplifier 110 according to a mask signal. Meanwhile, a clock CLK is applied to the driver 170 through a delay lock loop (DLL) 160 .

The DDR SDRAM constructed above needs a column address counter because there exists a burst operation in the read and write operations. The column address counter operates in accordance with a timing at which the sense amplifier reads or writes data. That is, in the read operation, the column address counter operates at a clock to which a read command is applied. In the write operation, it operates after 2*tCK since a write command is applied. This is because 1*tCK is needed to align internal data, as can be seen from FIG. 2 . In the DDR SDRAM, write data are applied later than the write command. It is also required that data latched at the rising edge of DQS be aligned at the falling edge of DQS, as shown in FIG. 2 . In other words, a data D 0 is latched at a first rising edge of DQS, and the data D 0 is aligned while a data D 1 is latched at a first falling edge of DQS. In the similar manner, a data D 2 is latched at a second rising edge of DQS, and the data D 2 is aligned while a data D 3 is latched at a second falling edge of DQS. Accordingly, the fastest time point where data can be written in the sense amplifier is after 2*tCK from write. Therefore, in the write operation, all of the write command, the bank address and the column address have to be delayed as much as 2*tCK. A circuit for such delay is provided in the column address counter and latch 80 . In the prior art, such a delay circuit is driven even in the read operation. Thus, lots of power is consumed.

Accordingly, the present invention has been made in view of the above problems, and it is an object of the present invention to provide a semiconductor memory device in which the current consumed in a column address counter at the time of a read operation can be reduced.

To achieve the above object, according to the present invention, there is provided a semiconductor memory device including delay circuits for delaying a bank address and a column address in a write operation, comprising a controller for disabling the operation of the delay circuits in a read operation.

FIG. 1 is a functional block diagram illustrating the configuration of a DDR SDRAM in the prior art;

FIG. 2 a write timing diagram of FIG. 1 ;

FIG. 3 is a block diagram illustrating some of a column address counter and a latch according to an embodiment of the present invention;

FIG. 4 is a detailed circuit diagram of a delay unit shown in FIG. 3 ;

FIG. 5 is a timing diagram for explaining the operation of FIG. 3 ;

FIG. 6 is a block diagram of a column address counter and a latch according to another embodiment of the present invention; and

FIG. 7 is a circuit diagram for explaining another embodiment of the present invention.

Now, the preferred embodiments according to the present invention will be described with reference to the accompanying drawings.

FIG. 3 is a schematic block diagram of a column address counter and a latch according to an embodiment of the present invention.

In the read operation, a control signal casp6_rd is enabled, and a column address Y-add is thus provided to a counter 804 through a bypass unit 801 . A controller 802 generates a control signal according to a signal casp 6 , which is enabled in the write and read operations, and a signal WT6RD5Z, which is enabled in the write operation and disabled in the read operation. The column address Y-add can be provided to a delay unit 803 or block according to an output signal of the controller 802 . The delay unit 803 delays the received column address Y-add by 2*tCK and provides the delayed column address to the counter 804 .

That is, in the present embodiment, the delay unit 803 is not driven in the read operation but only in the write operation.

FIG. 4 is a detailed circuit diagram of the controller and the delay unit shown in FIG. 3 . The operation of each of the controller and the delay unit will now be described in detail with reference to FIG. 5 .

The controller 802 includes a NAND gate G 1 . The NAND gate G 1 receives a signal CASP6, which is enabled according to a write command WRITE or a read command READ shown in FIG. 5 , and a signal WT6RD5Z, which is enabled according to the write command and disabled according to the read command, as inputs. If these two signals CASP6 and WT6RD5Z are at a logic HIGH state, the output of the NAND gate G 1 becomes a logic LOW state. If the output of the NAND gate G 1 becomes a logic LOW state, the output of an inverter G 2 becomes a logic HIGH state, and a transfer gate T 1 is thus turned on. Accordingly, a received column address is provided to a latch L 1 through the transfer gate T 1 . Meanwhile, transfer gates T 2 to T 5 are turned according to a signal clkp 4 , which is enabled at the rising edge of a clock CLK and a signal inverted by an inverter G 3 . The column address through the transfer gate T 1 is output to an output terminal out via latches L 1 to L 5 and an inverter G 4 . That is, the delay unit 803 delays an input column address as much as 2*tck only in the write operation, but does not perform a shifting operation in the read operation. As a result, it is possible to reduce current consumption that much.

Generally, a memory device such as a DDR DRAM is composed of a plurality of column address counter and latches. At this time, the controller constructed above can be installed in each block.

FIG. 6 is a block diagram of column address counter and latches according to another embodiment of the present invention.

For instance, in the case of a 256 Mb DDR SDRAM, the number of column address counter and latches is 13. Therefore, in the read operation, a total of 13 delay units in each column address counter and latch unnecessarily operate. In order to solve this problem, in the embodiment of FIG. 4 , the controller is additionally installed every column address counter and latch. In the embodiment of FIG. 6 , however, one controller is used to control the 13 column address counter and latch blocks.

As shown in FIG. 6 , 13 column address counters and latches 901 to 913 are controlled according to outputs casp6_dly of a controller 914 . The controller 914 consists of a NAND gate G 5 and an inverter G 6 , and receives the signal CASP6, which is enabled according to the write command WRITE or the read command READ shown in FIG. 5 , and the signal WT6RD5Z, which is enabled according to the write command and disabled according to the read command, as inputs. If both the signals CASP6 and WT6RD5Z are at a logic HIGH state, the output of the NAND gate G 5 becomes a logic LOW state. If the output of the NAND gate G 5 becomes a logic LOW state, the output casp_dly of the inverter G 6 becomes a logic HIGH state. The output casp_dly of the inverter G 6 is provided to the column address counter and latches 901 to 903 . Accordingly, a shifting operation of a delay unit, which is included in each of the column address counter and latches 901 to 903 and delays the column address as much as 2*tck in the read operation is blocked. It is thus possible to reduce current consumption to that extent.

FIG. 7 is a circuit diagram for explaining another embodiment of the present invention.

In case of a DDR SDRAM, in the write operation, the bank address as well as the column address has to be delayed as much as 2*tck. However, in the same manner as the column address counter and latch block, if the shift operation of the delay unit for delaying the bank address in the read operation is blocked, current consumption can be saved.

A controller 915 is composed of a NAND gate G 7 , and receives the signal CASP 6 , which is enabled according to the write command WRITE or the read command READ shown in FIG. 5 , and the signal WT6RD5Z, which is enabled according to the write command and disabled according to the read command, as inputs. If both the signals CASP6 and WT6RD5Z are at a logic HIGH state, the output of the NAND gate G 7 becomes a logic LOW state. If the output of the NAND gate G 7 becomes a logic LOW state, the output of an inverter G 10 becomes a logic HIGH state, and a transfer gate T 6 is thus turned on. Meanwhile, transfer gates T 7 to T 10 are turned on according to the signal clkp4, which is enabled at the rising edge of the clock CLK and a signal clkpl4z inverted by an inverter G 8 . Thus, a latched bank address eat_bk is delayed through the transfer gates T 6 to T 10 and latches L 6 to L 10 and outputs to an output terminal out via an inverter G 11 . That is, a delay unit 1000 delays an inputted bank address as much as 2*tck only in the write operation, but does not perform a shift operation in the read operation. Accordingly, current consumption can be saved.

A 256 Mb DDR SDRAM needs four circuits as shown in FIG. 7 since it is 4 banks. Accordingly, if the shift operation of these circuits is blocked in the read operation, current consumption can be saved to that extent.

As described above, according to the present invention, unnecessary current consumed in the read operation can be reduced. Therefore, the present invention is advantageous in a low-power operation of a DDR SDRAM.

Although the foregoing description has been made with reference to embodiments, it is to be understood that changes and modifications of the present invention may be made by the ordinary skilled in the art without departing from the spirit and scope of the present invention and appended claims.