Switching circuit using closed control loop to precharge gate of switching transistor and stable open loop to switch the switching transistor

1. The Field of the Invention

The present invention relates generally to switching circuits. More specifically, the present invention relates to switching circuits that have controlled switching of the switching transistor for reduced Electro-Magnetic Interference (EMI), and that precharge the switching transistor for reduced switching delay.

2. Background and Relevant Art

Electronic circuitry has contributed enormously to the advancement of civilization. One of the fundamental building blocks of electronic circuitry is the switching circuit, in which a node of the circuitry is switched from one voltage to another in response to a switch control signal.

Designers of switching circuits take various constraints into account when conceiving such circuits. One of these constraints is the electromagnetic compatibility (or EMC) of the silicon chip they are designing. While operating, the chip should not radiate excessive electromagnetic energy in order not to interfere with the proper operation of other surrounding circuits. Such interference is often termed Electro-Magnetic Interference (EMI).

Electro-Magnetic energy will radiate to some extent every time a time-dependent voltage signal is present on chip. In general, the faster that voltage signal varies, the more electro-magnetic energy is radiated. Since switching circuits by their very nature involve the transition of a voltage signal from one voltage to another, switching circuits also involve rapid changes in current to sustain the voltage signal transition at a particular node. These rapid changes in current cause the switching circuits to radiate EMI. EMI may be of particular concern in Pulse Width Modulation (PWM) drivers, which often generate sharp transition edges.

One conventional solution to limit EMI is to limit the slope of the transition edge when switching the switching circuit. An example of such a conventional switching circuit is illustrated in FIG. 7 as switching circuit 700 . The slope of the transition edge is controlled by the current sources IQ 1 and IQ 2 and the capacitor C 1 . Accordingly, this switching circuit emits less EMI than switching circuits that do not implement slope control.

However, a main disadvantage of that switching circuit is that it has a very long delay between the command to perform a switch to the actual start of the switch. The turn-on delay is caused by the necessity for the gate to source voltage of switch transistor M 1 to reach the threshold voltage of the switch transistor M 1 before the switch transistor M 1 starts conducting. The turn-off delay is caused by the necessity for the gate to source voltage of switch transistor M 1 to drop before exiting the linear region. FIG. 8 illustrates a timing signal diagram 800 of the transition control signal VON and the switch voltage VDS across the switch transistor M 1 . Note the turn on delay t 1 and the turn off delay t 2 .

Some conventional switching circuits reduce switching delay by pre-charging the gate terminal of the switch transistor prior to an off-on transition, and pre-discharging the gate terminal of the switch transistor prior to the on-off transition. However, the gate terminal should not be pre-charged to a point where the switch transistor conducts significant current. Likewise, the gate terminal should not be pre-discharged to a point where the switch transistor reduces significantly the amount of current conducted. Otherwise, the output voltage would be altered despite not being in a transition. To avoid this, a significant safety factor is built into the pre-charge and pre-discharge. This safety factor may be quite large due to the variability in transistor performance. This large safety factor often prevents much of any possible pre-charge or pre-discharge. Accordingly, such conventional circuits may still have significant switching delay.

Furthermore, this and other conventional circuits may use a closed loop to pre-charge and pre-discharge. Closed loops can be quite unstable if not designed properly. Accordingly, significant time is often expended in designing such closed loop pre-charge switching circuits.

What would thereby be advantageous are switching circuits that have slope control during transitions to reduce EMI, that perform pre-charging to reduce switching delay, and that do not need significant design and/or testing to ensure stability during operation.

The foregoing problems with the prior state of the art are overcome by the principles of the present invention, which relate to a switching circuit that transitions using a switch transistor. Prior to a high-low transition, a control loop pre-charges the gate of the switch transistor to reduce high-low switching delays. Once the current flowing through the switch transistor reaches a value for which the rate of decline in output voltage (dV/dt) lowers to a specified threshold, a loop opening mechanism opens the control loop. Further opening (in the case of an n-type pull down switch transistor) or closing (in the case of a p-type pull up switch transistor) of the switch transistor in the high-low transition is taken care of by a relatively constant current source. At that point, no or negligible feedback current is used to charge the gate of the switch transistor.

Prior to the low-high transition, the control loop pre-discharges the gate of the switch transistor to reduce low-high switching delays. Once the current flowing through the switch transistor reaches a value for which the rate of increase of the output voltage dV/dt rises to a specified threshold, the loop once again opens. Further closing (in the case of an n-type pull down switch transistor) or opening (in the case of a p-type pull up switch transistor) of the switch transistor in the low-high transition is also taken care of by a constant current source, with no more than negligible current being drawn through the control loop.

The switch transistor is opened and closed at controlled speeds, resulting in reduced Electro-Magnetic Interference (EMI). Furthermore, the gate of the switch transistor is pre-charged prior to a high-low transition, and is pre-discharged prior to a low-high transition. This reduces switching delays that occur between the time a switch signal is provided to the time that the switching is actually initiated. Furthermore, even though a closed control loop is used to pre-charge and pre-discharge, the control loop is opened in order to perform the actual switching operation. Since the switching occurs in open loop, stability is achieved without having to rely on a well-designed stable closed loop for such switching.

Additional features and advantages of the invention will be set forth in the description that follows, and in part will be obvious from the description, or may be learned by the practice of the invention. The features and advantages of the invention may be realized and obtained by means of the instruments and combinations particularly pointed out in the appended claims. These and other features of the present invention will become more fully apparent from the following description and appended claims, or may be learned by the practice of the invention as set forth hereinafter.

In order to describe the manner in which the above-recited and other advantages and features of the invention can be obtained, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. Understanding that these drawings depict only typical embodiments of the invention and are not therefore to be considered to be limiting of its scope, the invention will be described and explained with additional specificity and detail through the use of the accompanying drawings in which:

FIG. 1A is a schematic diagram of a switching circuit having an n-type field effect switch transistor in accordance with one embodiment of the present invention;

FIG. 1B is a schematic diagram of a switching circuit having a p-type field effect switch transistor in accordance with a second embodiment of the present invention;

FIG. 2 illustrates the control loop component of FIGS. 1A and 1B in further detail including a first stage and a second stage;

FIG. 3A illustrates a first embodiment of the first stage of FIG. 2 in which the transistors are n-type field effect transistors;

FIG. 3B illustrates a second embodiment of the first stage of FIG. 2 in which the transistors are p-type field effect transistors;

FIG. 3C illustrates a third embodiment of the first stage of FIG. 2 in which the transistors are NPN bi-polar transistors;

FIG. 3D illustrates a fourth embodiment of the first stage of FIG. 2 in which the transistors are PNP bi-polar transistors;

FIG. 4A illustrates a first embodiment of the second stage of FIG. 2 in which the transistors are field-effect transistors;

FIG. 4B illustrates a second embodiment of the second stage of FIG. 2 in which the transistors are bi-polar transistors;

FIG. 5 illustrates a complete circuit diagram of an embodiment of the switching circuit of FIG. 1A using the first stage of FIG. 3A , and the second stage of FIG. 4A ;

FIG. 6 illustrates an alternative embodiment of a control loop component suitable as the control loop component of FIGS. 1A and 1B ;

FIG. 7 is a circuit diagram of a conventional switching circuit; and

FIG. 8 is a signal timing diagram associated with the conventional switching circuit of FIG. 7 .

The principles of the present invention relate to a switching circuit that transitions using a controlled voltage slope at the drain terminal of the switch transistor to thereby reduce Electro-Magnetic Interference (EMI). In addition, a closed control loop pre-charges and pre-discharges the gate voltage of the switch transistor to thereby reduce switching delay. Furthermore, unlike conventional switching circuits, the closed control loop is configured to open during the actual switching of the switch transistor. Accordingly, the switching circuit is stable during the actual switching operation, which is the operation of greatest susceptibility to instability. Therefore, the closed control loop need not be stable and thus is more easily designed and tested.

FIG. 1A is a schematic diagram of a switching circuit 100 A having an n-type switch field effect transistor 131 A in accordance with one embodiment of the present invention. The n-type switch field effect transistor 131 A has a source terminal electrically connected to a first circuit node 135 A that is configured to draw current when the n-type switch field effect transistor 131 A is conducting. The drain terminal of the n-type switch field effect transistor 131 A is electrically connected to the output terminal 141 A of the switching circuit 100 A shown as carrying voltage V OUT . A resistor 134 A having resistance R LOAD is shown between the output terminal 141 A and a circuit node 136 A that provides current. This resistance may be, but need not be, a load resistance.

When the output voltage V OUT is to transition from high to low, a control signal S 1 transitions high, and a complementary control signal S 2 transitions low. Accordingly, the switch 111 A is closed and the switch 121 A is opened permitting a substantially constant current I 1 to be provided by the current source 112 A to the gate terminal of the n-type switch field effect transistor 131 A. This closes the switch field effect transistor 131 A to thereby draw current from the circuit node 136 A, through resistor 134 A, and through switch field effect transistor 131 A. As the resistance through the channel region of the switch transistor 131 A decreases, the output voltage V OUT accordingly lowers.

Conversely, when the output voltage V OUT is to transition from low to high, the control signal S 2 transitions high, and a complementary control signal S 1 transitions low. Accordingly, the switch 121 A is closed and the switch 111 A is opened permitting a substantially constant current I 2 to be drawn by the current sink 122 A from the gate terminal of the n-type switch field effect transistor 131 A. This increases the resistance of (and ultimately opens) the switch field effect transistor 131 A to thereby increase the output voltage VOUT to a high value.

In this configuration, there is an implicit capacitance looking into the gate terminal of the n-type switch field effect transistor 131 A. This capacitance means that it takes some time for the current source 112 A to fully turn the switch transistor 131 A on, and that it takes some time for the current source 122 A to fully turn the switch transistor 131 A off. In order to increase this transition time, the capacitance may be increased by capacitor 133 A, which capacitively couples the drain and gate terminals of the n-type switch field effect transistor 131 A. This controlled rate of transition reduces the amount of EMI emitted by the switching circuit 100 A.

For example, immediately before a low to high transition, the gate voltage of switch transistor 131 A is high, and the output voltage at the drain terminal of switch transistor 131 A is low. As mentioned above, a low to high transition is initiated when switch 121 A closes, and switch 111 A opens. From this time, the current I 2 discharges the combination of the gate terminal capacitance of the switch transistor 131 A (based on its gate to source capacitance) as well as the capacitor 133 A. The split of these two discharging currents is based on capacitor ratio of these two capacitors.

When the gate voltage of switch transistor 131 A reaches a voltage for which the drain current through switch transistor 131 A starts to be smaller than approximately V DD /R LOAD , the output voltage Vout starts to increase. As the switch transistor 131 A is in saturation at this moment, very small variations of gate voltage cause large variation in the drain current. In this state, the gate voltage of switch transistor 131 A may be considered to be constant through the rest of the transition. As the change in voltage across the gate to source capacitance of switch transistor 131 A is relatively small, substantially all of the discharging current I 2 flows through 133 A. Because the gate voltage of switch transistor 131 A has a relatively constant voltage, and since the current I 2 flowing through capacitor 133 A is relatively constant, a voltage slope of dV OUT /dt=I 2 /C (where C is the capacitance of capacitor 133 A) is seen on the output voltage Vout. This is of course true if the loop composed of switch transistor 131 A and capacitor 133 A has sufficient gain (or in other words, if the gate voltage of switch transistor 131 A varies only a little during the transition).

A control loop component 132 A performs different functions depending on whether the switching circuit is transitioning to a low state (with V OUT being low), or transitioning to a high state (with V OUT being high). In particular, when the output voltage V OUT is in the initial stages of a high-to-low transition, the control loop component 132 A partially or fully pre-charges the gate terminal of the n-type switch field effect transistor 131 A through the output terminal 142 A of the control loop component 132 A using a closed control loop. This pre-charging supplements the relatively constant charge current I 1 to accelerate the pre-charging process. Once the rate of decline of the output voltage dV OUT /dt increases to above a certain value, the control loop component 132 opens, leaving much of the rest of the transition to occur in open loop with a relatively constant current I 1 driving the transition. As a secondary effect, towards the end of the transition, the rate of decline dV OUT /dt will once again decline below the threshold value, thereby closing the control loop component 132 A. This has the effect of accelerating the end of the transition, which is not susceptible to instabilities in the control loop.

Conversely, when the output voltage V OUT is in the initial stages of a low-to high transition, the control loop component 132 A partially or fully pre-discharges the gate terminal of the n-type switch field effect transistor 131 A by drawing current through the terminal 142 A of the control loop component 132 A using a closed control loop. This pre-discharging supplements the relatively constant discharge current I 2 to accelerate the pre-charging process. Once the rate of increase of the output voltage dV OUT /dt increases to above a certain value, the control loop component 132 opens, leaving the rest of the transition to occur in open loop with a relatively constant current I 2 driving the transition. As a secondary effect, towards the end of the transition, the rate of increase dV OUT /dt will once again decline below the threshold value, thereby closing the control loop component 132 A. Once again, this has the effect of accelerating the end of the transition, which is not susceptible to instabilities in the control loop.

This pre-charging and pre-discharging of the n-type field effect transistor 131 A significantly reduces switching delay. Switching delay is the amount of time between the time that the control signal for the transition is received by the switching circuit (i.e., when the switches 111 A and 121 A change state) until the time the transition of the output voltage V OUT actually begins. During non-transitioning moments, the switching circuit is not vulnerable to any instability of the closed loop in the control loop component 132 A. This is because control loop component 132 A allows either only positive or negative output currents, and also because the switch transistor 131 A operates in either the linear or “on” mode, or the deep subthreshold or “off” mode, and thus has no gain.

FIG. 1B illustrates a switching circuit 100 B, which is similar to the switching circuit 100 A described with reference to FIG. 1A . However, in FIG. 1B , the n-type switch field effect transistor 131 A is replaced by a p-type field effect transistor 131 B. Circuit components 111 B, 112 B, 121 B, 122 B, 131 B, 132 B, 133 B, 134 B, 135 B and 136 B, 141 B and 142 B of FIG. 1B may be similar to circuit components 111 A, 112 A, 121 A, 122 A, 131 A, 132 A, 133 A, 134 A, 135 A and 136 A, 141 A and 142 A of FIG. 1A . In the case of FIG. 1B , however, circuit node 135 B is configured to provide current, whereas circuit node 136 B is configured to draw current. A high to low transition is accomplished by turning off the p-type switch field effect transistor 131 B. Conversely, a low to high transition is accomplished by turning on the p-type switch field effect transistor.

While any configuration for the control loop component that at least partially opens during the transition will suffice, FIG. 2 schematically illustrates an embodiment 200 of the control loop component 132 A of FIG. 1A , or of the control loop component 132 B of FIG. 1B in further detail.

The control loop component 200 includes a first stage 210 having an input terminal 141 electrically connected to the drain terminal of the switch field effect transistor. The first stage 210 is configured to change a first stage output voltage applied to the output terminal 211 of the first stage depending on the rate of change of the first stage input voltage on the input terminal 141 of the first stage 210 . The first stage output voltage is a function of the rate of change of the input voltage (i.e., dV OUT /dt) such that if the rate of change increases above a certain rate, the first stage output voltage decreases below a first reference voltage (referred to below as V REFN ), and such that if the rate of change decreases below a certain rate, the first stage output voltage increases above a second reference voltage (referred to below as V REFP ).

The control loop component 200 also includes a second stage 220 that has an input terminal 211 electrically connected to the output terminal of the first stage 210 , and an output terminal 142 that is electrically coupled to the gate terminal of the switch field effect transistor 131 .

If the first stage output voltage applied to the input terminal 211 of the second stage 220 is below the second reference voltage V REFP and the transition of the output voltage V OUT is from high-to-low, a current is provided through the output terminal 142 of the second stage to the gate terminal of the switch field effect transistor 131 A or 131 B to thereby facilitate pre-charge. If the first stage output voltage applied to the input terminal 211 of the second stage 220 is above the first reference voltage V REFN and the transition of the output voltage V OUT is from low-to-high, a current is drawn from the gate terminal of the switch field effect transistor 131 A through the output terminal 142 of the second stage 220 to thereby facilitate pre-discharge. This configuration supports the pre-charging and pre-discharging operation of the control loop component 200 .

If the first stage output voltage is below the first reference voltage V REFN and the switching circuit is transitioning from low to high, or if the first stage output voltage is above the second reference voltage V REFP and the switching circuit is transitioning from high to low, the output terminal of the first stage is substantially electrically disconnected from the gate terminal of the switch field effect transistor.

FIGS. 3A shows an example first stage circuit embodiment 300 A of the first stage 210 of FIG. 2 . Just as the first stage 210 of FIG. 2 , the first stage circuit 300 A receives a voltage signal from input terminal 141 and provides a resulting voltage signal on the output terminal 211 . The first stage circuit 300 A includes a capacitor 301 A that capacitively couples the input terminal 141 to gate terminals of two n-type field effect transistors 302 A and 304 A and to the drain terminal of the n-type field effect transistor 302 A. The source terminal of the n-type field effect transistor 302 A is electrically connected to a circuit node 306 A (such as ground) that is configured to draw current when the n-type field effect transistor 302 A is conducting. A current source 303 A provides a substantially constant current I 3 from the circuit node 308 A (e.g., V DD ) to the drain terminal of the n-type field effect transistor 302 A. The n-type field effect transistor 304 A has a drain terminal electrically connected to the output terminal 211 of the first stage, and a source terminal electrically connected to a circuit node 307 A (such as ground) that is configured to draw current when the n-type field effect transistor 304 A is conducting. A resistor 305 A resistively couples the output terminal 211 to another circuit node 309 A that is configured to provide current through the resistor 305 A. The node 309 A is connected to a voltage source V DD to which the voltage references V REFP and V REFN (described hereinafter) are referred for reasons that will be described hereinafter. The operation of FIG. 3A will be described with respect to FIG. 5 . FIGS. 3B through 3D are alternative embodiments for the first stage 210 and will be described subsequent to the descriptions of FIGS. 5 and 6 .

FIG. 4A illustrates a second stage circuit 400 A that represents an embodiment of the second stage 220 of FIG. 2 . Just as the second stage 220 of FIG. 2 , the second stage circuit 400 A receives a voltage signal from input terminal 211 and provides a resulting current on the output terminal 142 .

The second stage circuit 400 A includes a transconductance amplifier 401 A having a negative input terminal configured to receive a reference voltage V REFP , and a positive input terminal electrically connected to the input terminal 211 . The output terminal of the transconductance amplifier 401 A is electrically connected to the gate terminals of the p-type field effect transistors 402 A and 403 A and to the drain terminal of p-type field effect transistor 402 A. The source terminals of the p-type field effect transistors 402 A and 403 A are electrically connected to a circuit node (e.g., V DD ) that is configured to provide current through the p-type field effect transistors 402 A and 403 A when conducting. The drain terminal of the p-type field effect transistor 403 A is selectively connected to the output terminal 142 via a switch 405 A that is controlled by a signal S 1 B that is controlled together with signal S 1

The second stage circuit 400 A also includes a transconductance amplifier 411 A having a negative input terminal configured to receive a reference voltage V REFN , and a positive input terminal electrically connected to the input terminal 211 . The output terminal of the transconductance amplifier 411 A is electrically connected to the gate terminals of the n-type field effect transistors 412 A and 413 A and to the drain terminal of n-type field effect transistor 412 A. The source terminals of the n-type field effect transistors 412 A and 413 A are electrically connected to a circuit node (e.g., ground) that is configured to draw current through the n-type field effect transistors 412 A and 413 A when conducting. The drain terminal of the n-type field effect transistor 413 A is selectively connected to the output terminal 142 via a switch 415 A that is controlled by a signal S 2 B that is controlled together with signal S 2 . FIG. 4B illustrates an alternative embodiment for the second stage 220 and will be explained in further detail after the description of FIGS. 5 and 6 .

FIG. 5 illustrates a first particular embodiment of a switching circuit 500 in accordance with the principles of the present invention. The switching circuit 500 is the same as the switching circuit 100 A of FIG. 1A , with the control loop component 132 A being structured as shown in FIG. 2 , and with the first stage of the control loop being as illustrated in FIG. 3A , and with the second stage of the control loop being as illustrated in FIG. 4A . The operation of the switching circuit 500 will now be described.

A driver circuit for slope limited pulse switching of the load 134 A comprises a transistor switch 131 A. The capacitor 133 A is connected between the drain and the gate terminals of transistor 131 A. The gate terminal of transistor 131 A is connected to the two current sources 112 A and 122 A respectively activated by the switches 111 A (controlled by signal S 1 ) and 121 A (controlled by signal S 2 ). Signals S 1 and S 2 are complementary signals such that when switch 111 A is open, the switch 121 A is closed, and vice versa. The capacitor 301 A is used to sense the slope dV OUT /dt.

The current I S flowing through the sense capacitor 301 A is given by the following Equation (1): I S =pC S (V D2 −V OUT ), where “V D2 ” is the voltage at the drain of transistor 302 A, “C S ” is the capacitance of sense capacitor 301 A, and “p” is the Laplace variable.

In a first approximation, Equation (1) may be rewritten as Equation (2) as follows: I S =−pC S V OUT . In this case, the sense current I S is approximately proportional to the slope dV OUT /dt, where I S will be positive for falling edges (dV OUT /dt being negative) and negative for rising edges (dV OUT /dt being greater than zero). This approximation is justified by the fact that the interval of variation for V OUT is greater than the interval of variation of V D2 , and by the fact that V D2 does not vary faster than V OUT . Equation (2) is a good approximation of Equation (1) since the impedance of the drain of transistor 302 A (which is approximately equal to the transconductance “gm” of the transistor 302 A) is much smaller than the impedance of the output voltage (which is approximately equal to the resistance of resistor 305 A).

During the initial stage of a high-to-low transition when switches 111 A and 405 A are initially closed, and switches 121 A and 415 A are initially opened, the gate terminal of the switching transistor 131 A is pre-charged using a closed loop. In this state, the current I 1 starts to charge up the gate of the transistor 131 A. As long as the gate voltage required for conduction is not reached, the switch transistor 131 A remains closed in this initial stage of the high-low transition. Thus, V OUT does not vary and the sense current I S is zero.

The current magnitude 13 , the transistors 302 A and 304 A, and the resistor 305 A are dimensioned so that if the magnitude of the sense current I S is smaller than a given threshold, the voltage at terminal 211 will be smaller than V REFP . This balance is important to properly open and close the control loop at the appropriate times, and so the voltage reference V REFP is tied to the voltage V DD , such that variations in the supply voltage VDD will not adversely affect this balance. These same elements are also sized so that in that case, the output of transconductance amplifier 401 A is sufficiently low to have current flowing through the transistor 402 A. The current through transistor 402 A is mirrored by transistor 403 A. The mirrored current (referred to herein as I 9 ) passes through closed switch 405 A, and is added to current I 1 at the gate terminal of switch transistor 131 A.

The gate voltage of switch transistor 131 A now increases at a rate (I 1 +I 9 )/C instead of I 1 /C, where C is the capacitance seen at the gate of transistor 131 A. The current I 9 may be designed to be large compared to current I 1 so that the switch transistor 131 A quickly pre-charges. As soon as switch transistor 131 A starts conducting, V OUT will vary, and thus sense current I S will be non-zero. The current through transistor 302 A is now I 3 minus I S instead of I 3 . That current is mirrored by the transistor 304 A. Variations of the drain current of transistor 304 A are converted into voltage variations at terminal 211 using resistor 305 A. As the voltage at terminal 211 increases, the output of the transconductance amplifier 401 A increases. Consequently, the gate to source voltage of transistor 402 A decreases and the current sourced by transistor 403 A decreases. The system is designed so that the transconductance amplifier 401 A rapidly saturates (i.e. its output is limited by the supply voltage of the amplifier). Transconductance amplifier 401 A saturates in the moment when the voltage at node 211 becomes greater than V REFP .

When the transconductance amplifier 401 A saturates, no current flows through transistors 402 A and 403 A. The switch 405 A is still closed, but transistor 403 A is now open. Therefore, the control loop is likewise open. Once the control loop is open, the slope of V OUT is determined by I 1 alone without using the control loops. Thus there are no stability issues during the high to low transition.

A similar reasoning can be done for a low to high transition. In the initial stages of a low-to-high transition, the gate terminal of the switching transistor 131 A is pre-discharged using a closed loop. In the low state, the switches 121 A and 415 A are closed, whereas switches 111 A and 405 A are open. In this state, the current I 2 starts to discharge the gate of the transistor 131 A. As long as the transistor 131 A remains closed, V OUT remains low and does not vary, and thus the sense current I S is zero.

As previously mentioned, the current magnitude I 3 , the transistors 302 A and 304 A, and the resistor 305 A are dimensioned so that if the magnitude of the sense current I S is less negative than a given threshold, the voltage at terminal 211 will be larger than V REFN . This balance is important to properly open and close the control loop at the appropriate times, and so the voltage reference V REFN is also tied to the voltage V DD , such that variations in the supply voltage VDD will not adversely affect this balance. These same elements are also sized so that in that case, the output of transconductance amplifier 411 A is sufficiently high to have current flowing through the transistor 412 A. The current through transistor 412 A is mirrored by transistor 413 A. The mirrored current (referred to herein as I 10 ) is drawn through closed switch 415 A, and is added to the current I 2 drawn from the gate terminal of switch transistor 131 A.

The gate voltage of switch transistor 131 A now decreases at a rate (I 2 +I 10 )/C instead of I 2 /C. Once again, the current I 10 may be designed to be large compared to current I 2 so that the switch transistor 131 A quickly pre-discharges. As soon as switch transistor 131 A increases resistance, V OUT will vary, and thus sense current I S will be non-zero. The current through transistor 302 A is now I 3 minus I S (where I S is negative) instead of I 3 . That current is mirrored by the transistor 304 A. Variations of the drain current of transistor 304 A are converted into voltage variations at terminal 211 using resistor 305 A. As the voltage at terminal 211 decreases, the output of the transconductance amplifier 411 A decreases. Since the transconductance amplifier has an output lout equal to its transconductance gm times the differential input voltage Vin, the transconductance amplifier saturates. Consequently, the gate to source voltage of transistor 412 A decreases and the current drained by transistor 413 A decreases. The system is designed so that the transconductance amplifier 411 A rapidly saturates at the point where the voltage at node 211 becomes less than V REFN .

When the transconductance amplifier 411 A saturates, no current flows through transistors 412 A and 413 A. The switch 415 A is still closed, but transistor 413 A is now open. Therefore, the control loop is likewise open. Once the control loop is open, the slope of V OUT is determined by I 2 alone without using the control loops. Thus there are no stability issues during the low to high transition.

The switching circuit 500 provides a driver (such as, but not limited to, a PWM driver) with reduced turn on and turn off delays. The circuit 500 may be used in a wide variety of operating conditions (i.e. specified R L and dV OUT /dt) without requiring extensive stability analysis. The circuit 500 more quickly brings the switch transistor to the verge of conduction regardless of the process tolerances by operating in closed loop. Once the switch is starting to conduct, the regulation loop opens and the gate is charged in open loop without the risk that a closed loop would become unstable as in the prior art.

Having described the general principles of the present invention with respect to a specific circuit embodiment, those of ordinary skill in the art will recognize various modification and variations that be apparent from this description. For instance, FIGS. 3B through 3D represent alternative embodiments of the first stage circuit, in which the polarity of the circuit is reversed, and in which the possibility of using bipolar transistors is shown. The elements of FIGS. 3B through 3D have a similar function as described for the corresponding elements of FIG. 3A . Likewise, FIG. 4B shows that bi-polar transistors may be used in the second stage of the control loop as well.

More specifically, FIG. 3B shows a first stage circuit embodiment 300 B of the first stage 210 of FIG. 2 . The first stage circuit 300 B includes a capacitor 301 B that capacitively couples the input terminal 141 to gate terminals of two p-type field effect transistors 302 B and 304 B and to the drain terminal of the p-type field effect transistor 302 B. The source terminal of the p-type field effect transistor 302 B is electrically connected to a circuit node 306 B (such as V DD ) that is configured to provide current when the p-type field effect transistor 302 B is conducting. A current source 303 B draws a substantially constant current I 3 to the circuit node 308 B (e.g., ground) from the drain terminal of the p-type field effect transistor 302 B. The p-type field effect transistor 304 B has a drain terminal electrically connected to the output terminal 211 of the first stage, and a source terminal electrically connected to a circuit node 307 B (such as V DD ) that is configured to provide current when the p-type field effect transistor 304 B is conducting. A resistor 305 B resistively couples the output terminal 211 to another circuit node 309 B that is configured to draw current through the resistor 305 B.

FIG. 3C shows yet another example first stage circuit embodiment 300 C of the first stage 210 of FIG. 2 . The first stage circuit 300 C includes a capacitor 301 C that capacitively couples the input terminal 141 to base terminals of two NPN bipolar transistors 302 C and 304 C and to the collector terminal of the NPN bipolar transistor 302 C. The emitter terminal of the NPN bipolar transistor 302 C is electrically connected to a circuit node 306 C (such as ground) that is configured to draw current when the NPN bipolar transistor 302 C is conducting. A current source 303 C provides a substantially constant current I 3 from the circuit node 308 C (e.g., V DD ) to the collector terminal of the NPN bipolar transistor 302 C. The NPN bipolar transistor 304 C has a collector terminal electrically connected to the output terminal 211 of the first stage, and an emitter terminal electrically connected to a circuit node 307 C (such as ground) that is configured to draw current when the NPN bipolar transistor 304 C is conducting. A resistor 305 C resistively couples the output terminal 211 to another circuit node 309 C that is configured to provide current through the resistor 305 C.

FIG. 3D shows a final example first stage circuit embodiment 300 D of the first stage 210 of FIG. 2 . The first stage circuit 300 D includes a capacitor 301 D that capacitively couples the input terminal 141 to base terminals of two PNP bipolar transistors 302 D and 304 D and to the collector terminal of the PNP bipolar transistor 302 D. The emitter terminal of the PNP bipolar transistor 302 D is electrically connected to a circuit node 306 D (such as V DD ) that is configured to provide current when the PNP bipolar transistor 302 D is conducting. A current source 303 D draws a substantially constant current I 3 to the circuit node 308 D (e.g., ground) from the collector terminal of the PNP bipolar transistor 302 D. The PNP bipolar transistor 304 D has a collector terminal electrically connected to the output terminal 211 of the first stage, and an emitter terminal electrically connected to a circuit node 307 D (such as VDD) that is configured to provide current when the PNP bipolar transistor 304 D is conducting. A resistor 305 D resistively couples the output terminal 211 and another circuit node 309 D that is configured to draw current through the resistor 305 D.

FIG. 4B illustrates an alternative second stage embodiment 400 B of the second stage 220 of FIG. 2 . The second stage 400 B is structured similar to the second stage 400 A described with respect to FIG. 4A , except that PNP bipolar transistors replace p-type bi-polar transistors, and in which NPN bipolar transistors replace n-type bi-polar transistors.

More specifically, the second stage 400 B includes a first transconductance amplifier 401 B having a negative input terminal configured to receive the reference voltage V REFP , and a positive input terminal electrically connected to the input terminal 211 . A PNP bi-polar transistor 402 B has base and collector terminals electrically connected to the output terminal of the first transconductance amplifier 401 B, and an emitter terminal electrically connected to circuit node 404 B (such as V DD ) that is configured to provide current through the PNP bi-polar transistor 402 B. A second PNP bi-polar transistor 403 B has a base terminal electrically connected to the output terminal of the first transconductance amplifier 401 B, an emitter terminal electrically connected to the circuit node 404 B, and a collector terminal selectively electrically connected to the output terminal 142 of the second stage through switch 405 B controlled by signal S 1 B.

A second transconductance amplifier 411 B has a negative input terminal configured to receive the reference voltage V REFN , and a positive input terminal electrically connected to the input terminal 211 . An NPN bi-polar transistor 412 B has base and collector terminals electrically connected to an output terminal of the second transconductance amplifier 411 B, and an emitter terminal electrically connected to a circuit node 414 B (such as ground) that is configured to drawn current through the NPN bi-polar transistor 412 B. A second NPN bi-polar transistor 413 B has a base terminal electrically connected to the output terminal of the second transconductance amplifier 411 B, an emitter terminal electrically connected to the circuit node 414 B, and a collector terminal selectively electrically connected to the output terminal 142 of the second stage through switch 415 B controlled by signal S 2 B.

FIG. 6 illustrates a second particular embodiment 600 of a control loop component 132 A of FIG. 1A or 132 B of FIG. 1B . During the high-to-low transition, when the rate of decline dV OUT /dt of the output voltage starts to accelerate, the current I S increases in the positive direction. This causes the current passing through transistor 302 A to decrease from I 3 by increasing amounts. This decreasing current is passed through transistor 604 sized with ratio N with respect to the transistor 302 A. More importantly for high-to-low transitions, however, the decreasing current is passed through transistor 603 sized with ratio N with respect to transistor 302 A. Before the current passing through transistor 603 (equal to N times (I 3 −I S )) drops below the current I refp provided by current source 601 , there is a current drawn from the gate terminals of p-type transistor 402 A, causing transistor 402 A to conduct. That current is mirrored by mirror ratio M (where M may be much larger than 1) to provide a supplemental pre-charge current through switch 405 A, to the terminal 142 and to the gate of the switch transistor. However, once the current passing through transistor 603 drops below the current I refp provided by current source 601 (due to a more rapid decline in the output voltage), there is a current provided to the gate terminal of p-type transistor 402 A, causing transistor 402 A to turn off. That opens the control loop for much of the remainder of the transition, until the rate of decline dV OUT /dt once again drops below the threshold.

During the low-to-high transition, when the rate of increase dV OUT /dt of the output voltage starts to accelerate, the current I S increases in the negative direction. This causes the current passing through transistor 302 A to increase from I 3 by increasing amounts. This increasing current is passed through transistor 604 sized with ratio N with respect to the transistor 302 A. Before the current passing through transistor 604 (equal to N times (I 3 −I S ) (where I S is negative)) increases above the current I refn provided by current source 602 , there is a current provided from the gate terminals of n-type transistor 412 A, causing transistor 412 A to conduct. That current is mirrored by mirror ratio M (where M may be much larger than 1) to provide a supplemental pre-discharge current through switch 415 A, to the terminal 142 and to the gate of the switch transistor. However, once the current passing through transistor 604 increase to be above the current I refn provided by current source 602 (due to a more rapid increase in the output voltage), there is a current drawn from the gate terminal of n-type transistor 412 A, causing transistor 412 A to turn off. That opens the control loop for much of the remainder of the transition, until the rate of increase dV OUT /dt once again drops below the threshold.

The present invention may be embodied in other specific forms without departing from its spirit or essential characteristics. The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the invention is, therefore, indicated by the appended claims rather than by the foregoing description. All changes, which come within the meaning and range of equivalency of the claims, are to be embraced within their scope.