Current-mode instrumentation amplifier

This application claims the benefit of provisional patent application No. 60/580,295 to Botker et al., filed Jun. 15, 2004.

1. Field of the Invention

This invention relates to the field of amplifiers, and particularly to current-mode instrumentation amplifiers.

2. Description of the Related Art

An instrumentation amplifier (IA) is a type of amplifier that has been specifically designed to have characteristics suitable for use in measurement and test equipment, such as low DC offset, high common mode rejection (CMR), and high input impedance. Such an amplifier is typically used when a user needs to look at a differential signal in the presence of a common mode signal, which can often be larger than the differential signal of interest.

A well-known IA is shown in FIG. 1 . This topology, which employs three operational amplifiers, is commonly used with bipolar and JFET processes to provide an IA with good DC precision. However, this topology has several limitations. For example, the design requires at least six resistors, which generally must be trimmed to achieve the matching required to meet precision specifications such as CMR and gain error. Also, each of the three amplifiers is usually trimmed to ensure good overall DC specifications. Both of these requirements limit the minimum die size of this topology.

The input common-mode voltage and the overall gain of the IA of FIG. 1 limit the range of valid output voltages. The resultant limitation on output swing becomes especially problematic with low supply voltages. Also, when operated from a single supply, the IA's reference pin (V ref ) must be driven by a low impedance source to maintain good CMR. This is typically done with an additional external amplifier 10 which drives the reference pin to a voltage within the valid output swing of the IA. This external amp adds to the total board space needed for the IA, as well as its total solution cost.

One approach that overcomes some of these limitations is exemplified by the INA326 IA from Texas Instruments. Here, current-mode signal processing is used to provide rejection of common-mode input voltage and power supply variation without the need for accurately matched resistors. However, this design employs four current mirrors, each of which contributes an output-referred voltage error due to device mismatch within each of the mirrors.

A current-mode instrumentation amplifier is presented which overcomes the problems noted above, providing high DC precision with a small die area.

The present IA employs a current-mode topology. The IA includes first and second input terminals (VINP, VINN) which receive a differential voltage V in =VINP−VINN, a resistor having a resistance R 1 , and first and second buffer amplifiers which receive the differential voltage and provide first and second output voltages V 1 and V 2 at respective output nodes which vary with VINP and VINN, respectively. With reference to FIG. 2 , the first amplifier includes a first transistor (MN 1 ) biased with a bias current I bias1 =I 3 −I 1 and connected between V 1 and a circuit common point, and the second amplifier includes a second transistor (MN 2 ) biased with a bias current I bias2 =I 4 −I 2 and connected between V 2 and the circuit common point.

R 1 is connected between the first and second output nodes such that it conducts a current I R1 that varies with V in . When so arranged, the first transistor conducts a current I a =I bias1 −I R1 when VINP>VINN and a current I a =I bias1 +I R1 when VINP<VINN, and the second transistor conducts a current I b =I bias2 −I R1 when VINN>VINP and a current I b =I bias2 +I R1 when VINN<VINP. Circuitry is provided which couples current I a to the current input terminal of a current mirror, and couples current I b to the mirror's current output terminal—which also serves as the IA's current output node. To develop an output voltage, a resistance R 2 is typically connected between the current output node and circuit common, and a buffer amplifier connected to the current output node provides the IA's output voltage V out . Because each of the first and second transistors carries the signal current in R 1 , the current in R 2 is twice that in R 1 . Consequently, the gain G of the IA is given by: G=2*(R 2 /R 1 ) (assuming a current mirror ratio of 1:1). To minimize DC mismatch errors, the present IA is preferably chopper-stabilized and/or auto-zeroed; when chopper-stabilized, both the buffer amplifiers and signal current paths are chopped using a two-phase chopping cycle.

Currents I a and I b are preferably coupled to the current mirror using virtual ground nodes which fold the currents in the first and second transistors around to the output node. When so arranged, the IA requires only the one current mirror described above, instead of the multiple mirrors (and their attendant errors) found in prior art IA designs.

In another embodiment of the invention, the buffer amplifiers are arranged such that the amplifier coupled to VINP produces a signal current I vinp equal to (VINP−VINN)/R 1 and the amplifier coupled to VINN produces a signal current I vinn equal to (VINN−VINP)/R 1 . The IA includes a single current mirror having input and output terminals. Signal currents I vinp and I vinn are folded to respective current mirror terminals using, for example, respective transistors or virtual ground nodes; the current mirror's output terminal serves as the IA's current output node. With R 2 and a reference voltage V ref connected in series between the current output node and a circuit common point, the IA has a gain G given by: G=2*(R 2 /R 1 ) and an output voltage at the current output node given by 2*((VINP−VINN)/R 1 )*R 2 +V ref . Due to the folding of the buffer amplifier currents, only one current mirror is required, while maintaining good common mode rejection versus frequency. This reduces DC errors such as V os and dV os /dT, etc.

Further features and advantages of the invention will be apparent to those skilled in the art from the following detailed description, taken together with the accompanying drawings.

FIG. 1 is a schematic diagram of a prior art IA.

FIG. 2 is a schematic diagram of one embodiment of an IA per the present invention.

FIG. 3 is a schematic diagram of a preferred embodiment of an IA per the present invention.

FIGS. 4 a and 4 b are schematic diagrams of a chopper-stabilized embodiment of an IA per the present invention, as operated during first and second chopping phases, respectively.

FIG. 5 is a schematic diagram of a reference voltage source as might be used with an IA per the present invention.

FIG. 6 is a schematic diagram of an output circuit as might be used with an IA per the present invention.

FIG. 7 is a schematic diagram of another embodiment of an IA per the present invention.

One possible embodiment of a current-mode IA per the present invention is shown in FIG. 2 . The IA includes differential input terminals VINP and VINN which receive a differential voltage V in =VINP−VINN, which are coupled to the input nodes 20 , 22 of first and second buffer amplifiers 24 , 26 , respectively. Buffer amps 24 and 26 produce respective output voltages V 1 and V 2 at respective output nodes 28 , 30 , which vary with VINP and VINN; in the embodiment shown in FIG. 2 , V 1 and V 2 are level-shifted by ˜1 volt from inputs VINP and VINN, respectively. Buffer amp 24 includes a transistor MN 1 connected between output node 28 and a circuit common point 32 , and buffer amp 26 includes a transistor MN 2 connected between output node 30 and circuit common point 32 . Note that, though the transistors depicted in the exemplary embodiments described herein are shown as field-effect transistors (FETs), the invention could also be realized with bipolar transistors, as well as with opposite polarity implementations.

In a typical implementation, input nodes 20 and 22 would be connected to respective input FETs MP 1 and MP 2 , with MP 1 biased with a current source 34 which provides a bias current I 1 , and MP 2 biased with a current source 36 which provides a bias current I 2 . Additional current sources 38 and 40 are connected as shown between a supply voltage (VCC) and nodes 28 and 30 . Current sources 38 and 40 provide currents I 3 and I 4 , respectively, such that FET MN 1 is biased with a current I bias1 approximately given by I 3 −I 1 , and FET MN 2 is biased with a current I bias2 approximately given by I 4 −I 2 .

A resistor 39 having a resistance R 1 is connected between amplifier output nodes 28 and 30 . Since V 1 ≈VINP and V 2 ≈VINN, V in is replicated across R 1 , causing a current flow of (V 1 −V 2 )/R 1 =I R1 in R 1 . When so arranged, FET MN 1 conducts a current I a =I bias1 −I R1 when VINP>VINN and a current I a =I bias1 +I R1 when VINP<VINN, and FET MN 2 conducts a current I b =I bias2 −I R1 when VINN>VINP and a current I b =I bias2 +I R1 when VINN<VINP.

As discussed in more detail below, the present IA is preferably chopper-stabilized and/or auto-zeroed. When chopper-stabilized, the IA is operated in accordance with a two-phase chopping cycle, with amplifiers 24 and 26 , and the signal current paths between the amplifiers and the current mirror, exchanging places between phases. The IA's configuration during one of the chopping phases is shown in FIG. 2 .

For the chopping phase shown, a current mirror 42 is arranged to mirror a current applied at a current input terminal 44 to a current output terminal 46 , with current output terminal 46 being the IA's current output node. Note that current mirror 42 may itself be chopped (as discussed in more detail below), in which case the functions provided by the mirror's terminals are periodically reversed. Circuitry 50 is arranged to couple current I a to the current input terminal of current mirror 42 , and circuitry 52 couples current I b to the mirror's current output terminal. One way in which the coupling might be accomplished is shown in FIG. 2 , in which FETs MN 3 and MN 4 serve as mirror transistors which mirror I a and I b to mirror terminals 44 and 46 , respectively. The present IA typically includes a resistor 54 having a resistance R 2 connected between current output node 46 and circuit common (or to a reference voltage V ref , discussed below) , and a buffer amplifier 55 connected to the current output node which provides the IA's output voltage V out .

Assuming there are no device mismatches, it can be seen that a voltage approximately equal to input voltage V in is applied across R 1 . The resulting current (I R1 ) flows through MN 1 and MN 2 , with both the MN 1 and MN 2 currents coupled to current output node 46 . For the chopping phase shown, when VINP is positive with respect to VINN, the current in MN 3 decreases by ˜V in /R 1 while the current in MN 4 increases by the same amount, such that the current that flows into R 2 is twice the value that flows into R 1 . Consequently, the gain G=(V out −V ref )/V in of this current mode topology is given by G=−2*(R 2 /R 1 ) (V ref is discussed below). Note that for proper operation, the ratio of input current to output current for current mirror 42 should be one.

In some applications, it may be necessary to provide a means to set output voltage V out to a center value when VINP−VINN is equal to a predetermined value, typically zero. If the IA is powered by dual supplies, the center value would typically be set to ground; if a single supply is used, the center value would often be set to VCC/2. One means of setting the center value, shown in FIG. 2 , is to connect a reference voltage source 56 in series with R 2 , with its output voltage V ref selected to provide the desired center value.

Resistances R 1 and R 2 are chosen to set the desired gain needed for a particular application. Resistance R 1 should be made large enough so that the current it diverts from the buffer amplifiers will not cause any of the amplifiers' devices to be turned off. This can be a significant problem with large input signals, so the value of R 1 typically must be larger for low gains than for high gains, where the input signal range is more limited.

Note that this topology is relatively insensitive to additional series wiring resistance in either R 1 or R 2 . This added resistance only results in a small change in gain, but the CMR of the IA is not degraded. Furthermore, common mode input movement produces currents that cancel at R 2 , thereby providing an excellent CMR without the need for perfectly matched resistors.

Note that circuit common point 32 is shown as being “ground”, but this is not essential; other fixed voltages might also be used.

For the I a and I b equations noted above to be correct, I 3 should be greater than I 1 and I 4 should be greater than I 2 , such that an input signal current applied to MN 1 or MN 2 appears as a small signal.

The IA of FIG. 2 is preferably chopper-stabilized and/or auto-zeroed to eliminate DC mismatch errors. When chopper-stabilized, the IA is operated in accordance with a two-phase chopping cycle, with amplifiers 24 and 26 , and the signal current paths between the amplifiers and the current mirror, exchanging places between phases; a duty cycle of 50% is preferred. This requires the use of a number of switches 60 a / 60 b and 64 a / 64 b. During the first phase of the chopping cycle, the IA is configured as shown, with switches 60 a and 60 b arranged to connect input node 20 to VINP and input node 22 to VINN, switch 64 a arranged to connect the drain of MN 3 to current mirror terminal 44 , and switch 64 b arranged to connect the drain of MN 4 to output node 46 . During the second phase of the chopping cycle, the positions of amplifiers 24 and 26 are swapped, such that input nodes 20 and 22 are connected to VINN and VINP, respectively, the drain of MN 3 is connected to output node 46 , and the drain of MN 4 is connected to current mirror terminal 44 . In this way, both the amplifiers and the signal current paths are chopped, thereby making it possible to eliminate trimming steps that might otherwise be necessary.

To further reduce DC mismatch errors, current mirror 42 can be implemented as a chopped mirror and/or as a cascoded mirror (not shown). Note that, if implemented as a chopped mirror, the chopping frequency used for mirror 42 should be different than that used for switches 60 a / 60 b and 64 a / 64 b, to ensure that errors that might otherwise arise due to mismatch between the mirror's transistors are cancelled.

A preferred embodiment of the present IA is shown in FIG. 3 . This implementation is similar to that of FIG. 2 , except for the realization of current coupling circuitry 50 and 52 . Here, circuitry 50 includes current sources 70 and 72 and FETs MN 5 and MN 6 . Current source 70 provides a current I 5 and is connected between the source of MN 1 and circuit common point 32 . Current source 72 provides a current I 6 and is connected between supply voltage VCC and a node 74 . FET MN 5 has its gate coupled to the source of MN 1 , its source connected to circuit common point 32 , and its drain connected to node 74 , and FET MN 6 has its gate coupled to node 74 , its source coupled to the gate of MN 5 , and its drain connected to the current input node 44 of current mirror 42 .

Similarly, circuitry 52 includes current sources 76 and 78 and FETs MN 7 and MN 8 . Current source 76 provides a current I 7 and is connected between the source of MN 2 and circuit common point 32 . Current source 78 provides a current I 8 and is connected between supply voltage VCC and a node 80 . FET MN 7 has its gate coupled to the source of MN 2 , its source connected to circuit common point 32 , and its drain connected to node 80 , and FET MN 8 has its gate coupled to node 80 , its source coupled to the gate of MN 7 , and its drain connected to the current output node 46 of current mirror 42 .

When so arranged, MN 5 /MN 6 and MN 7 /MN 8 form virtual ground nodes that fold the currents in MN 1 and MN 2 around to current output node 46 , with the MN 1 current conveyed to node 46 via current mirror 42 (for the chopping phase shown). When VINP is positive with respect to VINN, the current in MN 6 increases by V in /R 1 while the current in MN 8 decreases by the same amount; the opposite occurs when VINN is positive with respect to VINP. Currents I 5 and I 7 are fixed such that, when I R1 ≠0, the difference between I 5 and I a must be provided by MN 6 and mirrored to current output node 46 , and the difference between I 7 and I b is conducted from current output node 46 by MN 8 . FET MN 5 and current source 72 act to stabilize the node voltage at the gate of MN 5 and source of MN 6 (or MN 8 , depending on chopping phase), and FET MN 7 and current source 78 stabilize the node voltage at the gate of MN 7 and source of MN 8 (or MN 6 , depending on chopping phase).

For the I a and I b equations noted above to be correct for this embodiment, I 3 should be greater than I 1 and I 4 should be greater than I 2 , such that an input signal applied to MN 1 or MN 2 appears as a small signal. For best performance, I 5 should be greater than I bias1 , and I 7 should be greater than I bias2 , such that signal currents in MN 6 and MN 8 appear as small signals. As with the embodiment shown in FIG. 2 , the IA shown in FIG. 3 can be chopper stabilized to eliminate DC mismatch errors. For the chopping phase shown in FIG. 3 , switches 60 a and 60 b are connected between input nodes 20 and 22 and VINP and VINN, respectively, a switch 82 a is connected between the source of MN 6 and the gate of MN 5 , a switch 82 b is connected between the source of MN 8 and the gate of MN 7 , a switch 83 a is connected between the gate of MN 6 and node 74 , and a switch 83 b is connected between the gate of MN 8 and node 80 , such that both the buffer amplifiers and the signal current paths are chopped. The operation of a chopper-stabilized version of the IA of FIG. 3 during the first and second chopping phases is shown in FIGS. 4 a and 4 b, respectively. Amplifiers 24 and 26 exchange positions from FIG. 4 a to FIG. 4 b, thereby enabling DC mismatches within the amplifiers and the current sources to be largely eliminated. For example, assume that VINP−VINN=1V, and amplifier 24 has a 10 mV input offset voltage. During the first chopping phase, the buffer amplifiers apply 1V+10mv=1.01V across R 1 , whereas during the second chopping phase the amplifiers apply 0.99V across R 1 . As a result, the average differential input voltage applied across R 1 over the full chopping cycle is 1V.

As with the embodiment shown in FIG. 2 , DC mismatch errors can be further reduced by implementing current mirror 42 as a chopped mirror, and/or as a cascoded mirror (not shown).

Another advantage of this topology is that parasitic capacitance on output nodes 28 and 30 (CP 1 , CP 2 , shown in FIGS. 4 a and 4 b ) does not cause a degradation in CMR versus frequency. As common mode input voltage increases, parasitic capacitances CP 1 and CP 2 need to be charged. As a result, the currents in MN 6 and MN 8 will increase. But, if CP 1 and CP 2 are balanced, the amount that the MN 6 current changes will match the change in MN 8 . Consequently, the average current into R 2 will not change, thereby providing a good CMR versus frequency characteristic.

It should further be noted that the topology shown in FIG. 3 employs a single current mirror, instead of the multiple mirrors found in prior art IA designs and which can contribute offset, offset drift and DC errors to the IA output. By eliminating all but one current mirror in accordance with the present invention, errors associated with the other mirrors are eliminated.

An alternative means of setting output voltage V out to a center value when VINP−VINN is equal to a predetermined value is shown in FIG. 5 . Here, resistor R 2 and reference voltage source 56 are replaced with a divider comprising resistors R 2 a and R 2 b, chosen to bias current output node 46 as needed without needing an external amplifier. This is desirable, because it allows a user using a single supply to avoid the cost and board space needed for an external amplifier to bias the output within the valid output range of the IA.

Another possible means of setting output voltage V out to a center value is shown in FIG. 6 . Here, an amplifier 90 is connected to current output node 46 at its inverting input, and to V ref at its non-inverting input. Resistor R 2 is connected between the output and inverting input of amplifier 90 and sets the IA's gain G=2*(R 2 /R 1 ). The voltage at node 46 , and thus V out , is set by V ref . Note that for the previous embodiments, a positive current into node 46 caused an increase in V out . Here, a negative current into node 46 causes an increase in V out ; as such, the inputs of amplifier 90 are reversed with respect to those of amplifier 55 in FIGS. 2 , 3 , 4 a, 4 b and 5 .

Another possible embodiment of an IA per the present invention is shown in FIG. 7 . This embodiment assumes (but does not show) first and second input terminals which receive a differential voltage (VINP−VINN), first and second buffer amplifiers which receive the differential voltage and provide first and second output voltages at respective output nodes which vary with VINP and VINN, respectively, and a resistance R 1 connected between the output nodes. The amplifiers are arranged such that the amplifier coupled to VINP produces a signal current I vinp equal to (VINP−VINN)/R 1 and the amplifier coupled to VINN produces a signal current I vinn equal to (VINN−VINP)/R 1 . Signal currents I vinp and I vinn are represented in FIG. 7 with current sources 100 and 102 , respectively.

The IA includes a current mirror 104 having an input terminal 106 and an output terminal 108 ; terminal 108 serves as the IA's current output node. Respective current folding circuits 110 and 112 fold signal currents I vinp and I vinn to respective current mirror terminals. With a resistance R 2 and a reference voltage V ref connected in series between the current output node and a circuit common point, the IA has a gain G given by: G=2*(R 2 /R 1 ) and an output voltage at current output node 108 given by 2*((VINP−VINN)/R 1 )*R 2 +V ref .

Due to the folding of the buffer amplifier currents I vinp and I vinn , the IA requires only one current mirror ( 104 ) in the IA's signal path, and provides good common mode rejection versus frequency. This reduces DC errors such as V os and dV os /dT, etc.

Folding circuits 110 and 112 can comprise respective transistors biased with respective bias voltages, as shown in FIG. 7 . Alternatively, folding circuits 110 and 112 could comprise respective virtual ground nodes such as those ( 50 , 52 ) shown in FIG. 3 .

While particular embodiments of the invention have been shown and described, numerous variations and alternate embodiments will occur to those skilled in the art. Accordingly, it is intended that the invention be limited only in terms of the appended claims.