Liquid crystal display device with prevention of defective disconnection of drain/pixel electrodes by forming two conductive layers on top of entire pixel electrode and then removing a portion of both therefrom

This application claims the benefit of Korean Patent Application No. 10-2004-0063590, filed on Aug. 12, 2004, which is hereby incorporated by reference for all purposes as if fully set forth herein.

1. Field of the Invention

The present invention relates to a liquid crystal display (LCD) device and its fabrication method, and more particularly, to an LCD device and its fabrication method capable of simplifying a fabrication process and enhancing yield by reducing the number of masks used for fabrication of a polycrystalline silicon thin film transistor.

2. Description of the Related Art

Recently, as research and development of information displays and demand for using a portable (mobile) information medium increase, research on and commercialization of a light thin film type flat panel display (FPD) which can substitute for the existing display device CRT are actively ongoing.

Of the FPDs, in particular, an LCD, a device for producing an image by using the optical anisotropy of liquid crystal, exhibits excellent resolution, color display and picture quality, so it is popular in notebook computers, desktop monitors or the like.

The liquid crystal display panel includes a color filter substrate, namely, a first substrate, an array substrate, namely, a second substrate, and a liquid crystal layer formed between the color filter substrate and the array substrate.

As a switching device of the liquid crystal display device, the thin film transistor (TFT) is used, and as a channel layer of the TFT, an amorphous silicon thin film or a polycrystalline silicon thin film is used.

In a process for fabricating the LCD device, a plurality of masking processes (namely, photolithography process) are required for fabricating the array substrate including the TFT, so a method for reducing the number of masking processes is on demand in terms of productivity.

The structure of the general LCD device will now be described with reference to FIG. 1 .

FIG. 1 is a plan view illustrating a portion of an array substrate of the general LCD device. Although actual array substrate includes the M×N number of pixels as the N number of gate lines and the M number of data lines cross each other, only one pixel is illustrated in FIG. 1 for the sake of explanation.

As illustrated, a gate line 16 and a data line 17 are arranged vertically and horizontally on an array substrate 10 , defining a pixel region. A TFT as a switching device is formed at the crossing of the gate line 16 and the data line 17 . A pixel electrode 18 is formed at each pixel region.

The TFT includes a gate electrode 21 connected to the gate line 16 , a source electrode 22 connected to the data line 17 and a drain electrode 23 connected to the pixel electrode 18 . The TFT also includes a first insulation film (not illustrated) and a second insulation film (not illustrated) for insulating the gate electrode 21 and source/drain electrodes 22 and 23 , and an active pattern 24 for forming a conductive channel between the source electrode 22 and drain electrode 23 by a gate voltage supplied to the gate electrode 21 .

Through the first contact hole 40 A formed at the first and second insulation films, the source electrode 22 is electrically connected with a source region of the active pattern 24 and the drain electrode 23 is electrically connected with a drain region of the active pattern 24 .

A third insulation film (not illustrated) having a second contact hole 40 B is formed on the drain electrode 23 , so that the drain electrode 23 and the pixel electrode 18 are electrically connected through the second contact hole 40 B.

The process of fabricating the array substrate constructed as described will now be explained with reference to FIGS. 2A to 2F .

FIGS. 2A to 2F are sequential sectional views of the process for fabricating the array substrate of FIG. 1 taken along line I-I′. The illustrated TFT is a polycrystalline silicon TFT which uses polycrystalline silicon as a channel layer.

As illustrated in FIG. 2A , the active pattern 24 is formed as a polycrystalline silicon thin film on the substrate 10 by using a photolithography process (a first masking process).

Next, as illustrated in FIG. 2B , a first insulation film 15 A and a conductive metal material are sequentially deposited on the entire surface of the substrate 10 with the active pattern 24 formed thereon, and then, the conductive metal material is selectively patterned by using the photolithography process (a second masking process) to form the gate electrode 21 over the active pattern 24 with the first insulation film 15 A interposed therebetween.

Thereafter, p+ type or n+ type source/drain regions 24 A and 24 B are formed at certain regions of the active pattern 24 by injecting a high density impurity ion by using the gate electrode 21 as a mask. The source/drain regions 24 A and 24 B are formed for ohmic contact with source/drain electrodes (to be described).

And then, as illustrated in FIG. 2C , a second insulation film 15 B is deposed on the entire surface of the substrate 10 with the gate electrode 21 formed thereon, and then, a portion of the first and second insulation films 15 A and 15 B is removed through the photolithography (a third masking process) to form the first contact hole 40 A exposing a portion of the source/drain regions 24 A and 24 B.

Subsequently, as illustrated in FIG. 2D , a conductive metal material is deposited on the entire surface of the substrate 10 and then patterned by using the photolithography process (a fourth making process) to form the source electrode 22 connected with the source region 24 A and the drain electrode 23 connected with the drain region 24 B through the first contact hole 40 A. In this case, a portion of the conductive metal layer constituting the source electrode 22 extends in one direction to form the data line 17 .

And then, as illustrated in FIG. 2E , a third insulation film 15 C is deposited on the entire surface of the substrate 10 , and then, a second contact hole 40 B is formed, exposing a portion of the drain electrode 23 by using the photolithography process (a fifth masking process).

Finally, as illustrated in FIG. 2F , a transparent conductive metal material is deposited on the entire surface of the substrate 10 with the third insulation film 15 C formed thereon and then patterned by using the photolithography process (a sixth masking process) to form a pixel electrode 18 connected with the drain electrode 23 through the second contact hole 40 B.

As mentioned above, in fabricating the array substrate including the polycrystalline silicon TFT, a total of six photolithography processes are required to pattern the active pattern, the gate electrode, the first contact hole, the source/drain electrodes, the second contact hole and the pixel electrode.

The photolithography process is a process of transferring a pattern formed on a mask onto the thin film-deposited substrate to form a desired pattern, including a plurality of processes such as applying a photosensitive solution, exposing and developing process. As a result, the plurality of photolithography processes degrade a production yield and cause a high possibility that a fabricated TFT is defective.

In particular, the mask designed to form the pattern is expensive, so the increase in the number of masks applied to the process would lead to an increase in a fabrication cost proportionally.

Therefore, one advantage of the present invention is to provide an LCD device and its fabrication method capable of reducing the number of masks to be used for fabrication of a thin film transistor (TFT) by simultaneously forming a gate electrode, a gate line and a pixel electrode.

Another advantage of the present invention is to provide an LCD device and its fabrication method capable of preventing a defective disconnection of a drain electrode due to an undercut at an edge of a pixel electrode by simultaneously performing patterning of source/drain electrodes and removing of a gate metal exposing the pixel electrode.

To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described herein, there is provided a method for fabricating an LCD device including: providing first and second substrates; forming an active layer having a source region, a drain region and a channel region on the first substrate; forming a first insulation layer on the first substrate; forming first and second conductive layers on the first substrate; forming a gate electrode, a gate line and a pixel electrode by patterning the first and second conductive layers; forming a second insulation layer on the first substrate; forming a contact hole exposing a portion of the source and drain regions by removing a portion of the first and second insulation layers and removing the second insulation layer of the upper portion of the pixel electrode; forming a third conductive layer on the first substrate; forming source and drain electrodes electrically connected to the source and drain regions through the contact hole by patterning the third conductive layer and exposing the second conductive layer of the upper portion of the pixel electrode; and forming a liquid crystal layer between the first and second substrates.

To achieve the above advantages, there is also provided a method for fabricating an LCD device including: providing first and second substrates; forming an active layer on the first substrate; forming a first insulation layer on the first substrate; forming a gate electrode, a gate line and a pixel electrode formed of a dual layer having first and second conductive layers; forming a second insulation layer exposing a portion of the active layer and the pixel electrode; forming source and drain electrodes electrically connected to the portion of the active layer through the contact hole by patterning a third conductive layer and exposing the pixel electrode of the first conductive layer; and forming a liquid crystal layer between the first and second substrates.

In order to achieve the above advantages, there is also provided a liquid crystal display (LCD) device including: first and second substrates; an active layer on the first substrate; a first insulation layer on the first substrate; a gate electrode, a gate line and a pixel electrode, the gate electrode and the gate line having first and second conductive layers and the pixel electrode having the first conductive layer; a second insulation layer on the first substrate, the second insulation layer having a contact hole; a source electrode and a drain electrode on the first substrate, the source electrode being connected to a source region and the drain electrode being connected to a drain region through the contact hole; and a liquid crystal layer between the first and second substrates.

The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.

In the drawings:

FIG. 1 is a plan view illustrating a portion of an array substrate of a general LCD device;

FIGS. 2A to 2F are sequential sectional view illustrating a process of fabricating the array substrate taken along line I-I′ of FIG. 1 ;

FIG. 3 is a plan view illustrating a portion of an array substrate of an LCD device in accordance with the first embodiment of the present invention;

FIGS. 4A to 4D are sequential sectional views illustrating a process of fabricating the array substrate taken along line III-III′ of FIG. 3 ;

FIGS. 5A to 5D are sectional views illustrating a process of simultaneously forming a gate electrode, a gate line and a pixel electrode in FIGS. 4B and 4C in accordance with the first embodiment of the present invention;

FIGS. 6A to 6D are sequential sectional views illustrating a process of fabricating an array substrate in accordance with a second embodiment of the present invention;

FIGS. 7A to 7D are sequential plan views illustrating the process of fabricating the array substrate in accordance with the second embodiment of the present invention; and

FIGS. 8A to 8D are sectional view illustrating a process of forming a gate electrode, a gate line and a pixel electrode in FIGS. 6B to 6D in accordance with the second embodiment of the present invention.

An LCD device and its fabrication method in accordance with exemplary embodiments of the present invention will now be described with reference to the accompanying drawings.

FIG. 3 is a plan view illustrating a portion of an array substrate of an LCD device in accordance with the first embodiment of the present invention, particularly illustrating one pixel including a thin film transistor (TFT). Although actual LCD device includes the M×N number of pixels as the N number of gate lines and the M number of data lines cross each other, only one pixel is illustrated in FIG. 3 for the sake of explanation.

In this embodiment, a polycrystalline silicon TFT using a polycrystalline silicon thin film as a channel layer is taken as an example, and the present invention is not limited thereto and an amorphous silicon thin film can be used as the channel layer of the TFT.

As illustrated, a gate line 116 and a data line 117 are arranged vertically and horizontally on the array substrate 110 , defining a pixel region. In addition, a TFT as a switching device is formed at the crossing of the gate line 116 and the data line 117 , and a pixel electrode 150 B connected with the TFT and driving liquid crystal (not illustrated) together with a common electrode of a color filter substrate (not illustrated) is formed in the pixel region.

The TFT includes a gate electrode 121 connected with the gate line 116 , a source electrode 122 connected with the data line 117 and a drain electrode 123 connected with the pixel electrode 150 B. In addition, the TFT also includes first and second insulation films (not illustrated) for insulating the gate electrode 121 and the source/drain electrodes 122 and 123 , and an active pattern 124 for forming a conductive channel between the source electrode 122 and the drain electrode 123 by a gate voltage supplied to the gate electrode 121 .

A portion of the source electrode 122 is electrically connected with a source region of the active pattern 124 and a portion of the drain electrode 123 is electrically connected with a drain region of the active pattern 124 through a contact hole 140 formed at the first and second insulation films. Another portion of the source electrode 122 is connected with the data line 117 to form a portion of the data line 117 and another portion of the drain electrode 123 extends toward the pixel region to be electrically connected with the pixel electrode 150 B.

A conductive pattern 160 B′ formed of a gate metal (namely, a conductive material constituting the gate electrode 121 and the gate line 116 ) remains at an edge of the pixel electrode 150 B, and by simultaneously forming the pixel electrode 150 B together with the gate electrode 121 and the gate line 116 on the same layer, the number of masks used for fabricating the TFT can be reduced, which will now be described in detail through a process for fabricating the array substrate.

FIGS. 4A to 4D are sequential sectional views illustrating a process of fabricating the array substrate taken along line III-III′ of FIG. 3 .

As illustrated in FIG. 4A , the active pattern 124 is formed as a silicon layer on the substrate 110 made of a transparent insulation material such as glass by using a photolithography process (a first masking process).

In this case, a buffer layer can be formed as a silicon oxide film (SiO2) on the substrate 110 , on which the active pattern 124 can be formed. The buffer layer serves to prevent infiltration of an impurity such as natrium (Na) existing in the glass substrate 110 into an upper layer during a process.

The silicon layer can be formed as an amorphous silicon thin film or a crystallized silicon thin film, and in the present invention, the TFT is formed by using the crystallized polycrystalline silicon thin film. The polycrystalline silicon thin film can be formed by using various crystallizing methods after the amorphous silicon thin film is formed on the substrate, which will be described as follows.

First, the amorphous silicon thin film can be deposited to be formed in various methods, of which a typical method is a low pressure chemical vapor deposition (LPCVD) and plasma enhanced chemical vapor deposition (PECVD).

Thereafter, in order to remove hydrogen atoms existing in the amorphous silicon thin film, dehydrogenation process is performed and then crystallization is performed thereon. In order to crystallize the amorphous silicon thin film, solid phase crystallization (SPC) in which the amorphous silicon thin film is thermally treated in a high temperature furnace or examiner laser annealing (ELA) using laser can be used.

As the laser crystallization, the ELA using laser in a pulse form is commonly used, and recently, research is ongoing on sequential lateral solidification (SLS) which remarkably improves crystallization characteristics by making grains grow laterally (in a horizontal direction).

The SLS uses the fact that grains are grown in a vertical direction to an interface of liquid phase silicon and solid phase silicon at the interface. By growing grains to a certain length laterally by suitably controlling a size of a laser energy and laser beam irradiation range, the size of silicon grains can be enhanced.

FIGS. 4B and 4C illustrate the process of simultaneously forming the gate electrode, the gate line and the pixel electrode in accordance with the first embodiment of the present invention, which will now be described with reference to FIGS. 5A and 5D .

As illustrated in FIG. 5A , a first insulation film 115 A, namely, a gate insulation film, a first conductive film 150 and a second conductive film 160 are sequentially formed on the entire surface of the substrate 110 with the active pattern 124 formed thereon.

The first conductive film 150 is made of a transparent conductive material with excellent transmittance, such as indium tin oxide (ITO) or indium zinc oxide (IZO), for forming the pixel electrode, and the second conductive film 160 is formed of a low-resistance opaque conductive material such as aluminum, an aluminum alloy, tungsten, copper, chromium, molybdenum or the like for forming the gate electrode and the gate line.

Next, as illustrated in FIG. 5B (or FIG. 4B ), the second conductive film 160 and the first conductive film 150 are selectively patterned by using the photolithography process (a second masking process) in order to form the gate electrode 121 , the gate line 116 and the pixel electrode 150 B.

The gate electrode 121 includes a first gate electrode pattern 150 A formed as a transparent first conductive film and a second gate electrode pattern 160 A formed as an opaque second conductive film, and a pixel electrode pattern 160 B formed as an opaque second conductive film with the same form as the pixel electrode 150 B remains on the pixel electrode 150 B formed of the transparent first conductive film.

Thereafter, an impurity ion (namely, dopant) is injected into certain regions of the active pattern 124 by using the gate electrode 121 as a mask to form a source region 124 A and a drain region 124 B, namely, ohmic contract layers. In this case, the gate electrode 121 serves as an ion stopper preventing infiltration of the dopant into the channel region 124 C of the active pattern 124 .

Electrical characteristics of the active pattern 124 can change according to a type of the injected dopant, and if the injected dopant corresponds to a 3-group element such as boron (B), it operates as a P-type TFT, while if the injected dopant corresponds to a 5-group element such as phosphor (P), it operates as an N-type TFT.

After the ion-injection process, a process for activating the injected dopant can be performed.

Thereafter, as illustrated in FIG. 5C , a second insulation film 115 B is deposited on the entire surface of the substrate 110 with the gate electrode 121 , the gate line 116 and the pixel electrode 150 B formed thereon, to form a photosensitive film 170 made of a photosensitive material such as photoresist.

The second insulation film 115 B can be formed of a transparent organic insulation material such as benzocyclobutene (BCB) or an acrylic resin for a high aperture ratio.

And then, as illustrated in FIG. 5D , light is irradiated on the photosensitive film through the photolithography process (a third masking process) and then the exposed photosensitive film 170 is developed to form a photosensitive film pattern 170 ′ for forming the contact hole and opening the pixel electrode region.

Subsequently, a portion of the second insulation film 115 B and the first insulation film 115 A is removed by using the photosensitive film pattern 170 ′ as a mask to form a pair of contact holes 140 exposing a portion of the source/drain regions 124 A and 124 B of the active pattern 124 , and simultaneously, the second insulation film 115 B and the pixel electrode pattern 160 B formed as the second conductive film at the pixel electrode region are removed to expose the surface of the pixel electrode 150 B formed as the first conductive film formed of the transparent conductive material.

Because of the alignment margin between photolithography equipment and the mask, the pixel electrode region is opened with a certain distance inward from the pixel electrode 150 B, leaving the second conductive film pattern 160 B′ formed as the second conductive film at an upper portion of the edge of the pixel electrode 150 B.

The pixel electrode pattern 160 B remaining at the upper portion of the pixel electrode 150 B is not removed using a mask but removed using the pattern of the second insulation film 115 B (or the photosensitive film pattern 170 ′)) so that the pixel electrode region can be simultaneously opened when the contact hole 140 is formed, and in this case, the second conductive film, namely, the pixel electrode pattern 160 B is excessively etched to generate an undercut at the boundary between the second insulation film 115 B at the upper portion of the edge of the pixel electrode 150 B and the second conductive film pattern 160 B′.

Thereafter, as illustrated in FIG. 4C , the photosensitive film pattern 170 ′ is removed and then the photolithography process is performed twice to form the gate electrode 121 , the gate line 116 and the pixel electrode 150 B.

And then, as illustrated in FIG. 4D , a third conductive film is deposited on the entire surface of the substrate 110 and then patterned by using the photolithography process (a fourth masking process) to form the source electrode 122 connected with the source region 124 A and the drain electrode 123 connected with the drain region 124 B through the contact hole 140 .

A portion of the source electrode 122 extends in one direction to form the data line 117 and a portion of the drain electrode 123 extends toward the pixel electrode so as to be connected with the pixel electrode 150 B.

In the process of fabricating the array substrate in accordance with the first embodiment of the present invention, the gate electrode, the gate line and the pixel electrode are simultaneously patterned and one process for forming contact hole is reduced, so that two times of masking processes are reduced compared with a general fabrication process. Accordingly, the yield can be increased thanks to the simplification of the fabrication process and the fabrication cost can be reduced.

However, as illustrated, due to the undercut at the second conductive film pattern 160 B′ formed at the upper portion of the edge of the pixel electrode 150 B, the drain electrode 123 and the pixel electrode 150 B may not connected.

Thus, the second conductive film is etched to open the pixel electrode region in the following process of forming the source/drain electrodes in order to prevent the deficiency of disconnection between the drain electrode and the pixel electrode due to the undercut of the second conductive film pattern. This will be described in detail in the second embodiment of the present invention as follows.

FIGS. 6A to 6D are sequential sectional views illustrating a process of fabricating an array substrate in accordance with a second embodiment of the present invention, and FIGS. 7A to 7D are sequential plan views illustrating the process of fabricating the array substrate in accordance with the second embodiment of the present invention.

The process for fabricating the LCD device in the second embodiment is the same as that of the first embodiment, except that a process order is changed to prevent a disconnection between the drain electrode and the pixel electrode caused by an undercutting of the second conductive film pattern that is generated when the second insulation film and the second conductive film of the pixel electrode region are etched.

With reference to FIGS. 6A and 7A , an active pattern 224 is formed as a silicon layer on a substrate 210 made of a transparent insulation material such as glass by using the photolithography process (a first masking process).

Next, as illustrated in FIGS. 6B and 7B , a first insulation film 215 A, a first conductive film and a second conductive film are sequentially formed on the entire surface of the substrate 210 .

And then, the second and the first conductive films are selectively patterned by using the photolithography (a second making process) to simultaneously form a gate electrode 221 , a gate line 216 and a pixel electrode 250 B.

The gate electrode 221 includes a first gate electrode pattern 250 A formed as the transparent first conductive film and a second gate electrode pattern 260 A formed as the opaque second conductive film, and a pixel electrode pattern 260 B formed as an opaque second conductive film with the same form as the pixel electrode 250 B remains on the pixel electrode 250 B made of the transparent first conductive film.

Thereafter, an impurity ion (namely, dopant) is injected into a certain region of the active pattern 224 by using the gate electrode 221 as a mask to form a source region 224 A and a drain region 224 B, namely, ohmic contract layers.

In order to prevent disconnection between the drain electrode and the pixel electrode due to the undercut of the second conductive film pattern in the first embodiment, in the second embodiment, the second conductive film for opening the pixel electrode region is etched in the following process of forming the source/drain electrodes. This will be described in detail through the follow-up process of FIGS. 6C and 6D .

As illustrated in FIGS. 6C and 7C , a second insulation film 215 B is deposited on the entire surface of the substrate 210 with the gate electrode 221 , the gate line and the pixel electrode 250 B formed thereon, and then patterned through the photolithography process (a third masking process) to form the contact hole 240 at the source/drain regions 224 A and 224 B and at the same time open the pixel electrode region. In this embodiment, only the second insulation film 215 B of the pixel electrode region is removed to leave the pixel electrode pattern 260 B made of the second conductive film at the upper portion of the pixel electrode 250 B.

The third masking process will be described in detail through FIGS. 8A to 8D as follows.

First, as illustrated in FIG. 8A , a first photosensitive film 270 made of a photosensitive material such as photoresist is formed on the entire surface of the substrate 210 with the second insulation film 215 B formed thereon.

Thereafter, as illustrated in FIG. 8B , light is irradiated on the first photosensitive film 270 through the photolithography process and then the exposed first photosensitive film 270 is developed to form a first photosensitive film pattern 270 ′ for forming the contact hole and opening the pixel electrode region.

Subsequently, a portion of the second insulation film 215 B and the first insulation film 215 A is removed by using the first photosensitive film pattern 270 ′ as a mask to form a pair of contact holes 240 exposing a portion of the source/drain regions 224 A and 224 B of the active pattern 224 , and simultaneously, the second insulation film 215 B of the pixel electrode region is removed to expose the surface of the pixel electrode pattern 260 B formed as the second conductive film.

Thereafter, as illustrated in FIG. 8C , a third conductive film 280 is deposited on the entire surface of the substrate 210 , and then, a second photosensitive film 370 for patterning the source/drain electrodes is formed.

At this time, since a third conductive film 280 is directly deposited at the upper portion of the pixel electrode pattern 250 B of the pixel electrode region so as to be electrically connected with the pixel electrode pattern 250 B, although the a portion of the pixel electrode pattern 250 B and the third conductive film 280 is removed through an etching process (to be described), such a deficiency of disconnection between the drain electrode and the pixel electrode as in the first embodiment cannot be generated.

Light is selectively irradiated on the second photosensitive film 370 through the photolithography process (a fourth masking process), and then, the exposed second photosensitive film 370 is developed to form a second photosensitive film pattern 370 ′ for defining the source/drain electrode regions and removing the pixel electrode pattern 260 B of the pixel electrode region.

A portion of the third conductive film 280 is removed by using the second photosensitive film pattern 370 ′ as a mask to simultaneously form a source electrode 222 connected with the source region 224 A and a drain electrode 223 connected with the drain region 224 B through the contact hole 240 , and at the same time, the pixel electrode pattern 260 B of the pixel electrode region is removed to expose the surface of the pixel electrode 250 B formed as the transparent first conductive film.

In this case, in order to simultaneously etch the third conductive film constituting the source/drain electrodes 222 and 223 and the second conductive film constituting the pixel electrode pattern 260 B through one time of etching process, the second and third conductive films can be formed of the same conductive metal material.

For the same reason as in the first embodiment of the present invention, the pixel electrode pattern 260 B of the pixel electrode region remains at the upper portion of the edge of the pixel electrode 250 B, without being etched, to form a second conductive film pattern 260 B′.

When the pixel electrode pattern 260 B formed as the second conductive film remaining at the upper portion of the pixel electrode 250 B is removed at the same time when the source/drain electrodes 222 and 223 are formed, although undercut is generated at the boundary of the second conductive film pattern 260 B′ due to an excessive etching of the second conductive film, such a deficiency of disconnection between the drain electrode 223 and the pixel electrode as in the first embodiment of the present invention cannot be generated because the drain electrode 223 and the second conductive film pattern 260 B′ are connected.

Thereafter, as illustrated in FIGS. 6D and 7D , when the second photosensitive film pattern 370 ′ is removed, the gate electrode 221 , the source/drain electrodes 222 and 223 and the pixel electrode 250 B are formed.

At this time, a portion of the source electrode 222 extends in one direction to form a data line 217 , and a portion of the drain electrode 223 extends toward the pixel region so as to be connected with the pixel electrode 250 B.

As so far described, the LCD device and its fabrication method in accordance with the present invention have many advantages.

That is, for example, because the gate electrode and the pixel electrode are simultaneously patterned, the number of masks used for fabrication of the TFT can be reduced, and thus, the fabrication process and cost can be reduced.

In addition, in fabricating the array substrate with the four-masking structure, the deficiency of disconnection between the drain electrode and the pixel electrode generated when the pixel electrode region is opened is solved, so the yield can be enhanced.

As the present invention may be embodied in several forms without departing from the spirit or essential characteristics thereof, it should also be understood that the above-described embodiments are not limited by any of the details of the foregoing description, unless otherwise specified, but rather should be construed broadly within its spirit and scope as defined in the appended claims, and therefore all changes and modifications that fall within the metes and bounds of the claims, or equivalence of such metes and bounds are therefore intended to be embraced by the appended claims.