Semiconductor conductive layers

This application claims priority under 35 U.S.C. 119(e) from U.S. Provisional Application Ser. No. 60/579,639 filed 15 Jun. 2004, which application is incorporated herein by reference.

This invention was made with government support under Grant No. F49620-03-1-0437 awarded by the Air Force Office of Scientific Research. The United States Government has certain rights in the invention.

This invention relates to electronic devices, in particular, to semiconductor devices.

With the recent increased interest in mid-wavelength infrared (hereinafter referred to as “MWIR”) optoelectronic devices and applications, much attention has been directed to semiconductor optoelectronic devices, such as lasers, light emitting diodes (hereinafter referred to as “LEDs”), photodetectors, photodiodes, or the like. Particular concern has been directed to the area of lasers that operate at wavelengths between approximately 2 μm and 6 μm. Such devices are essential components in optical systems, which may be used for applications including remote sensing, LADAR, detection of chemical warfare agents, intelligence, surveillance and reconnaissance (ISR), enemy missile tracking and infrared countermeasures (IRCM).

An example of one such device is an edge-emitting laser (hereinafter referred to as an “EEL”), which may be used to provide a light signal in the above-mentioned optical systems. EELs typically include upper and lower contacting and cladding regions, formed on opposite sides of an active region. The EEL may be driven or pumped electrically by forcing current through the active region or optically by supplying light of a desired frequency to the active region.

In conventional telecommunication and data-communication EELs, typical device structures perform adequately. However, for MWIR applications, it is typically difficult to form structures with both good optical performance and, simultaneously, good electrical performance.

It is generally desirable to provide an EEL device with improved conductive regions that provide current flow through the active region of the device. Current flow is typically achieved by including highly doped layers in the EEL, on either side of the active region, allowing a high vertical current flow. However, sufficiently high doping levels can be difficult to achieve for some semiconductor materials used in MWIR devices, causing undesirable effects on current flow. In particular, n-type doping of InGaAlSb layers is a key problem in the realization of MWIR devices. It is difficult to achieve high electron concentrations in many compositions of this alloy since the ionization energy can be relatively high. Without adequate current flow, resistivity of devices increases and current injection can be non-uniform or exhibit current crowding effects, problems which can degrade optoelectronic device performance. Furthermore, growth of some semiconductor materials required for forming conductive regions is limited by the miscibility gap.

It would be highly advantageous, therefore, to remedy the foregoing and other deficiencies inherent in the prior art.

Embodiments and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in these embodiments and their equivalents.

FIG. 1 is a plan view of an edge emitting laser in accordance with an embodiment of the present invention.

FIG. 2 is a plan view of a conductive region of an edge emitting laser in accordance with an embodiment of the present invention.

FIGS. 3 , 4 , and 5 are graphs of the log of the carrier concentration (N) as a function of temperature for In x Al 1−x Sb (x=0.0725, x=0.30 and x=0.555) layers, obtained by Hall measurements.

FIG. 6 is a plot of activation energy as a function of the composition of InAlSb.

FIG. 7 is a plot of the log of the carrier concentration against inverse temperature for several compositions of Te-doped In x Al 1−x Sb;

FIG. 8 is a plot of room temperature-normalized carrier concentration as a function of temperature for several compositions of Te-doped In x Al 1−x Sb; and

FIG. 9 is a plot of a current-voltage (I-V) relationship for a PIN diode fabricated using a superlattice of AlSb/In 0.50 Al 0.50 Sb.

The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the invention. The various embodiments disclosed herein are not necessarily mutually exclusive, as some disclosed embodiments may be combined with one or more other disclosed embodiments to form new embodiments. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the embodiments of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.

Turning now to FIG. 1 , a sectional view of an edge emitting laser 100 is illustrated. EEL 100 is illustrated in an embodiment for simplicity and ease of discussion. However, it will be understood that other optoelectronic devices could be used and the illustration of EEL 100 is not meant to limit the scope of the invention. For example, a vertical-cavity surface-emitting laser, a quantum cascade laser, light emitting diode, or the like may also be used. As can be appreciated by those skilled in the art, optoelectronic devices include devices that provide light emission, light absorption, or light modulation.

In an embodiment, EEL 100 includes a substrate 102 , wherein substrate 102 includes gallium antimonide (GaSb). However, it will be understood that substrate 102 may include other materials such as indium phosphide (InP), indium arsenide (InAs), gallium arsenide (GaAs), silicon (Si), an epitaxially grown material (such as a ternary or quaternary semiconductor), or the like. It will also be understood that substrate 102 typically includes a lattice constant chosen to minimize defects in materials subsequently grown thereon.

In an embodiment, a buffer region 104 is positioned on substrate 102 . It will be understood that buffer region 104 may include more than one material layer, but is illustrated as including a single layer in an embodiment for simplicity and ease of discussion. In an embodiment, buffer layer 104 consists of a digital alloy (hereinafter referred to as “DA”) semiconductor superlattice of InAlSb layers, designed to provide a low defect density. As understood by those skilled in the art, a digital alloy is an alloy with an average composition that is grown using two or more different semiconductor components. The average composition of the digital alloy depends on the thickness and composition of each of the constituent layer types used to form the superlattice. The superlattice layers are typically thin, of the order of 10-100 Angstrom, so that the resulting material has the properties of the average composition and not of the individual layers constituting the alloy. Further, buffer region 104 provides a lattice constant, which may be different from the lattice constant of substrate 102 , and is chosen to minimize defects in materials subsequently grown thereon. However, it will also be understood that buffer region 104 may be formed in other semiconductor materials, including AlGaAs, InP and the like.

In an embodiment, conductive region 106 is positioned on buffer region 104 . It will be understood that conductive region 106 may include more than one material layer, but is illustrated as including a single layer in an embodiment for simplicity and ease of discussion. Also in an embodiment, conductive region 106 includes highly doped semiconductor material with a conductivity type (i.e. n-type or p-type) to provide a lateral contact and current spreading. The design of conductive region 106 will be discussed separately.

In an embodiment, a cladding region 108 is positioned on conductive region 106 and a waveguiding layer 110 is positioned on cladding layer 108 . An active region 112 is positioned on waveguiding region 110 wherein active region 112 includes a material capable of emitting a substantial amount of light at a desired wavelength of operation. As can be appreciated by those skilled in the art, an active region capable of emitting light is a light processing region. Other light processing regions include regions to absorb light and regions to modulate light. In an embodiment, the desired wavelength of operation is in a range given approximately from 2.0 μm to 5.0 μm. However, it will be understood that other wavelength ranges may be desired and will depend on the substrate material and the intended application.

Further, it will be understood that active region 112 may include various light emitting structures, such as quantum dots, quantum wells, or the like, which improve a light emitting efficiency of EEL 100 . Also, it will be understood that active region 112 may include more than one material layer, but is illustrated as including a single layer in an embodiment for simplicity and ease of discussion.

In an embodiment, a waveguiding region 114 is positioned on active region 112 and a cladding region 116 is positioned on waveguiding region 114 . In an embodiment, a conductive region 118 is positioned on cladding region 116 . It will be understood that conductive semiconductor region 118 may include more than one material layer, but is illustrated as including a single material layer in an embodiment for simplicity and ease of discussion. Conductive region 118 includes highly doped semiconductor material with a conductivity type opposite to that of conductive contact region 106 (i.e. p-type or n-type). The design of conductive semiconductor region 118 will be discussed separately.

In an embodiment, blanket regions of material (i.e. regions 104 , 106 , 108 , etc.) are typically positioned on substrate 102 sequentially so that a plurality of EELs may be formed in an array. However, only one such device (i.e. EEL 100 ) is illustrated for simplicity and ease of discussion. Also, in an embodiment, regions 104 , 106 , 108 , etc. may be deposited using Molecular Beam Epitaxy, Metalorganic Chemical Vapor Deposition, or a similar technique well known by those skilled in the art.

In an embodiment, a ridge 101 is formed by etching through to conductive region 106 as shown. It will be understood that ridge 101 may be formed using techniques well known to those skilled in the art such as wet-etching, or dry-etching using inductance-coupled plasma (ICP) etching in an Ar/Cl 2 /BCl 3 gas mixture, or the like.

A lower ohmic contact 120 may be formed on the etched, exposed conductive region 106 of EEL 100 . An upper ohmic contact 122 may be formed on the conductive region 118 of EEL 100 . It will be understood that ohmic contact regions 120 and 122 may include gold (Au), titanium (Ti), platinum (Pt), palladium (Pd), gold-germanium (Au—Ge), nickel, (Ni), metal alloys, or the like.

Turn now to FIG. 2 which shows a sectional view of conductive region 106 , formed in accordance with an embodiment of the present invention. It will be understood that a similar discussion applies to conductive semiconductor region 118 . However, only conductive semiconductor region 106 is discussed for simplicity and ease of discussion. In an embodiment, conductive region 106 includes two InAlSb layers 202 and 204 , with thicknesses t 202 and t 204 , respectively, wherein the composition of the layers is chosen to be different, and the thickness and composition of each layer provides an average composition of conductive region 106 . In an embodiment, conductive region 106 has a single average composition. However, it will be understood that conductive region 106 may be formed using more than one region, each region having a different average composition, wherein the layer thicknesses and/or the layer compositions are varied.

It will also be understood that conductive region 106 may include more than two different layer types, wherein each layer type is periodically repeated through a superlattice. However, two layer types are illustrated for simplicity and ease of discussion. Conductive region 106 is typically between 0.5 and 10 μm thick, whereas the layer thicknesses t 202 and t 204 are typically of the order of several nanometers or tens of nanometers.

If conductive region 106 is grown as a bulk (random) alloy of an average composition, a poor carrier concentration, and hence inferior electrical properties, can be achieved, due to a high ionization energy for a dopant in the material. In an embodiment, the average composition of conductive region 106 is determined by the composition and the thickness of layers 202 and 204 . The composition of the layers 202 and 204 is chosen such that at least one of layer 202 and layer 204 may include highly doped semiconductor material with a conductivity type (i.e. n-type or p-type) to provide a lateral contact and current spreading.

In the case where both layer 202 and layer 204 include highly doped semiconductor, a higher vertical current flow may also be achieved than is the case for a bulk (random) alloy. In the case where only one of layer 202 and layer 204 include highly doped semiconductor, the thickness of the lower-doped layer is chosen to be sufficiently thin so as to allow tunneling of carriers from the highly doped layer, permitting a higher vertical current flow than can be achieved than is the case for a bulk (random) alloy.

It will be understood that the doping of each layer of a superlattice may be chosen to be different, so that a vertical current flow and a lateral current flow may be varied throughout conductive region 106 in order to provide a desired current flow. In an embodiment, by way of example, a configuration may include a region with a high lateral current flow (relative to a vertical current flow) in a region of conductive region 106 , and a high vertical current flow in another region of conductive region 106 . Further, layers of the superlattice may be coherently strained, which may also yield higher mobilities than for bulk semiconductor.

Further, it will also be understood that conductive regions 106 or 118 may include alternative conductive structures, such as tunnel junction structures. The formation and operation of tunnel junction structures is well known to those skilled and will not be elaborated upon further here.

Turn now to FIG. 3 which illustrates a plot of the log of the carrier concentration (N) as a function of temperature for Te-doped In x Al 1−x Sb (x=0.0725). It should be noted that Te incorporation in the InAlSb material system is used by way of example only and is not meant to limit the scope of the invention. The doping level achieved is 2×10 17 cm −3 and the activation (or ionization) energy is 22 meV, obtained from the slope of the characteristic Hall measurement curve. This is a relatively shallow energy level below the conduction band edge, allowing a sufficiently high free carrier concentration to be achieved.

Turn now to FIG. 4 which illustrates a plot of the log of the carrier concentration (N) as a function of temperature for Te-doped In x Al 1−x Sb (x=0.3). The doping level achieved is 4×10 15 cm −3 and the ionization energy is 126 meV. The high ionization energy causes fewer of the incorporated dopant atoms to be ionized, thus the resulting free carrier concentration is very low and is not suitable for producing high quality conductive layers.

Turn now to FIG. 5 which illustrates a plot of the log of the carrier concentration (N) as a function of temperature for Te-doped In x Al 1−x Sb (x=0.555). The doping level achieved is 1×10 17 cm −3 and the ionization energy is 31 meV. This ionization energy is sufficiently small such that a sufficiently high free carrier concentration may be achieved.

Turn now to FIG. 6 which illustrates a plot of the ionization energy for Te-doped In x Al 1−x Sb as a function of composition. For compositions with x greater than approximately 0.45 and x less than approximately 0.1, the ionization (or activation) energy is less than about 40 meV. For compositions with x in the range of approximately 0.1<x<0.45, the ionization energy is of the order of 100 meV, indicating around 1% ionization, i.e. only 1% of the incorporated dopant atoms contribute to free carriers. Thus it is difficult to produce conductive bulk layers of In x Al 1−-x Sb, for this composition range. An average composition of In x Al 1−x Sb in the range approximately (0.1<x<0.45) may also be achieved by growth as a digital alloy using layers of In x Al 1−x Sb with compositions in the ranges of approximately x<0.1 and x>0.45. Since a dopant may be incorporated in these compositional ranges to allow higher carrier concentrations, it is possible to achieve layers with an average composition in the range of approximately (0.1<x<0.45) with improved electrical properties, when grown as a digital alloy, when compared to a bulk layer of the same average composition.

Turn now to FIG. 7 , a plot of the logarithm of the carrier concentration as a function of inverse temperature for several compositions of Te-doped In x Al 1−x Sb. For the compositions x=7%, x=11% and x=45%, the carrier concentrations are higher and the characteristic slopes are shallower than for x=21% and x=31%, indicating low activation energies and a relatively shallow donor for these compositions. A transition occurs between approximately 38% and 45% Indium content that causes the donors to become predominantly shallow.

Turn now to FIG. 8 , a plot of room temperature-normalized carrier concentration as function of temperature for the same compositions of Te-doped In x Al 1−x Sb as shown in FIG. 7 . Smaller slopes indicate a low temperature dependence of carrier concentration as a function of temperature, which indicates a low activation energy and hence a relatively shallow donor. For the compositions where x=0.07 (7%) and x=0.45 (45%), the slope of the characteristic curves is small, whereas for the compositions x=0.11 (11%), x=0.21 (21%), and x=0.31 (31%), the characteristic curves have a steep slope, indicating a high activation energy for a deep donor.

Thus semiconductor devices with improved conductive regions have been disclosed. In the case of an EEL, improved vertical current flow is achieved. The conductive region includes digital alloy superlattice structures which allow higher doping levels to be achieved than for a bulk (random) alloy with the same average composition. Furthermore, the superlattice structures improve the resistivity of the region, improving the current spreading of the region, and hence the electronic properties of optoelectronic devices.

Using Te-doped In x Al 1−x Sb in an embodiment, the ionization energy for free carriers for compositions approximately in the range 0.1<x<0.45 is of the order of 100 meV. This implies that only 1% of the incorporated dopants are electrically active and provide free carriers. For the compositions in the ranges approximately x<0.1 and x>0.45, however, the ionization energy is significantly lower, therefore resulting in higher free carrier concentrations, usable in optoelectronic and electronic devices.

To overcome the limitation of bulk In x Al 1−x Sb layers with compositions 0.1<x<0.45, in an embodiment an improved conductive region is formed by growing a digital alloy superlattice, where the thickness and compositions of the superlattice layers are chosen to provide the desired average compositions of the bulk alloy, and wherein at least one of the components of the superlattice has a low ionization energy such that high doping of that layer type may be achieved. Consequently, the conductivity of the superlattice conductive region is higher than that for a bulk alloy with the same average composition.

Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiments shown. This application is intended to cover any adaptations or variations of embodiments of the present invention. It is to be understood that the above description is intended to be illustrative, and not restrictive, and that the phraseology or terminology employed herein is for the purpose of description and not of limitation. Combinations of the above embodiments and other embodiments will be apparent to those of skill in the art upon studying the above description. The scope of the present invention includes any other applications in which embodiment of the above structures and fabrication methods are used. The scope of the embodiments of the present invention should be determined with reference to claims associated with these embodiments, along with the full scope of equivalents to which such claims are entitled.