Low distortion amplifier

This application claims the benefit of U.S. Provisional Application No. 60/577,974, filed Jun. 8, 2004, the disclosure of which is hereby incorporated by reference.

1. Field of the Invention

The present invention relates to electronics. More specifically, the present invention relates to amplifiers.

2. Description of the Related Art

High dynamic range, low distortion, wideband amplifiers (or gain blocks) are used in a myriad of applications such as communications, high quality audio and video, electronic warfare, and radar systems. Many of these applications require amplifiers having very high performance (low distortion), wide bandwidth, and low power dissipation.

Modem communications systems, with the advent of high speed, low distortion analog to digital converters, tend to sample at IF (intermediate frequency) or RF (radio frequency). This allows all subsequent processing (demodulation, filtering, etc.) to be performed in the digital domain. As the ratio of information bandwidth to carrier frequency increases, it becomes increasingly difficult to maintain the linearity required. In particular, conventional amplifiers do not meet the linearity requirements for these types of applications.

The high power dissipation characteristics of conventional amplifiers require the circuit designer to increase system power or narrow the information bandwidth of each channel, thereby requiring more channels to be used, to meet systems linearity requirements.

Hence, there is a need in the art for an improved wideband amplifier offering lower distortion and lower power dissipation than prior art approaches.

The need in the art is addressed by the low distortion amplifier of the present invention. The novel amplifier includes a first transistor Q 1 having first and second output terminals and an input terminal adapted to receive an input signal, and a second transistor Q 2 having first and second output terminals and an input terminal adapted to receive a signal from the first output terminal of Q 1 , wherein the second output terminal of Q 1 is connected to the second output terminal of Q 2 in order to eliminate a nonlinear current component in Q 2 . In an illustrative embodiment, the amplifier also includes a cascode Darlington pair Q 3 , Q 4 for holding the second output terminals of Q 1 and Q 2 at a desired voltage to further reduce distortion and to maintain a wide bandwidth. In one embodiment, the amplifier also includes a first feedback loop with an operational amplifier to minimize the amplifier's overall distortion products, and a second feedback loop to set the input and output impedances of the amplifier.

FIG. 1 is a simplified schematic of a conventional amplifier having low input and output impedances.

FIG. 2 is a simplified schematic of a conventional high input impedance, low distortion amplifier.

FIG. 3 is a simplified schematic of a low impedance, low distortion amplifier that combines the approaches of the previous two circuits.

FIG. 4 is a simplified schematic of a conventional amplifier showing the current flows in the circuit.

FIG. 5 is a simplified schematic of an illustrative amplifier designed in accordance with the teachings of the present invention.

FIG. 6 is a simplified schematic of a low input/output impedance, low distortion RF amplifier designed in accordance with the teachings of the present invention.

FIG. 7 is a simplified schematic of an amplifier with a differential configuration designed in accordance with the teachings of the present invention.

FIG. 8 is a simplified schematic of an amplifier with a differential configuration designed in accordance with the teachings of the present invention.

Illustrative embodiments and exemplary applications will now be described with reference to the accompanying drawings to disclose the advantageous teachings of the present invention.

While the present invention is described herein with reference to illustrative embodiments for particular applications, it should be understood that the invention is not limited thereto. Those having ordinary skill in the art and access to the teachings provided herein will recognize additional modifications, applications, and embodiments within the scope thereof and additional fields in which the present invention would be of significant utility.

FIG. 1 is a simplified schematic of a conventional amplifier 10 having low input and output impedances. The amplifier 10 includes a Darlington pair comprised of two transistors Q 1 and Q 2 . An input voltage V IN is applied to an input terminal 12 connected to the base of Q 1 . An output voltage V OUT is taken at an output terminal 14 connected to the collector of Q 2 . The emitter of Q 2 is connected to ground through a resistor R 1 , and the collector of Q 2 is connected to a supply voltage V CC through a resistor R 2 . The emitter of Q 1 is connected to the base of Q 2 and to ground through a resistor R 4 . The collector of Q 1 is connected to V CC . The input terminal 12 is connected to the output terminal 14 by a resistor R 3 .

IF and RF systems typically require matched impedances (50 ohm). The prior art amplifier implementation of FIG. 1 can be designed to have low (50 ohm) input and output impedances, but exhibits high distortion. The distortion can be reduced by increasing the current in Q 2 , but this approach leads to high power dissipation. For reasonable power levels, the third order output intercept (OIP3) tends to be low (<30 dB).

A second prior art implementation is shown in FIG. 2 . FIG. 2 is a simplified schematic of a conventional high input impedance, low distortion amplifier 20 . The amplifier 20 includes a Darlington pair comprised of two transistors Q 1 and Q 2 , plus an operational amplifier (op amp) 16 having gain A. The input voltage V IN is applied to an input terminal 12 connected to the positive input terminal of the op amp 16 . The output of the op amp 16 is connected to the base of Q 1 . The emitter of Q 1 is connected to the base of Q 2 and to a current source 18 . The collector of Q 1 is connected to V CC . The emitter of Q 2 is connected to the negative input terminal of the op amp 16 and to ground through a resistor R 1 . The collector of Q 2 is connected to V CC through a resistor R 2 . The output voltage V OUT is taken at an output terminal 14 connected to the collector of Q 2 .

This circuit has a high input impedance and the distortion is reduced by the loop gain of the op amp 16 . While this circuit can provide reasonable OIP3 for reasonable power dissipation, it is not suitable for use in a 50 ohm system.

FIG. 3 is a simplified schematic of a low impedance, low distortion amplifier 30 that combines the approaches of the previous two circuits. The amplifier 30 includes a Darlington pair comprised of two transistors Q 1 and Q 2 , plus an op amp 16 . The input voltage V IN is applied to an input terminal 12 connected to the positive input terminal of the op amp 16 . The output of the op amp 16 is connected to the base of Q 1 . The emitter of Q 1 is connected to the base of Q 2 and to a current source 18 . The collector of Q 1 is connected to V CC . The emitter of Q 2 is connected to the negative input terminal of the op amp 16 and to ground through a resistor R 1 . The collector of Q 2 is connected to V CC through a resistor R 2 . The output voltage V OUT is taken at an output terminal 14 connected to the collector of Q 2 . The input terminal 12 is connected to the output terminal 14 by a capacitor C connected in series with a resistor R 3 .

In this approach, the input and output impedances can be set to equal 50 ohms, thereby allowing this circuit to be used in a 50 ohm system. The OIP3 is still reasonable as is the power level. Unfortunately the OIP3 is, in general, below +40 dBm in this circuit configuration as a result of the nonlinear base current contribution in Q 2 . FIG. 4 illustrates why the distortion is still higher than desired even though the gain A of the op amp 16 might be large.

FIG. 4 is a simplified schematic of a conventional amplifier 20 showing the current flows in the circuit. The current provided by the current source 18 is labeled I 1 . The current going into the collector of Q 1 is labeled I 2 . The current flowing out of the emitter of Q 2 through R 1 is labeled I 3 . The current going into the collector of Q 2 through R 2 is labeled I 4 . The current flowing into the base of Q 2 is labeled I 5 . The voltage at the emitter of Q 2 is labeled V F .

The voltage V F is almost a perfect (linear) representation of the input voltage V IN if the gain A of the op amp 16 is large. Therefore, I 3 is also a perfect (linear) representation of the input. The problem arises in that I 4 , which is the current that sets the output V OUT , is shown to be: I 4 =I 3 −I 5 . Now, I 5 has a component that is not a linear function of the input voltage V IN . This nonlinearity is due in part to the Early effect which cannot be eliminated in this circuit configuration. The Early effect results in a nonlinear base current. Also, the current gain of the transistor Q 2 is a non-linear function of the signal current in Q 2 . This results in a second source of non-linear base signal current in Q 2 . Since I 5 varies in a nonlinear fashion, so will I 4 since it has I 5 as a component. This results in distortion in the output V OUT .

The present invention eliminates this problem by using a novel method to cancel the nonlinear base currents that exist in the output Darlington pair. The novel current routing for the Darlington pair is shown in FIG. 5 .

FIG. 5 is a simplified schematic of an illustrative amplifier 40 designed in accordance with the teachings of the present invention. The amplifier 40 includes a Darlington pair comprised of two transistors Q 1 and Q 2 . The input voltage V IN is applied to an input terminal 12 connected to the base of Q 1 . The emitter of Q 1 is connected to the base of Q 2 and to a current source 18 . The emitter of Q 2 is connected to ground through a resistor R 1 . The collector of Q 2 is connected to V CC through a resistor R 2 . The output voltage V OUT is taken at an output terminal 14 connected to the collector of Q 2 . In accordance with the teachings of the present invention, the collector of Q 1 is connected to the collector of Q 2 , instead of to V CC as in conventional approaches.

The current provided by the current source 18 is labeled I 1 . The current going into the collector of Q 1 is labeled I 2 . The current flowing out of the emitter of Q 2 through R 1 is labeled I 3 . The current flowing through R 2 is labeled I 4 . The current flowing into the base of Q 2 is labeled I 5 . The voltage at the emitter of Q 2 is labeled V F .

By tying the collector of Q 1 to the output, the current I 4 is equal to: I 4 =I 3 −I 5 +I 2 . The current I 2 is given by: I 2 =I 1 +I 5 . Substituting for I 2 in the equation for I 4 results in: I 4 =I 3 −I 5 +I 1 +I 5 , or I 4 =I 3 +I 1 . The nonlinear current I 5 has been cancelled out and replaced with I 1 which is a constant. This allows the amplifier to have a much higher OIP3 than conventional amplifier implementations. In this configuration, the nonlinear base current error in Q 2 is circulated and is now replaced by the nonlinear base current error in Q 1 in response to Q 2 's nonlinear base current. Therefore, the original error in Q 2 is reduced by a factor of β, which is 80 to 100.

This approach can be used in a dual loop configuration to create a 50 ohm wideband amplifier that exhibits extremely low distortion products (OIP3 greater that +50 dBm) at DC power levels less than 0.5 watts.

FIG. 6 is a simplified schematic of a low input/output impedance, low distortion RF amplifier 50 designed in accordance with the teachings of the present invention. The amplifier 50 includes a Darlington pair comprised of two transistors Q 1 and Q 2 , and an op amp 16 . The input voltage V IN is applied to an input terminal 12 connected to the positive input terminal of the op amp 16 . The output of the op amp 16 is connected to the base of Q 1 . The emitter of Q 1 is connected to the base of Q 2 and to a current source 18 that provides a current I 1 . The emitter of Q 2 is connected to the negative input terminal of the op amp 16 and to ground through a resistor R 1 . As described above, the collector of Q 1 is connected to the collector of Q 2 to eliminate the nonlinear component of Q 2 's base current.

In accordance with the teachings of the present invention, the amplifier 50 also includes a cascode Darlington pair comprised of two transistors Q 3 and Q 4 , added between the collectors of Q 1 and Q 2 , and the output terminal 14 . The base of Q 3 is connected to a reference voltage V REF , and the emitter of Q 3 is connected to the base of Q 4 and to a current source 42 that provides a current I 2 . The emitter of Q 4 is connected to the collectors of Q 1 and Q 2 , and the collector of Q 4 is connected to V CC through a resistor R 2 . The collector of Q 3 is connected to the collector of Q 4 . Thus, the cascode pair Q 3 , Q 4 utilizes the same configuration previously described to eliminate the variable component of Q 4 's base current. The output voltage V OUT is taken at the output terminal 14 connected to the collectors of Q 3 and Q 4 , and the input terminal 12 is connected to the output terminal 14 by a capacitor C connected in series with a resistor R 3 .

The cascode provides additional benefits to the circuit. First, it reduces the distortion due to the Early effect by holding the collectors of Q 1 and Q 2 at a constant voltage (V REF -V BEQ3 -V BEQ4 , where V BEQ3 is the base to emitter voltage of Q 3 and V BEQ4 is the base to emitter voltage of Q 4 ). It also improves the frequency response of the circuit by providing a low impedance at the collectors of Q 1 and Q 2 . It therefore allows Q 1 and Q 2 to be implemented with transistors that have a very high transition frequency f t . In silicon bipolar and silicon germanium technology, devices with high f t have low breakdown voltages. Since V OUT will swing over a 4 volt range, the transistors attached to V OUT must have high breakdown. By using Q 3 and Q 4 in a common base configuration (the effective f t of this configuration is very high), Q 3 and Q 4 can be implemented using devices that have a higher breakdown voltage than Q 1 and Q 2 at the expense of f t . However, since Q 3 and Q 4 are configured as a current amplifier, the effective bandwidth of the cascode is close to the f t of the high breakdown device, which is sufficient. This circuit approach allows the transistors in the signal path at the input stage to be low breakdown, high f t devices. The output, which requires a high voltage swing, can utilize high breakdown, low f t devices to handle the voltage swing while continuing to maintain a wide bandwidth. If additional headroom is required (to achieve a 4 volt swing on the output) a choke can be substituted for R 2 .

Illustrative values for the components of the amplifier 50 of FIG. 6 are shown in the following table:

Thus, the novel amplifier 50 of the present invention utilizes a configuration that employs two separate feedback loops. One loop is used to set the input impedance and output impedance of the amplifier, and a second independent loop is used to minimize the amplifier's overall distortion products. A novel Darlington pair configuration is used to eliminate distortion arising from the nonlinear base current. In addition, a cascode Darlington pair is added to further reduce distortion and to maintain a wide bandwidth.

This topology allows higher OIP3 (10× improvement) at lower DC power (2-5×) at lower supply voltages (2-3×) over existing products on the market. The amplifier can be configured for standard 50 ohm input and 50 ohm output, 20 dB gain, a third order output intercept greater than +50 dBm, and power dissipation less than 0.5 watts. Prior art amplifiers with similar bandwidth (10 MHz-3 GHz), gain, and pulse performance tend to have third order output intercepts less than +37 dBm at similar power levels as the described invention. The circuit can also perform with a power supply voltage of +5V where prior art amplifiers that operate with +5 V supplies have been limited to +40 dBm third order OIP3 performance.

Because of this amplifier's excellent linearity, it can be used in applications where direct sampling of IF or RF waveforms is desired. The low power requirements of the amplifier allow it to be used in multi-channel applications as well as applications where low power, low distortion and small size are important parameters.

The teachings of the present invention can also be applied to a differential configuration. FIG. 7 is a simplified schematic of an amplifier 60 with a differential configuration designed in accordance with the teachings of the present invention. The amplifier 60 employs a phase splitter 62 , which receives an input signal V IN and provides two output signals differing in phase by 180°. The first output of the phase splitter is amplified by an amplifier 50 A to generate an output signal V OUT , and the second output of the phase splitter is amplified by an amplifier 50 B to generate a signal −V OUT . The amplifiers 50 A and 50 B are each implemented using the configuration of FIG. 6 .

FIG. 8 is a simplified schematic of an amplifier 60 ′ with a differential configuration designed in accordance with the teachings of the present invention. FIG. 8 shows one possible implementation of a phase splitter 62 ′. The phase splitter 62 ′ includes a transformer 64 connected in parallel to a capacitor C P and a resistor R P in series.

A differential configuration increases the OIP3 by 6 dB over the single ended performance (to +56 dBm) while increasing the power only by a factor of two. The performance potential of this configuration represents a significant improvement over commercially available devices currently advertised in the marketplace.

Thus, the present invention has been described herein with reference to a particular embodiment for a particular application. Those having ordinary skill in the art and access to the present teachings will recognize additional modifications, applications and embodiments within the scope thereof. For example, while the illustrative embodiments have been described using NPN bipolar transistors, other process technologies may be used without departing from the scope of the present teachings.

It is therefore intended by the appended claims to cover any and all such applications, modifications and embodiments within the scope of the present invention.

Accordingly,