Voltage comparator circuit

The present invention relates to a differential amplifier and a voltage comparator circuit using the same, especially to a voltage comparator circuit suitable for a high-speed differential interface circuit.

In recent years, high-speed differential interface circuits are used in various types of devices. For instance, in the field of TFT_LCD (Thin Film Transistor Liquid Crystal Display), as interfaces between LCD driver LSI and timing controller LSI, RSDS (Reduced Swing Differential Signaling: a registered trademark of National Semiconductor Corporation) and mini-LVDS (mini Low Voltage Differential Signaling: a registered trademark of Texas Instruments, Inc.) are becoming standardized. The voltage comparator circuits with differential inputs are used in the receiver circuits of these technologies.

The frequencies of the differential signal inputted into the voltage comparator circuits are approximately 85 MHz and 200 MHz in the cases of RSDS and mini-LVDS respectively. The input differential voltages of the differential signal component and in-phase signal component are ±50 mV and approximately 0.3V to VDD-0.5V respectively.

A circuit that meets these specifications, as the characteristics required for a voltage comparator circuit, is demanded. However, with the circuit configuration currently available, it is difficult to meet the standards of the in-phase signal component and have a satisfying operation speed simultaneously.

FIG. 6 shows the configuration of a differential amplifier circuit described in Non-Patent Document 1 (IEEE J. Solid-State Circuits. vol. 29 No. 12. December 1994, pp. 1505 to 1513 “A Compact Power-Efficient 3V CMOS Rail-to-Rail Input/Output Operational Amplifier for VLSI Cell Libraries”).

In reference to FIG. 6 , this differential amplifier comprises a differential amplifier circuit, comprising a first differential pair of a first P-channel MOS transistor MP 1 and a second P-channel MOS transistor MP 2 and a second differential pair of a first N-channel MOS transistor MN 1 and a second N-channel MOS transistor MN 2 , a third and fourth N-channel MOS transistors MN 3 and MN 4 , connected to a first voltage source V 1 , wherein their respective gates are connected in common, a third and fourth P-channel MOS transistors MP 3 and MP 4 wherein their respective gates and sources are connected in common, a fifth and sixth P-channel MOS transistors MP 5 and MP 6 , connected to a second voltage source V 2 , wherein their respective gates are connected in common, a first constant current source (supplying a current I 1 ) connected between a source connected in common to the first differential pair (MP 1 and MP 2 ) and a positive power source VDD, a second constant current source (supplying a current I 2 ) connected between a source connected in common to the second differential pair (MN 1 and MN 2 ) and a negative power source, a third constant current source (supplying a current I 3 ) connected between the source of the third N-channel MOS transistor MN 3 and the negative power source, and a fourth constant current source (supplying a current I 4 ) connected between the source of the fourth N-channel MOS transistor MN 4 and the negative power source.

The drains of the first and second P-channel MOS transistors MP 1 and MP 2 , which constitute the first differential pair, are connected to the sources of the third and fourth N-channel MOS transistors MN 3 and MN 4 respectively.

The drain of the first N-channel MOS transistor MN 1 , which constitutes the second differential pair, the drain of the third P-channel MOS transistor MP 3 , and the source of the fifth P-channel MOS transistor MP 5 are connected in common, and the drain of the second N-channel MOS transistor MN 2 , which constitutes the second differential pair, the drain of the fourth P-channel MOS transistor MP 4 , and the source of the sixth P-channel MOS transistor MP 6 are connected in common.

The gate of the third P-channel MOS transistor MP 3 , the drain of the fifth P-channel MOS transistor MP 5 , and the drain of the third N-channel MOS transistor MN 3 are connected in common.

The gate of the first N-channel MOS transistor MN 1 and the gate of the first P-channel MOS transistor MP 1 are connected in common to a noninverting input terminal, and the gate of the second N-channel MOS transistor MN 2 and the gate of the second P-channel MOS transistor MP 2 are connected in common to an inverting input terminal.

The drain of the sixth P-channel MOS transistor MP 6 and the drain of the fourth N-channel MOS transistor MN 4 are connected in common to an output terminal.

Voltage comparator circuit is an application of differential amplifier, and the conventional differential amplifier shown in FIG. 6 can be used as a voltage comparator circuit. However, when the differential amplifier shown in FIG. 6 is practically used as a voltage comparator circuit, waveform shaping is necessary.

For the purpose of waveform shaping, CMOS inverters must be connected after this differential amplifier circuit.

FIG. 9 shows a concrete configuration of the above idea. In reference to FIG. 9 , the input terminal of a first CMOS inverter INV 1 is connected to the output of the differential amplifier. After the first CMOS inverter INV 1 , second and third CMOS inverters INV 2 and INV 3 are connected in series for the purpose of further waveform shaping, and the output of the third CMOS inverter INV 3 becomes the final output.

FIG. 10 is a drawing showing a concrete example of the circuit configuration of the CMOS inverter shown in FIG. 9 . In reference to FIG. 10 , the CMOS inverter comprises a P-channel MOS transistor MP 1 whose source is connected to a positive power source VDD, an N-channel MOS transistor MN 1 whose drain is connected to the drain of the P-channel MOS transistor MP 1 and to an output terminal, and source is connected to a negative power source VSS (GND), and the gates of the P-channel MOS transistor MP 1 and the N-channel MOS transistor MN 1 are connected in common and connected to an input terminal.

Hereinafter, the use of this differential amplifier as a voltage comparator circuit will be analyzed. First, the basic operation of a differential amplifier comprised of MOS transistors is explained with reference to FIGS. 7 and 8 . FIG. 7 shows a basic circuit configuration of a differential amplifier circuit, and FIG. 8 shows the direct current transmission characteristics of its input voltage/output current. The sources of N-channel MOS transistors MN 1 and MN 2 are connected in common, and a constant current source Iss is connected between these sources connected in common and a negative power source. Further, a voltage source V i1 is connected to the gate of the MN 1 , and a voltage source V i2 is connected to the gate of the MN 2 . The following Equation (1) holds because of the relationship of the input voltage, where the gate-source voltages of the MN 1 and MN 2 are V GS1 and V GS2 respectively.

V i1 −V GS1 +V GS2 −V i2 =0  (1)

Furthermore, where the drain currents are I d1 and l d2 respectively, the gate width and length are W and L respectively, the mobility is μ, the gate oxide film capacity per unit area is C o , and the threshold value is V t , the transconductance β (refer to the following Equation (2)), V GS1 and V GS2 (the gate-source voltages of the MOS transistors MN 1 and MN 2 ) are given by the following Equations (3) and (4).

Here, a differential voltage ΔV id with which the bias current I ss is completely switched to the transistor MN 1 is calculated from Equations (1), (3), and (4) as in the following Equation (5).

Further, where V GS0 is the gate-source voltage V GS when V i1 =V i2 , the drain currents of the MN 1 and MN 2 become I ss /2 respectively and the following Equation (6) is obtained.

Therefore, the following Equation (7) is given from Equations (5) and (6).

Δ V id =√{square root over (2)}( V GS0 −V T )  (7)

This Equation (7) is a conditional equation for when the MOS differential stage is completely switched. As described above, when the input differential voltage is higher than the value represented by Equation (7), the bias current source of the differential stage flows in one of the transistors and the current of the other transistor becomes zero. This provides a comparator operation.

However, even if it is not switched completely as described above, depending on the structure of a stage after this differential stage, a comparator operation can be obtained with a lower differential voltage than this. It is because this differential stage has enough gain. FIG. 8 shows a relation graph between the input voltage and the drain current, which constitutes the differential stage.

A detailed explanation on the differential amplifier shown in FIG. 6 will be given. The differential amplifier shown in FIG. 6 is a so-called folded cascode-type differential amplifier circuit.

This circuit has the following three operation modes, depending on the input voltage range.

[1]<When Both the First and Second Differential Pairs are Operating>

Where V in is the input voltage

V DD −( V GS(MP1/2) +V DS(sat)(I1) )> V in >V GS(MP1/2) +V DS(sat)(I2)   (8)

and where

V GS(MN1/2) : the gate-source voltages of the N-channel MOS transistors MN 1 / 2 ,

V DS(sat)(I2) : the drain-source voltage of the N-channel MOS transistor, which constitutes the current source I 2 , at the saturation point (a minimum voltage needed for the operation in the pentode region),

V GS(MP1/2) : the gate-source voltages of the P-channel MOS transistors MP 1 / 2 , and

V DS(sat)(I1) : the drain-source voltage of the P-channel MOS transistor, which constitutes a current source I 1 , at the saturation point (a minimum voltage needed for the operation in the pentode region),

and when the above conditions are met, both the first and second differential pairs are in an operating mode.

Assuming a voltage higher than Equation (7) is inputted and it is higher on the side of In + than that of In − , this circuit operates as a voltage comparator circuit, therefore, all the bias current of the first differential pair (MP 1 and MP 2 ) I 1 flows to the second P-channel MOS transistor MP 2 , and the current of the first P-channel MOS transistor MP 1 becomes zero. On the other hand, all the bias current of the second differential pair (MN 1 and MN 2 ) I 2 flows to the first N-channel MOS transistor MN 1 and the current of the second N-channel MOS transistor MN 2 becomes zero. Looking at the bias current condition of each transistor at this time, the following Equations (9) and (10) hold where ID (MN3) is the drain current of the third N-channel MOS transistor MN 3 , and ID (MN4) is the drain current of the fourth N-channel MOS transistor MN 4 :

I D(MN4) =I 4 −I 1   (9)

I D(MN3) =I 3   (10)

Here, the relationship of I 1 , I 3 , and I 4 is as follows:

I 3 =I 4 ≧I 1   (11)

On the other hand, the fifth P-channel MOS transistor MP 5 's drain current I D(MP5) is the same as the third N-channel MOS transistor MN 3 's drain current ID (MN3) , therefore the following Equation (12) holds:

I D(MP5) =I D(MN3)   (12)

Furthermore, the third P-channel MOS transistor MP 3 's drain current I D(MP3) is obtained by adding the fifth P-channel MOS transistor MP 5 's drain current I D(MP5) and the first N-channel MOS transistor MN 1 's drain current I D(MN1)

I D(MP5) =I 3 ,

I D(MN1) =I 2 ,

therefore, the following Equation (13) holds:

I D(MP3) =I D(MP5) +I D(MN1) =I 3 +I 2   (13)

Since the respective gates and sources of the fourth P-channel MOS transistor MP 4 and the third P-channel MOS transistor MP 3 are connected in common, their drain currents are equal. Therefore, the fourth P-channel MOS transistor MP 4 's drain current I D(MP4) is given by the following Equation (14):

I D(MP4) =I D(MP3) =I 3 +I 2   (14)

Further, the value of the sixth P-channel MOS transistor MP 6 's drain current I D(MP6) is obtained by subtracting the second N-channel MOS transistor MN 2 's drain current I D(MN2) from the fourth P-channel MOS transistor MP 4 's drain current I D(MP4) , and since I D(MN2) is zero in this condition, I D(MP6) is given by the following Equation (15):

I D(MP6) =I D(MP4) −I D(MN2) =I 3 +I 2   (15)

Since the drain of the sixth P-channel MOS transistor MP 6 and the drain of the fourth N-channel MOS transistor MN 4 are connected in common to the output terminal, the output current is the subtraction of Equation (9) from Equation (15) described above (I D(MP6) −I D(MN4) ). In other words, the output terminal goes to a high level, and the current discharge capability I out is given by the following Equation (16):

I out =( I 3 +I 2 )−( I 4 −I 1 )  (16)

Here, I 3 =I 4 , and as a result, the output end current I out has the current discharge capability of

I out =I 1 +I 2   (17)

and it goes to a high level. Potentially it is a VDD, a nearly positive power source.

Next, assuming a voltage higher than Equation (7) is inputted and it is lower on the side of In + than that of In − , the present circuit operates as a comparator circuit, therefore, all the bias current of the first differential pair I 1 flows to the first P-channel MOS transistor MP 1 , and the current of the second P-channel MOS transistor MP 2 becomes zero. On the other hand, all the bias current of the second differential pair I 2 flows to the second N-channel MOS transistor MN 2 and the current of the first N-channel MOS transistor MN 2 becomes zero. The bias current condition of each transistor at this time can be given by the following Equations (18) and (19) where I D(MN3) is the drain current of the third N-channel MOS transistor MN 3 , and I D(MN4) is the drain current of the fourth N-channel MOS transistor MN 4 :

I D(MN4) =I 4   (18)

I D(MN3) =I 3 −I 1   (19)

On the other hand, the fifth P-channel MOS transistor MP 5 's drain current I D(MP5) is the same as the third N-channel MOS transistor MN 3 's drain current I D(MN3) , therefore it is given by the following Equation (20):

I D(MP5) =I D(MN3)   (20)

Furthermore, the third P-channel MOS transistor MP 3 's drain current I D(MP3) is obtained by adding the fifth P-channel MOS transistor MP 5 's drain current I D(MP5) and the first N-channel MOS transistor MN 1 's drain current I D(MN1) , and in this condition, I D(MP5) =I 3 , I D(MN1) =0, therefore, the following Equation (21) holds:

I D(MP3) =I D(MP5) +I D(MN1) =I 3 −I 1   (21)

Since the respective gates and sources of the fourth P-channel MOS transistor MP 4 and the third P-channel MOS transistor MP 3 are connected in common, their drain currents are equal. Therefore, the fourth P-channel MOS transistor MP 4 's drain current I D(MP4) is given by the following Equation (22):

I D(MP4) =I D(MP3) =I 3 −I 1   (22)

Further, the value of the sixth P-channel MOS transistor MP 6 's drain current I D(MP6) is obtained by subtracting the second N-channel MOS transistor MN 2 's drain current I D(MN2) from the fourth P-channel MOS transistor MP 4 's drain current I D(MP4) , and since I D(MN2) =I 2 in this condition, I D(MP6) is given by the following Equation (23):

I D(MP6) =I D(MP4) −I D(MN2) =I 3 −I 1 −I 2   (23)

Similarly, the output current is the subtraction between the current values shown in Equation (18) and Equation (23). In other words, the output end current I out is given by the following Equation (24) where the current discharged from the output end is positive:

I out =I 4 −( I 3 −I 1 −I 2 )  (24)

Here, I 3 =I 4 , and as a result, the output end current I out has a current absorption capability of

I out =I 1 +I 2   (25)

and it goes to a low level. Potentially it becomes 0V, nearly a negative power source (GND).

[2]<When Only the First Differential Pair is Operating>

As opposed to the case in [1], when the input voltage Vin in this case is

0 <V in <V GS(MN1/2) +V DS(sat)(I2)   (26)

only the first differential stage operates. It is because the drain-source voltage of the MOS transistor, which functions as the constant current source that constitutes I 2 , becomes unavailable, therefore, I 2 =0. As a result, the second differential stage stops operating. A detailed analysis method is omitted here, but if the drive current at the output terminal (OUT) is analyzed as in the case of [1], both the discharge current and absorption current are given by the following Equation (27):

I out =I 1   (27)

[3]<When Only the Second Differential Pair is Operating>

As opposed to the case in [1], when the input voltage Vin in this case is

V DD >V in >V DD −( V GS(MP1/2) +V DS(sat)(I1) )  (29)

only the second differential stage operates. It is because the drain-source voltage of the MOS transistor, which functions as the constant current source that constitutes I 1 , becomes unavailable, therefore, I 1 =0. As a result, the first differential stage stops operating. A detailed analysis method is omitted here, but if the drive current at the output terminal (OUT) is analyzed as in the case of [1], both the discharge current and absorption current are given by the following Equation (29):

I out =I 2   (29)

As becomes clear from the above, the drive capability of the output directly depends on the bias current values of the differential input stage.

Therefore, the only way to increase drive capability is to increase the bias current of the differential stage. This drive current is used for charging/discharging the parasitic capacitance related to the output of the voltage comparator circuit. Therefore, the operation speed depends on this bias current.

As the input frequency increases, the output of the differential amplifier becomes closer to a sinusoidal wave.

Therefore, a CMOS inverter circuit for converting this output sine wave into a rectangular wave, i.e. wave shaping, is connected after this differential amplifier.

Since the threshold of the CMOS inverter is set to approximately VDD/2, the borderline is when the input waveform of the CMOS inverter crosses VDD/2. When the input waveform of the CMOS inverter is below it, the output goes to a high level (VDD), and when it is above it, the output goes to a low level (VSS (GND)). This is how wave shaping is performed. The reason why there are multiple stages of the CMOS inverters (three stages in this case) is because wave shaping cannot be completed by only one stage.

In Patent Document 1, a structure in which the in-phase input voltage range can be as wide as to be from power supply voltage to GND by synthesizing the outputs of a differential amplifier comprising a P-channel MOS transistor and a differential amplifier comprising a N-channel MOS transistor is disclosed.

[Non-Patent Document 1]

IEEE J. Solid-State Circuits. Vol. 29 No. 12. December 1994, pp. 1505-1513, “A Compact Power-Efficient 3V CMOS Rail-to-Rail Input/Output Operational Amplifier for VLSI Cell Libraries.”

[Patent Document 1]

Japanese Patent Kokai Publication No. JP-A-03-62712

The entire disclosure of these documents is incorporated herein by reference thereto.

As described above, in order to have the voltage comparator circuit using the differential amplifier shown in FIG. 7 achieve high-speed operation, the current values of the first through fourth current sources have to be high. As a result, the power consumption will be increased as well.

Also, since the waveform of the output terminal cannot be swung to the full voltage, the N-channel MOS transistor and P-channel MOS transistor of the inverter connected at a later stage of this voltage comparator circuit are turned on simultaneously and a through current flows, resulting in an increase in power consumption.

Further, when the output drive current is increased in order to have the differential amplifier shown in FIG. 7 achieve high-speed operation, since the drive currents are set at the first and second constant current source, their currents I 1 and I 2 need to be increased. As a result, the power consumption is increased. Further, one of the reasons why the output terminal waveform cannot be swung to the full voltage is because the transistors are vertically stacked.

The differential amplifier shown in FIG. 7 is put into the structure shown in FIG. 9 , and the output waveforms (simulation values) with an input differential signal frequency of 200 MHz, a differential amplitude of ±50 mV, and an in-phase signal voltage of 0.3V are shown in FIG. 11 .

As shown in FIG. 11 , even though the duty of the input differential signal is 50%, the duty of the final output waveform is far from it.

Therefore, there is much to be desired in the art in the light of the above problems i.e., to provide a differential amplifier, with a simple circuit configuration and high-speed operation ability, and a voltage comparator comprising the same.

According to specific features of the present invention, there are provided differential amplifiers and voltage comparators as follows:

A differential amplifier according to an aspect of the present invention comprises: an input differential stage having first and second differential pairs of first and second-conductive types, which are driven by first and second current sources, respectively, and to which a differential input signal is inputted; a folded cascode-type differential stage, which constitutes a load of differential outputs (pair) of the first and second differential pairs, and adds a differential output signal (pair) of the first differential pair and a differential output signal (pair) of the second differential pair, folds and outputs differentially the result; and first and second current mirror circuits of first and second-conductive types, which are disposed oppositely between first and second power sources, receive differential outputs (pair) of the folded cascode-type differential stage into their respective inputs, with their outputs connected in common to an output terminal.

The differential amplifier relating to the present invention can be structured such that the folded cascode-type differential stage includes at least first through third transistor pairs, whose control terminals (gates) are connected to each other, and two current sources between the first and second power sources. The first transistor pair connected to the side of the first power source and the second transistor pair constitute a cascode current mirror circuit. The differential outputs (pair) of the first differential pair are connected respectively to the connection points between the first transistor pair and second transistor pair. The differential outputs (pair) of the second differential pair are connected respectively to connection points between the other ends of the two current sources, whose one end is connected in common to the second power source, and the third transistor pair. One output of the second transistor pair is connected to an input end of the second current mirror circuit, and one output of the third transistor pair is connected to an input end of the first current mirror circuit.

A differential amplifier relating to another aspect of the present invention can be structured as follows. The folded cascode-type differential stage includes at least first through third transistor pairs, whose control terminals (gates) are connected to each other, and two current sources between the first and second power sources. The first transistor pair connected to the side of the second power source and the second transistor pair constitute a cascode current mirror circuit. The differential outputs (pair) of the first differential pair are connected respectively to the connection points between the other ends of the two current sources, whose one end is connected in common to the first power source, and the third transistor pair. The differential outputs (pair) of the second differential pair are connected respectively to the connection points between the first transistor pair and second transistor pair. One output of the second transistor pair is connected to the input end of the first current mirror circuit, and one output of the third transistor pair is connected to the input end of the second current mirror circuit.

A differential amplifier relating to a further aspect of the present invention can be structured as follows. The folded cascode-type differential stage comprises at least a third current mirror circuit, a first transistor pair, whose respective gates are connected to each other, and two current sources between the first and second power sources. The differential outputs (pair) of the first differential pair are connected to the input end of the third current mirror circuit and the input end of the first current mirror circuit respectively. The differential outputs (pair) of the second differential pair are connected to the first transistor pair and the connection points between the two current sources respectively. One output of the first transistor pair is connected to the input end of the second current mirror circuit, and the output of the third current mirror circuit is connected to the input end of the second current mirror circuit.

A voltage comparator relating to a further aspect of the present invention comprises a wave shaping circuit at the output stage of the differential amplifier described above. The wave shaping circuit is constituted by inverters or buffer circuits.

The meritorious effects of the present invention are summarized as follows.

According to the present invention, high-speed operation is achieved by a simple structure comprising an input differential stage, a folded cascode differential stage, and first and second current mirror circuits disposed oppositely between power sources.

According to the present invention, high-speed operation is made possible by having the first and second current mirror circuits with a current amplification function and increasing the driving ability as a result.

According to the present invention, a buffer circuit is provided after the output of the differential amplifier for the purpose of wave shaping, and the output of the buffer circuit becomes the output of the voltage comparator.

FIG. 1 is a drawing showing the circuit configuration of a differential amplifier of a first embodiment according to the present invention.

FIG. 2 is a drawing showing the circuit configuration of a differential amplifier of a second embodiment.

FIG. 3 is a drawing showing the circuit configuration of a differential amplifier of a third embodiment.

FIGS. 4A and 4B are drawings showing structural examples of the current mirror circuits shown in FIGS. 1 , 2 , and 3 .

FIG. 5 is a drawing showing simulated input/output waveforms of the present invention.

FIG. 6 is a drawing showing the circuit configuration of a conventional differential amplifier circuit.

FIG. 7 is a drawing showing the circuit configuration of a conventional differential amplifier stage.

FIG. 8 is a drawing showing the input/output characteristics of the differential amplifier stage shown in FIG. 7 .

FIG. 9 is a drawing showing an example of the conventional voltage comparator circuit.

FIG. 10 is a drawing of a concrete example of a CMOS inverter circuit.

FIG. 11 is a drawing showing simulated input/output waveforms of the conventional example.

Preferred embodiments of the present invention will be explained hereinafter with reference to drawings. The present invention comprises an input differential stage, which inputs a differential input signal and has a first and second differential pairs with reverse polarity to each other, a folded cascode-type differential stage, which is connected to the differential output of the input differential stage and adds a differential output signal of the first differential pair and a differential output signal of the second differential pair, a first and second current mirror circuits (CM 1 and CM 2 ) with reverse polarity to each other, which are disposed between the power supplies to face each other, receive the differential output of the folded cascode-type differential stage with their respective inputs, and whose outputs are connected in common to the output terminal. The folded cascode-type differential stage, which receives the output voltage (differential output) of the input differential stage and provides a folded current output, adds a differential output signal of the first differential pair and a differential output signal of the second differential pair, and the output of the folded cascode-type differential stage is folded and outputted from the output terminal by the first and second current mirror circuits. By having the first and second current mirror circuits with a current amplification function, the driving ability is increased and high-speed operation can be achieved. According to the present invention, multiple inverters (or buffer circuits) as a wave shaping circuit are provided after the output of the differential amplifier, and an output of the wave shaping circuit becomes a resultant output of the voltage comparator. A detailed explanation on the embodiments is given hereinafter.

Embodiment

FIG. 1 is a drawing showing an equivalent circuit of a differential amplifier of a first embodiment according to the present invention. It is a differential amplifier used in a voltage comparator circuit with a noninverting input and an inverting input. In reference to FIG. 1 , the differential amplifier of the first embodiment comprises a first differential pair of a first P-channel MOS transistor MP 1 and a second P-channel MOS transistor MP 2 with their sources connected in common, a second differential pair of a first N-channel MOS transistor MN 1 and a second N-channel MOS transistor MN 2 with their sources connected in common, third and fourth N-channel MOS transistors MN 3 and MN 4 with their gates connected in common to a first voltage source (V 1 ), third and fourth P-channel MOS transistors MP 3 and MP 4 with their gate connected in common and their sources connected in common to a positive power source (VDD), a fifth and sixth P-channel MOS transistors MP 5 and MP 6 with their gate connected in common to a second voltage source (V 2 ), a first current mirror circuit CM 1 with its input connected to the drain of the fourth N-channel MOS transistor MN 4 and its common terminal connected to the positive power source VDD, a second current mirror circuit CM 2 with its input connected to the drain of the sixth P-channel MOS transistor MP 6 and its common terminal connected to a negative power source terminal (GND), a first constant current source (I 1 ) connected between the commonly connected sources of the P-channel MOS transistors MP 1 and MP 2 , which constitute the first differential pair, and the positive power source VDD, a second constant current source (I 2 ) connected between the commonly connected sources of the N-channel MOS transistors MN 1 and MN 2 , which constitute the second differential pair, and the negative power source (GND), a third constant current source (I 3 ) connected between the source of the third N-channel MOS transistor MN 3 and the negative power source (GND), and a fourth constant current source (I 4 ) connected between the source of the fourth N-channel MOS transistor MN 4 and the negative power source (GND).

The drain of the first P-channel MOS transistor MP 1 , which constitutes the first differential pair, is connected to the source of the third N-channel MOS transistor MN 3 , and the drain of the second P-channel MOS transistor MP 2 , which constitutes the first differential pair, is connected to the source of the fourth N-channel MOS transistor MN 4 .

The drain of the first N-channel MOS transistor MN 1 , which constitutes the second differential pair, the drain of the third P-channel MOS transistor MP 3 , and the source of the fifth P-channel MOS transistor MP 5 are connected in common. The drain of the second N-channel MOS transistor MN 2 , which constitutes the second differential pair, the drain of the fourth P-channel MOS transistor MP 4 , and the source of the sixth P-channel MOS transistor MP 6 are connected in common, the gate of the third P-channel MOS transistor MP 3 , the drain of the fifth P-channel MOS transistor MP 5 , and the drain of the third N-channel MOS transistor MN 3 are connected in common. The output of the first current mirror circuit CM 1 and the output of the second current mirror circuit CM 2 are connected in common to an output terminal OUT. The gate of the first P-channel MOS transistor MP 1 and the gate of the first N-channel MOS transistor MN 1 are connected in common to an inverting input terminal In − . The gate of the second P-channel MOS transistor MP 2 and the gate of the second N-channel MOS transistor MN 2 are connected in common to an noninverting input terminal In + . CMOS inverter circuits (not shown in the drawing) connected in multiple stages to the output OUT of the differential amplifier circuit are connected, and the output of a final stage CMOS inverter becomes the final output of the voltage comparator circuit. Here, the first and second current mirror circuits CM 1 and CM 2 have an input to output current ratio of 1:k (k>1).

Concrete examples of the configuration of the current mirror circuit will be described. FIGS. 4A and 4B show structural examples of the first current mirror circuit CM 1 (current discharge type) and the second current mirror circuit CM 2 (current absorption type) shown in FIG. 1 . In reference to FIG. 4A , the first current mirror circuit CM 1 shown in FIG. 1 is constituted by two P-channel MOS transistors MP 1 and MP 2 , and their respective sources and gates are connected in common. The gate and drain of the P-channel MOS transistor MP 1 are connected in common to an input terminal of the current mirror circuit CM 1 , and the drain of the P-channel MOS transistor MP 2 becomes the output terminal of the current mirror circuit CM 1 . The commonly connected sources become a common terminal of the current mirror circuit.

Next, in reference to FIG. 4B , the second current mirror circuit CM 2 shown in FIG. 1 is constituted by two N-channel MOS transistors MN 1 and MN 2 , and their respective sources and gates are connected in common. The gate and drain of the N-channel MOS transistor MN 1 are connected in common to an input terminal of the current mirror circuit, and the drain of the N-channel MOS transistor MN 2 becomes the output terminal of the current mirror circuit CM 2 . The commonly connected sources become a common terminal of the current mirror circuit CM 2 .

Next, a structural example of a voltage comparator circuit using the differential amplifier shown in FIG. 1 will be shown. As in the conventional example shown in FIG. 9 , CMOS inverters ( FIG. 10 ) are cascode-connected in three stages after the differential amplifier circuit.

A detailed explanation on the differential amplifier shown in FIG. 1 will be given. This differential amplifier is an application of so-called folded cascode-type differential amplifier. Here, the operation of this circuit will be explained.

<When Both the First and Second Differential Pairs are Operating>

Assuming a voltage higher on the side of In − than that of In + is inputted and it is a differential input voltage higher than indicated in Equation (7), the differential amplifier shown in FIG. 1 operates as a comparator circuit, therefore, all the bias current of the first differential pair I 1 flows to the second P-channel MOS transistor MP 2 . The current of the first P-channel MOS transistor MP 1 becomes zero. On the other hand, all the bias current of the second differential pair I 2 flows to the first N-channel MOS transistor MN 1 and the current of the second N-channel MOS transistor MN 2 becomes zero. Looking at the bias current condition of each transistor at this time, the following Equations (30) and (31) hold where I D(MN3) is the drain current of the third N-channel MOS transistor MN 3 and I D(MN4) is the drain current of the fourth N-channel MOS transistor MN 4 , since the fourth N-channel MOS transistor MN 4 's drain current I D(MN4) is the subtraction of a second P-channel MOS transistor MP 2 's drain current I D(MP2) from a current source I 4 and the third N-channel MOS transistor MN 3 's drain current I D(MN3) is the subtraction of a first P-channel MOS transistor MP 1 's drain current I D(MP1) from a current source I 3 :

I D(MN4) =I 4 −I D(MP2) =I 4 −I 1   (30)

I D(MN3) =I 3 −I D(MP1) =I 3   (31)

Here, the relationship among I 1 , I 3 , and I 4 is as follows:

I 3 =I 4 ≧I 1   (32)

On the other hand, since a fifth P-channel MOS transistor MP 5 's drain current I D(MP5) is equal to the third N-channel MOS transistor MN 3 's drain current I D(MN3) , the following equation holds:

I D(MP5) =I D(MN3)   (33)

Further, a third P-channel MOS transistor MP 3 's drain current I D(MP3) is the addition of the fifth P-channel MOS transistor MP 5 's drain current I D(MP5) and a first N-channel MOS transistor MN 1 's drain current I D(MN1) , and I D(MP5) =I 3 , I D(MN1) =I 2 , therefore, the following equation holds:

I D(MP3) =I D(MP5) +I D(MN1) =I 3 +I 2   (34)

Because the respective gates and sources of the fourth P-channel MOS transistor MP 4 and the third P-channel MOS transistor MP 3 are connected in common, their drain currents are equal. Therefore, a fourth P-channel MOS transistor MP 4 's drain current I D(MP4) is given by the following equation:

I D(MP4) =I D(MP3)=I 3 +I 2   (35)

Further, since a sixth P-channel MOS transistor MP 6 's drain current I D(MP6) is the subtraction of a second N-channel MOS transistor MN 2 's drain current I D(MN2) from the fourth P-channel MOS transistor MP 4 's drain current I D(MP4) , and I D(MN2) is zero in this condition, it is given by the following equation:

I D(MP6) =I D(MP4) −I D(MN2) =I 3 +I 2   (36)

The currents indicated in Equations (30) and (36) are the input currents of the first and second current mirror circuits CM 1 and CM 2 respectively. The input to output current ratio of the first and second current mirror circuits CM 1 and CM 2 can be given by the following equation:

Input current:output current=1:k  (37)

Here, assuming k>1, an output end current I out is the addition of the output currents of the first and second current mirror circuits, therefore, it is given by the following Equation (38), assuming the current flowing into the output end is positive:

I out =k ( I 3 +I 2 )− k ( I 4 −I 1 )  (38)

Here, I 3 =I 4 , and as a result, the output end current I out has a current absorption capability indicated in the following equation and goes to a low level:

I out =k ( I 1 +I 2 )  (39)

Potentially it becomes 0V, a nearly negative power source (GND).

Assuming a voltage lower on the side of In − than that of In + is inputted, the circuit shown in FIG. 1 operates as a comparator circuit, therefore, all the bias current of the first differential pair I 1 flows to the first P-channel MOS transistor MP 1 . The current of the second P-channel MOS transistor MP 2 becomes zero. On the other hand, all the bias current of the second differential pair I 2 flows to the second N-channel MOS transistor MN 2 and the current of the first N-channel MOS transistor MN 1 becomes zero. Looking at the bias current condition of each transistor at this time, I D(MN3) , the drain current of the third N-channel MOS transistor MN 3 , and I D(MN4) , the drain current of the fourth N-channel MOS transistor MN 4 , are given by the following Equations (40) and (41) respectively:

I D(MN4) =I 4 −I D(MP2) =I 4   (40)

I D(MN3) =I 3 −I D(MP1) =I 3 −I 1   (41)

On the other hand, since a fifth P-channel MOS transistor MP 5 's drain current I D(MP5) is equal to the third N-channel MOS transistor MN 3 's drain current I D(MN3) , the following Equation (42) holds:

I D(MP5) =I D(MN3)   (42)

Further, a third P-channel MOS transistor MP 3 's drain current I D(MP3) is the addition of the fifth P-channel MOS transistor MP 5 's drain current I D(MP5) and a first N-channel MOS transistor MN 1 's drain current I D(MN1) , and I D(MP5) =I 3 −I 1 , I D(MN1) =0 in this condition, therefore, the following Equation (43) holds:

I D(MP3) =I D(MP5) +I D(MN1) =I 3 −I 1   (43)

Because the respective gates and sources of the fourth P-channel MOS transistor MP 4 and the third P-channel MOS transistor MP 3 are connected in common, their drain currents are equal. Therefore, a fourth P-channel MOS transistor MP 4 's drain current I D(MP4) is similarly given by the following equation (44):

I D(MP4) =I D(MP3) =I 3 −I 1   (44)

Further, since a sixth P-channel MOS transistor MP 6 's drain current I D(MP6) is the subtraction of a second N-channel MOS transistor MN 2 's drain current I D(MN2) from the fourth P-channel MOS transistor MP 4 's drain current I D(MP4) , and I D(MN2) is I 2 in this condition, it is given by the following equation:

I D(MP6) =I D(MP4) −I D(MN2) =I 3 −I 1 −I 2   (45)

The currents indicated in Equations (40) and (45) are the input currents of the first and second current mirror circuits CM 1 and CM 2 respectively.

Therefore, an output end current I out is given by the following Equation (46), assuming the current discharged from the output end is positive:

I out =kI 4 −k ( I 3 −I 1 −I 2 )  (46)

Here, I 3 =I 4 , and as a result, the output end current I out has a current discharge capability indicated in the following Equation (47) and goes to a high level:

I out =k ( I 1 +I 2 )  (47)

Potentially it becomes a nearly positive power source VDD.

As indicated in Equations (39) and (47), the current absorption capability at the time of a low level and the current discharge capability at the time of a high level have the same current value, therefore, even in the case where the load has a parasitic capacitance, a rising waveform and a falling waveform are symmetrical and a digital waveform obtained by waveform-shaping these waveforms can have an output with a duty ratio of 50%.

Above explanations relate to the case where the differential pair of the N-channel transistors and the differential pair of the P-channel transistors are both operating. When the in-phase signal voltage of the input differential signal decreases, the differential pair of the N-channel stops operating. On the other hand, when the in-phase signal voltage of the input differential signal increases, the differential pair of the P-channel stops operating. Hereinafter, the operation at this time will be explained.

<When Only the First Differential Pair is Operating>

In FIG. 1 , the current source I 2 , which biases the N-channel differential stage, is normally constituted by N-channel MOS transistors. At this time, the minimum input voltage V in(min.) required for the normal operation of the N-channel differential stage is given by the following Equation (48):

V in(min.) =V GS(MN1/2) +V DS(sat)(I2)   (48)

V GS(MN1/2) : the gate-source voltages of the N-channel MOS transistors MN 1 / 2 ,

V DS(sat)(I2) : the drain-source voltage of the N-channel MOS transistor, which constitutes the current source I 2 , at the saturation point (a minimum voltage required for the operation in the pentode region).

When the input voltage is lower than this V in(min.) , the N-channel transistor differential pair does not operate. Therefore, only the P-channel transistor differential pair operates. Under this condition, assuming a voltage higher on the side of In than that of In + is inputted, all the bias current of the first differential pair I 1 flows to the second P-channel MOS transistor MP 2 . The current of the first P-channel MOS transistor MP 1 becomes zero. On the other hand, the second differential pair does not operate since it is out of the input voltage range. In other words, the both drain currents of the first N-channel MOS transistor MN 1 and the second N-channel MOS transistor MN 2 become zero.

Looking at the bias current condition of each transistor at this time, I D(MN3) , the drain current of the third N-channel MOS transistor MN 3 , and I D(MN4) , the drain current of the fourth N-channel MOS transistor MN 4 , are given by the following Equations (49) and (50) respectively:

I D(MN4) =I 4 −I 1   (49)

I D(MN3) −I 3   (50)

On the other hand, since a fifth P-channel MOS transistor MP 5 's drain current I D(MP5) is equal to the third N-channel MOS transistor MN 3 's drain current I D(MN3) , it is given by the following Equation (51):

I D(MP5) =I D(MN3)   (51)

Further, a third P-channel MOS transistor MP 3 's drain current I D(MP3) is the addition of the fifth P-channel MOS transistor MP 5 's drain current I D(MP5) and a first N-channel MOS transistor MN 1 's drain current I D(MN1) , and I D(MN1) =0 in this condition, therefore, the following Equation (52) holds:

I D(MP3) =I D(MP5) =I 3   (52)

Because the respective gates and sources of the fourth P-channel MOS transistor MP 4 and the third P-channel MOS transistor MP 3 are connected in common, their drain currents are equal. Therefore, a fourth P-channel MOS transistor MP 4 's drain, current I D(MP4) is given by the following Equation (53):

I D(MP4) =I D(MP3) =I 3   (53)

Further, since a sixth P-channel MOS transistor MP 6 's drain current I D(MP6) is the subtraction of a second N-channel MOS transistor MN 2 's drain current I D(MN2) from the fourth P-channel MOS transistor MP 4 's drain current I D(MP4) , and I D(MN2) is zero in this condition, the following Equation (54) holds:

I D(MP6) =I D(MP4) −I D(MN2) I 3   (54)

Therefore, the output terminal OUT goes to a low level, and a current absorption capability I out can be given by the following Equation (55):

I out =kI 3 −k ( I 4 −I 1 )= kI 1   (55)

Next, assuming a voltage lower on the side of In − than that of In + is inputted, this circuit operates as a comparator circuit, therefore, all the bias current of the first differential pair I 1 flows to the first P-channel MOS transistor MP 1 . The current of the second P-channel MOS transistor MP 2 becomes zero. On the other hand, the second differential pair does not operate since it is out of the input voltage range. In other words, the both drain currents of the first N-channel MOS transistor MN 1 and the second N-channel MOS transistor MN 2 become zero. Looking at the bias current condition of each transistor at this time, I D(MN3) , the drain current of the third N-channel MOS transistor MN 3 , and I D(MN4) , the drain current of the fourth N-channel MOS transistor MN 4 , are given by the following Equations (56) and (57) respectively:

I D(MN4) =I 4 −I D(MP2) =I 4   (56)

I D(MN3) =I 3 −I D(MP1) =I 3 −I 1   (57)

On the other hand, since a fifth P-channel MOS transistor MP 5 's drain current I D(MP5) is equal to the third N-channel MOS transistor MN 3 's drain current I D(MN3) , it is given by the following Equation (58):

I D(MP5) =I D(MN3)   (58)

Further, a third P-channel MOS transistor MP 3 's drain current I D(MP3) is the addition of the fifth P-channel MOS transistor MP 5 's drain current I D(MP5) and a first N-channel MOS transistor MN 1 's drain current I D(MN1) , and I D(MN1) =0 in this condition, therefore, it is given by the following equation:

I D(MP3) =I D(MP5) =I 3 −I 1   (59)

Because the respective gates and sources of the fourth P-channel MOS transistor MP 4 and the third P-channel MOS transistor MP 3 are connected in common, their drain currents are equal. Therefore, a fourth P-channel MOS transistor MP 4 's drain current I D(MP4) is given by the following Equation (60):

I D(MP4) =I D(MP3) =I 3 −I 1   (60)

Further, since a sixth P-channel MOS transistor MP 6 's drain current I D(MP6) is the subtraction of a second N-channel MOS transistor MN 2 's drain current I D(MN2) from the fourth P-channel MOS transistor MP 4 's drain current I D(MP4) , and I D(MN2) is zero in this condition, I D(MP6) can be given by the following Equation (61):

I D(MP6) =I D(MP4) −I D(MN2) =I 3 −I 1   (61)

Therefore, the output terminal OUT goes to a high level at this time, and a current discharge capability I OUT is given by the following Equation (62):

I out =kI 4 −k ( I 3 −I 1 )= kI 1   (62)

<When Only the Second Differential Pair is Operating>

In FIG. 1 , the current source I 1 , which biases the P-channel differential pair, is normally constituted by P-channel MOS transistors. At this time, the maximum input voltage V in(max.) required for the normal operation of the P-channel differential stage is given by the following Equation (63):

V in(max.) =V DD −V GD(MP1/2) +V DS(sat)(I1)   (63)

V GS(MP1/2) : the gate-source voltages of the P-channel MOS transistors MP 1 / 2 ,

V DS(sat)(I1) : the drain-source voltage of the P-channel MOS transistor, which constitutes the current source I 1 , at the saturation point (a minimum voltage required for the operation in the pentode region).

When the input voltage is higher than this V in(max.) , the P-channel MOS transistor differential pair does not operate. Therefore, only the N-channel transistor differential pair operates. Under this condition, assuming a voltage higher on the side of In − than that of In + is inputted, all the bias current of the second differential pair I 2 flows to the first N-channel MOS transistor MN 1 . The current of the second N-channel MOS transistor MN 1 becomes zero. On the other hand, the first differential pair does not operate since it is out of the input voltage range. In other words, the both drain currents of the first P-channel MOS transistor MP 1 and the second P-channel MOS transistor MP 2 become zero. Looking at the bias current condition of each transistor at this time, the following Equations (64) and (65) hold where I D(MN3) is the drain current of the third N-channel MOS transistor MN 3 and I D(MN4) is the drain current of the fourth N-channel MOS transistor MN 4 :

I D(MN4) =I 4 −I D(MP2) =I 4   (64)

I D(MN3) =I 3 −I D(MP1) =I 3   (65)

On the other hand, since a fifth P-channel MOS transistor MP 5 's drain current I D(MP5) is equal to the third N-channel MOS transistor MN 3 's drain current I D(MN3) , the following Equation (66) holds:

I D(MP5) =I D(MN3)   (66)

Further, a third P-channel MOS transistor MP 3 's drain current I D(MP3) is the addition of the fifth P-channel MOS transistor MP 5 's drain current I D(MP5) and a first N-channel MOS transistor MN 1 's drain current I D(MN1) , and I D(MN1) =I 2 in this condition, therefore, the following Equation (67) holds:

I D(MP3) =I D(MP5) +I D(MN1) =I 3 +I 2   (67)

Because the respective gates and sources of the fourth P-channel MOS transistor MP 4 and the third P-channel MOS transistor MP 3 are connected in common, their drain currents are equal. Therefore, a fourth P-channel MOS transistor MP 4 's drain current I D(MP4) is given by the following Equation (68):

I D(MP4) =I D(MP3) =I 3 +I 2   (68)

Further, since a sixth P-channel MOS transistor MP 6 's drain current I D(MP6) is the subtraction of a second N-channel MOS transistor MN 2 's drain current I D(MN2) from the fourth P-channel MOS transistor MP 4 's drain current I D(MP4) , and I D(MN2) is zero in this condition, the following Equation (69) holds:

I D(MP6) =I D(MP4) −I D(MN2) =I 3 +I 2   (69)

Therefore, the output terminal OUT goes to a low level. Since the input to output current ratio of the first and second current mirror circuits is 1:k, a current absorption capability I out is given by the following Equation (70):

I out =k ( I 3 +I 2 )− kI 4 =kI 2   (70)

Next, assuming a voltage lower on the side of In − than that of In + is inputted, the circuit of the present embodiment operates as a comparator circuit, therefore, all the bias current of the second differential pair I 2 flows to the second N-channel MOS transistor MN 2 . The current of the first N-channel MOS transistor MN 1 becomes zero. On the other hand, the first differential pair does not operate since it is out of the input voltage range. In other words, the both drain currents of the first P-channel MOS transistor MP 1 and the second P-channel MOS transistor MP 2 become zero. Looking at the bias current condition of each transistor at this time, I D(MN3) , the drain current of the third N-channel MOS transistor MN 3 , and I D(MN4) , the drain current of the fourth N-channel MOS transistor MN 4 , are given by the following Equations (71) and (72):

I d(MN4) =I 4 −I D(MP2) =I 4   (71)

I D(MN3) =I 3 −I D(MP1) =I 3   (72)

On the other hand, since a fifth P-channel MOS transistor MP 5 's drain current I D(MP5) is equal to the third N-channel MOS transistor MN 3 's drain current ID(MN 3 ), the following Equation (73) holds:

I D(MP5) =I D(MN3)   (73)

Further, a third P-channel MOS transistor MP 3 's drain current I D(MP3) is the addition of the fifth P-channel MOS transistor MP 5 's drain current I D(MP5) and a first N-channel MOS transistor MN 1 's drain current I D(MN1) , and I D(MN1) =0 in this condition, therefore, the following Equation (74) holds:

I D(MP3) =I D(MP5) =I 3   (74)

Because the respective gates and sources of the fourth P-channel MOS transistor MP 4 and the third P-channel MOS transistor MP 3 are connected in common, their drain currents are equal. Therefore, a fourth P-channel MOS transistor MP 4 's drain current I D(MP4) is given by the following Equation (75):

I D(MP4) =I D(MP3) =I 3   (75)

Further, since a sixth P-channel MOS transistor MP 6 's drain current I D(MP6) is the subtraction of a second N-channel MOS transistor MN 2 's drain current I D(MN2) from the fourth P-channel MOS transistor MP 4 's drain current I D(MP4) , and I D(MN2) =I 2 in this condition, I D(MP6) can be given by the following Equation (76):

I D(MP6) =I D(MP4) −I D(MN2) =I 3 −I 2   (76)

Therefore, the output terminal OUT goes to a high level at this time, and a current discharge capability I OUT is given by the following Equation (77):

I out =kI 4 −k ( I 3 −I 2 )= kI 2   (77)

Next, an explanation on the operation of the current mirror circuit shown in FIG. 4 will be given. For instance, the following Equation (78) holds where W MP1 and W MP2 are the gate widths of the first and second P-channel MOS transistors MP 1 and MP 2 respectively, and L MP1 and L MP2 are the gate lengths:

The relationship between an input current I in and the output current I out of the current mirror circuit is given by the following Equation (79):

I out =kI in   (79)

As becomes clear by looking at Equations (2), (3), and (4) that shows the relationships between the gate-source voltage of the MOS transistor and a drain current I d , the drain current is proportional to W/L.

FIG. 2 is a drawing showing the configuration of a differential amplifier of a second embodiment according to the present invention. In the configuration shown in FIG. 2 , the P-channel MOS transistors MP 3 and MP 4 in FIG. 1 become N-channel MOS transistors MN 3 and MN 4 respectively, the P-channel MOS transistors MP 5 and MP 6 in FIG. 1 become N-channel MOS transistors MN 5 and MN 6 , the absorption-type current sources I 3 and I 4 , and the N-channel MOS transistors MN 3 and MN 4 in FIG. 7 become discharge type current sources I 3 and I 4 , and P-channel MOS transistors MP 3 and MP 4 respectively, and it is configured so that the polarity is symmetrical to the one in FIG. 1 .

In reference to FIG. 2 , the differential amplifier of the second embodiment comprises a first differential pair of a first P-channel MOS transistor MP 1 and a second P-channel MOS transistor MP 2 , a second differential pair of a first N-channel MOS transistor MN 1 and a second N-channel MOS transistor MN 2 , a third and fourth N-channel MOS transistors MN 3 and MN 4 with their respective gates and sources connected in common, a fifth and sixth N-channel MOS transistors MN 5 and MN 6 with their gates connected in common to a first voltage source, a third and fourth P-channel MOS transistors MP 3 and MP 4 with their gate connected in common to a second voltage source, a first current mirror circuit CM 1 with its input connected to the drain of the sixth N-channel MOS transistor MN 6 and its common terminal connected to the positive power source VDD, a second current mirror circuit CM 2 with its input connected to the drain of the fourth P-channel MOS transistor MP 4 and its common terminal connected to a negative power source terminal (GND), a first constant current source (I 1 ) connected between the sources connected in common to the first differential pair and the positive power source VDD, a second constant current source (I 2 ) connected between the sources connected in common to the second differential pair and the negative power source (GND), a third constant current source (I 3 ) connected between the source of the third P-channel MOS transistor MP 3 and the positive power source (VDD), and a fourth constant current source (I 4 ) connected between the source of the fourth P-channel MOS transistor MP 4 and the positive power source (VDD), and the drain of the first P-channel MOS transistor MP 1 , which constitutes the first differential pair, and the source of the fifth N-channel MOS transistor MN 5 are connected in common. The drain of the second P-channel MOS transistor MP 2 , which constitutes the first differential pair, and the source of the sixth N-channel MOS transistor MN 6 are connected in common. The drain of the first N-channel MOS transistor MN 1 , which constitutes the second differential pair, and the source of the third P-channel MOS transistor MP 3 are connected in common. The drain of the second N-channel MOS transistor MN 2 , which constitutes the second differential pair, and the source of the fourth P-channel MOS transistor MP 4 are connected in common. The gate of the third N-channel MOS transistor MN 3 is connected in common with the drain of the fifth N-channel MOS transistor MN 5 and the drain of the third P-channel MOS transistor MP 3 . The output of the first current mirror circuit CM 1 and the output of the second current mirror circuit CM 2 are connected in common to an output terminal OUT. The gate of the first P-channel MOS transistor MP 1 and the gate of the first N-channel MOS transistor MN 1 are connected in common to an inverting input terminal In − , and the gate of the second P-channel MOS transistor MP 2 and the gate of the second N-channel MOS transistor MN 2 are connected in common to an noninverting input terminal In + . Here, the first and second current mirror circuits CM 1 and CM 2 have an input to output current ratio of 1:k (k>1). As in the conventional example, CMOS inverters cascode-connected in three stages after the differential amplifier are connected to constitute the voltage comparator circuit.

The operation of the circuit shown in FIG. 2 is the same as the one in FIG. 1 except that the circuit is symmetrical, therefore the explanation will be omitted.

FIG. 3 is a drawing showing the configuration of a differential amplifier of a third embodiment according to the present invention. In reference to FIG. 3 , the differential amplifier of the third embodiment comprises a first differential pair of a first P-channel MOS transistor MP 1 and a second P-channel MOS transistor MP 2 , a second differential pair of a first N-channel MOS transistor MN 1 and a second N-channel MOS transistor MN 2 , a third and fourth N-channel MOS transistors MN 3 and MN 4 with their respective gates connected in common to a first voltage source (V 1 ), a first constant current source (I 1 ) connected between the sources connected in common to the first differential pair and a positive power source VDD, a second constant current source (I 2 ) connected between the sources connected in common to the second differential pair and a negative power source GND, a third constant current source (I 3 ) connected between the source of the third N-channel MOS transistor MN 3 and the negative power source (GND), a fourth constant current source (I 4 ) connected between the source of the fourth N-channel MOS transistor MN 4 and the negative power source (GND), a first current mirror circuit CM 1 with its input terminal connected in common to the drain of the first N-channel MOS transistor MN 1 and the drain of the third N-channel MOS transistor MN 3 and its common terminal connected in common to the positive power source (VDD) terminal, a second current mirror circuit CM 2 with its input terminal connected in common to the drain of the second N-channel MOS transistor MN 2 and the drain of the fourth N-channel MOS transistor MN 4 and its common terminal connected in common to the positive power source VDD terminal, and a third current mirror circuit CM 3 with its input terminal connected to the output terminal of the first current mirror circuit CM 1 and its common terminal connected to the negative power source (GND) terminal. And the drain of the first P-channel MOS transistor MP 1 is connected to the source of the third N-channel MOS transistor MN 3 . The drain of the second P-channel MOS transistor MP 2 is connected to the source of the fourth N-channel MOS transistor MN 4 . The output terminal of the second current mirror circuit CM 2 and the output terminal of the third current mirror circuit CM 3 are connected in common to an output terminal OUT. The gate of the first P-channel MOS transistor MP 1 and the gate of the first N-channel MOS transistor MN 1 are connected in common to an inverting input terminal In − , and the gate of the second P-channel MOS transistor MP 2 and the gate of the second N-channel MOS transistor MN 2 are connected in common to an noninverting input terminal In + . The second and third current mirror circuits CM 2 and CM 3 have an input to output current ratio of 1:k (k>1). As shown in FIG. 9 , CMOS inverters ( FIG. 10 ) are cascode-connected in three stages after the differential amplifier, and constitute the voltage comparator circuit.

Next, the operation of the differential amplifier shown in FIG. 3 will be explained. As the differential amplifiers shown in FIGS. 1 and 2 , this differential amplifier in FIG. 3 has three modes of operation, however, an explanation on the case where both the P-channel differential pair and N-channel differential pair are operating, the main mode out of the three, will be given here.

Assuming a voltage higher on the side of In − than that of In + is inputted and it is a differential input voltage higher than indicated in Equation (7), the circuit shown in FIG. 9 operates as a comparator. All the bias current of the first differential pair I 1 flows to the second P-channel MOS transistor MP 2 . The current of the first P-channel MOS transistor MP 1 becomes zero. On the other hand, all the bias current of the second differential pair I 2 flows to the first N-channel MOS transistor MN 1 and the current of the second N-channel MOS transistor MN 2 becomes zero. Looking at the bias current condition of each transistor at this time, the following Equations (80) and (81) hold where I D(MN3) is the drain current of the third N-channel MOS transistor MN 3 and I D(MN4) is the drain current of the fourth N-channel MOS transistor MN 4 , since the fourth N-channel MOS transistor MN 4 's drain current I D(MN4) is the subtraction of a second P-channel MOS transistor MP 2 's drain current I D(MP2) from a current source I 4 and the third N-channel MOS transistor MN 3 's drain current I D(MN3) is the subtraction of a first P-channel MOS transistor MP 1 's drain current I D(MP1) from a current source I 3 :

I D(MN4) =I 4 −I D(MP2) =I 4 −I 1   (81)

I D(MN3) =I 3 −I D(MP1) =I 3   (81)

Here, the relationship among I 1 , I 3 , and I 4 is as follows:

I 3 =I 4 ≧I 1   (82)

Next, an input current of the first current mirror circuit (CM 1 ) I in(CM1) is given by the following Equation (83), where the input current:output current of the first current mirror circuit=1:1, since I in(CM1) is the sum of a first N-channel MOS transistor's drain current I D(MN1) and the third N-channel MOS transistor's drain current I D(MN3) , and the same current becomes an output current of the first current mirror circuit I out(CM1) :

I in(CM1) =I D(MN1) +I D(MN3) =I 2 +I 3 =I out(CM1)   (83)

Next, an input current of the second current mirror circuit (CM 2 ) I in(CM2) is given by the following Equation (84) since I in(CM2) is the sum of a second N-channel MOS transistor's drain current I D(MN2) and the fourth N-channel MOS transistor's drain current I D(MN4) :

I in(CM2) =I D(MN2) +I D(MN4) =I 4 −I 1   (84)

Further, the following Equation (85) holds where the input current:output current of the second current mirror circuit=1:1, since an output current of the second current mirror circuit I out(CM2) is the input current of the second current mirror circuit I in(CM2) multiplied by k:

I out(CM2) =kI in(CM2) =k ( I 4 −I 1 )  (85)

The input terminal of the third current mirror circuit (CM 3 ) and the output terminal of the first current mirror circuit are connected in common. Therefore, the following Equation (86) holds since a third current mirror circuit (CM 3 )'s input current I in(CM3) is equal to the first current mirror circuit (CM 1 )'s output current I out(CM1) :

I in(CM3) =I out(CM1)   (86)

Further, the following Equation (87) holds where the input current: output current of the third current mirror circuit (CM 3 )=1:k, since an output current of the third current mirror circuit (CM 3 ) I out(CM3) is the input current of the third current mirror circuit (CM 3 ) I in(CM3) multiplied by k:

I out(CM3) =kI in(CM3) =k ( I 2 +I 3 )  (87)

Therefore, an output current of the output terminal I out is the subtraction of the output current of the second current mirror circuit I out(CM2) from the output current of the third current mirror circuit I out(CM3) in the case where the current flows to the output terminal in a positive direction and the following Equation (88) holds where I 3 =I 4 :

I out =I out(CM3) −I out(CM2) =k ( I 2 +I 3 )− k ( I 4 −I 1 )= k ( I 1 +I 2 )  (88)

The output terminal OUT goes to a low level, and potentially it becomes 0V, nearly a negative power source (GND).

Next, assuming a voltage lower on the side of In − than that of In + is inputted, the differential amplifier shown in FIG. 3 operates as a comparator circuit, therefore, all the bias current of the first differential pair I 1 flows to the first P-channel MOS transistor MP 1 : The current of the second P-channel MOS transistor MP 2 becomes zero. On the other hand, all the bias current of the second differential pair I 2 flows to the second N-channel MOS transistor MN 2 and the current of the first N-channel MOS transistor MN 1 becomes zero. Looking at the bias current condition of each transistor at this time, the following Equations (89) and (90) hold where I D(MN3) is the drain current of the third N-channel MOS transistor MN 3 and I D(MN4) is the drain current of the fourth N-channel MOS transistor MN 4 :

I D(MN4) =I 4 −I D(MP2) =I 4   (89)

I D(MN3) =I 3 −I D(MP1) =I 3 I 1   (90)

Here, the relationship among I 1 , I 3 , and I 4 is as follows:

I 3 =I 4 ≧I 1   (91)

Next, an input current of the first current mirror circuit (CM 1 ) I in(CM1) is given by the following Equation (92), where the input current:output current of the first current mirror circuit=1:1, since I in(CM1) is the sum of a first N-channel MOS transistor's drain current I D(MN1) and the third N-channel MOS transistor's drain current I D(MN3) , and the same current becomes an output current of the first current mirror circuit I out(CM1) :

I in(CM1) =I D(MN1) +I D(MN3) =I 3 −I 1 =I out(CM1)   (92)

Next, an input current of the second current mirror circuit (CM 2 ) I in(CM2) is given by the following Equation (93) since I in(CM2) is the sum of a second N-channel MOS transistor's drain current I D(MN2) and the fourth N-channel MOS transistor's drain current I D(MN4) :

I in(CM2) =I D(MN2) +I D(MN4) =I 2 +I 4   (93)

Further, the following Equation (94) holds where the input current:output current of the second current mirror circuit=1:1, since an output current of the second current mirror circuit I out(CM2) is the input current of the second current mirror circuit I in(CM2) multiplied by k:

I out(CM2) =kI in(CM2) =k ( I 2 +I 4 )  (94)

The input terminal of the third current mirror circuit (CM 3 ) and the output terminal of the first current mirror circuit are connected in common. Therefore, the following Equation (95) holds since a third current mirror circuit (CM 3 )'s input current I in(CM3) is equal to the first current mirror circuit (CM 1 )'s output current I out(CM1) :

I in(CM3) =I out(CM1)   (95)

Further, the following Equation (96) holds where the input current:output current of the third current mirror circuit (CM 3 )=1:k, since an output current of the third current mirror circuit (CM 3 ) I out(CM3) is the input current of the third current mirror circuit (CM 3 ) I in(CM3) multiplied by k:

I out(CM3) =kI in(CM3) =k ( I 3 −I 1 )  (96)

Therefore, an output current of the output terminal I out is the subtraction of the output current of the second current mirror circuit I out(CM2) from the output current of the third current mirror circuit I out(CM3) in the case where the current flows from the output terminal in a positive direction and the following Equation (97) holds where I 3 =I 4 :

I out =I out(CM2) −I out(CM3) =k ( I 2 +I 4 )− k ( I 3 −I 1 )= k ( I 1 +I 2 )  (97)

The output terminal OUT goes to a high level, and potentially it becomes 0V, nearly a positive power source (VDD). The comparator operates as described above.

FIG. 5 is a drawing showing an example of a circuit simulation result of the present embodiment. The differential amplifier shown in FIG. 1 is put into the structure shown in FIG. 9 , and the output waveforms (simulation values) with an input differential signal frequency of 200 MHz, a differential amplitude of ±50 mV, and an in-phase signal voltage of 0.3V are shown in FIG. 5 . As shown in FIG. 5 , according to the present embodiment, the duty of the final output waveform of the CMOS inverters is nearly (essentially) 50%. In other words, the case where it ends up being far from 50% as in the simulation result of the conventional structure shown in FIG. 11 will not happen.

As describe above, the voltage comparator circuit of the present embodiment is especially suitable for a high-speed differential interface circuit with a low power supply voltage and wide input voltage range. According to the circuit of the present embodiment, a high-speed voltage comparator circuit with a wide input voltage range can be realized with a small number of elements and relatively low power consumption. The present invention is most suitable to be used for a semiconductor integrated circuit device for a high-speed differential interface circuit.

The present invention is described above with reference to some preferred embodiments, however, the present invention is not limited to the structures of the above embodiments, and it should be noted that it includes various modifications and revisions, which may be made possible by a manufacturer within the scope of the present invention.

It should be noted that other objects, features and aspects of the present invention will become apparent in the entire disclosure and that modifications may be done without departing the gist and scope of the present invention as disclosed herein and claimed as appended herewith.

Also it should be noted that any combination of the disclosed and/or claimed elements, matters and/or items may fall under the modifications aforementioned.