VCO buffer circuit

This application claims priority from Indian patent application No. 1041/Del/2004, filed Jun. 4, 2004, which is incorporated herein by reference.

Embodiments of the present invention generally relate to Voltage Controlled Oscillators (VCO) and in particular relate to a VCO buffer circuit having low supply noise sensitivity for providing a stabilized output.

A VCO-buffer circuit is mainly used as interface between a Voltage Controlled Oscillator (VCO) and counters in a PLL (Phase Locked Loop). The purpose of the VCO-buffer circuit is to shift the level of the VCO output voltage to a level suitable for the counters operation so as to adjust the duty cycle of the counters. Here the VCO-buffer circuit for Ring VCO (hereinafter referred to as RING/VCO) is used as an interface.

One conventional VCO provides a VCO buffer cell that comprises a differential pair of transistors and a current mirror circuit. The differential pair of transistors receives input terminals and generates a differential voltage swing in response to the input signals. The current mirror circuit is operably coupled to the pair of transistors and is configured to receive a first external reference current and provide a mirrored current to an active one of the transistors. The VCO circuit provides high-speed consistent output but uses additive circuitry for the purpose and therefore causes an increase in the overall device area, which is undesirable in area specific Voltage Controlled Oscillators.

Schematics of conventional VCO and VCO buffer circuits are shown in FIG. 1 . The Ring Oscillator shown is a three-stage oscillator circuit. The three stages of the oscillator are the inverter stages. The oscillation frequency of the Ring is determined by the delay in the inverting stages. The VCO buffer shown is coupled between the VCO and the counters in the Phase Locked Loop. As shown in the figure it is a three input (IN 1 , IN 2 , IN 3 ) device powered by a higher voltage supply DVDD and connected to ground at DGND. It generates an output PHI that serves to shift the level of the VCO output voltage to a level suitable for the counters operation so as to adjust the duty cycle of the counters.

The following symbols are used hereafter for the analysis of the VCO buffer circuit:

Vthn=Threshold Voltage of NMOS transistors Vthp=Threshold Voltage of PMOS transistors Kn=Transconductance Parameter of NMOS transistors Kp=Transconductance Parameter of NMOS transistors VIN=Input voltage to the stages for loading the RING. DVDD=Digital Supply Voltage input to the VCO and VCO-buffer circuit. Vo 1 h=Minimum High output voltage. Vo 1 l=Maximum Low output voltage. Vm=Peak value of the input voltage.

The nodes of the RING are loaded by a stage as shown in FIG. 2 , which is a transistorized circuit formed by PMOS MS 1 P 1 and NMOS MS 1 N 1 or by a stage as shown in FIG. 3 , which is formed by PMOS MS 2 P 1 and NMOS MS 2 N 1 , wherein the input to NMOS is VIN and a bias signal BIAS is applied to the PMOS transistor. The following cases are considered for loading the VCO circuit ( FIG. 1 ) by the stages shown in FIGS. 2 & 3 .

Case (1) when VIN= 0 ; Vo 1 h=DVDD−Vthp   1.1

Case (2) when VIN=Vm;

Vo 1 l= ( DVDD−Vthp )+((2*β s 1 n 1)/β s 1 p 1)*( Vm−Vthn )−((2*β s 1 n 1)/β s 1 p 1)*( Vm−Vthn )* sqrt (1+(β s 1 n 1*( Vm−Vthn ))/(β s 1 p 1*( DVDD−Vthp )))  1.2

where, β s 1 n 1 =Kn* ( W/L ) s 1 n 1

andβ s 1 p 1 =Kp* ( W/L ) s 1 p 1.

If the digital supply changes by a small amount ΔDVDD, then the corresponding change in Vo1l is given by:

Δ Vo 1 l=ΔDVDD (1−1 /sqrt ((1+(β s 1 p 1*( DVDD−Vthp ))/(β s 1 n 1*( Vm−Vthn )))  1.3

If the digital supply changes by a small amount ΔDVDD, then the corresponding change in Vo1h is given by:

ΔVo1h=ΔDVDD   1.4

For the circuit shown in FIG. 1 ;

Case (1) when VIN=0; Vo2h=DVDD  1.5

Case (2) when VIN=Vm; Vo2l=0  1.6

If the digital supply changes by a small amount ΔDVDD, then there is no change in Vo2l. The change in Vo2h is given by:

ΔVo2h=ΔDVDD   1.7

FIG. 4 shows a conventional VCO-buffer circuit. The operation of the circuit is discussed as follows:

Case 1: When IN1=0, IN2=Vm; Case 2: When IN1=Vm, IN2=0; Case 3:When IN1=Vm, IN2=Vm; Case 4:When IN1=0, IN1=0.

Case (1): In this case the voltage at node VBUF_MIR_OLD is Vo1h (equation 1.1) that causes PMOS MP 2 to be switched off. Further, since IN 2 =Vm, the node VBUF_OLD discharges to zero volt.

Case (2) In this case the voltage at node VBUF_MIR_OLD is Vo1l (equation 1.2) that causes PMOS MP 2 to be switched on. Further, since IN 2 =0 volt, the node VBUF_OLD charges to DVDD.

Case (3) In this case the voltage at VBUF_MIR_OLD node is Vo1l (equation 1.2) that causes both the PMOS MP 2 and NMOS MN 2 to be switched on and the voltage at VBUF_MIR_OLD is determined by the relative sizes of the transistors MP 2 and MN 2 .

Case (4) In this case both PMOS MP 2 and NMOS MN 2 are switched off. The voltage at node VBUF_MIR_OLD is determined by the value of VBUF_MIR_OLD, before IN 1 and IN 2 both become zero volt.

As shown in FIG. 4 transistors MN 1 and MN 2 of the buffer load the VCO at two inputs (nodes IN 1 and IN 2 ). A dummy transistor MN 3 is used to load input IN 3 for providing balanced load distribution on the three nodes of the VCO. Symmetric loading is necessary so that the oscillation amplitude at each of the three nodes is the same, which in turn improves the phase noise performance of the VCO.

The capacitances by which these nodes are being loaded (by the buffer only) are the gate to source capacitance (Cgs) and the gate to drain capacitance (Cgd) of the transistors MN 1 , MN 2 and MN 3 . During each oscillation cycle IN 1 or IN 2 or IN 3 oscillate from zero volt to Vm and then again to zero volt (Loads are being charged and discharged). Here, charging and discharging of the Gate to Drain Capacitances of transistors MN 1 , MN 2 and MN 3 are discussed, because the amount of charge on these capacitors depends upon the value of DVDD.

Assuming the digital supply to be at DVDD, the VCO-buffer circuit operates for the following input-output parameters:

When IN 1 =0, the voltage at node VBUF_MIR_OLD is Vo1h (equation 1.1); when IN 1 =Vm, the voltage at node VBUF_MIR_OLD is Vo1l (equation 1.2); when IN 1 =0 and node VBUF_MIR_OLD at Vo1h the charge on the drain to gate capacitor of MN 1 is given by:

Qicgd=Cgd* ( Vo 1 h− 0)  1.8

When IN 1 =Vm and node VBUF_MIR_OLD at Vo1l (equation 1.2) charge on drain to gate capacitor of MN 1 is given by:

Qfcgd=Cgd* ( Vo 1 l−Vm )  1.9

If the oscillation frequency is fo then the average current per cycle used to charge this capacitor is given by:

The direction of this current is through drain to gate capacitor of transistor MN 1 into the RING. Further, the current directly adds to the current going into the RING and depending on the amount of current going into the RING the oscillation frequency of the VCO is fixed.

Assuming that the digital supply changes from DVDD to DVDD+ΔDVDD, then it is observed that the average current by which the capacitor is being charged each cycle changes from (fo/2)*C gd (V o1l −Vm−Vo1h+0) to (fo/2)*Cgd(Vo1l+ΔVo1l−Vm−Vo1h−ΔVo1h+0). The change in average charging current lavch 1 is given by:

Δ lavch 1=( fo/ 2)* C gd (Δ Vo 1 l−ΔVo 1 h )  1.11

Applying similar analysis to charging of drain to gate capacitor of transistor MN 2 , which is driven by node IN 2 we can say that average current by which this capacitor is being charged each cycle changes from (fo/2)*Cgd(Vo2l−Vm−Vo2h+0) to (fo/2)*Cgd(Vo2l−Vm−Vo2h−ΔVo2h+0).The change in average charging current lavch 2 is given by:

Δ lavch 2=( fo/ 2)* Cgd (−Δ Vo 1 h )  1.12

From equations 1.11 and 1.12 we note that |Δlavch 2 |>>Δlavch 1 .

This implies that the current that is going into the RING for a particular control voltage increases by Δlavch 1 +Δlavch 2 . Since both the quantities Δlavch 1 and Δlavch 2 are negative we can also say that the current that is going into the RING for a particular control voltage reduces by |Δlavch 1 |+|Δlavch 2 |. As a result the oscillation frequency reduces and when there is negative jump on the digital supply it can be proved by a similar argument that the oscillation frequency increases. A similar analysis can be done for the discharging current of the gate to drain capacitances of the transistors loading the RING.

The noise on the digital supply causes the oscillation frequency of the RING to vary which is mainly due to the changes in the charging and discharging currents of the gate to drain capacitances of the transistors loading the RING, which is undesirable for the operation of the VCO and VCO-buffer interface.

Thus, a need is felt for VCO buffer circuit that reduces the variation in oscillation frequency of the ring oscillator.

According to one embodiment of the present invention, an improved VCO buffer reduces supply noise sensitivity of frequency of oscillations of the VCO.

Other embodiments of the present invention are directed to improving the phase noise performance of the VCO.

According to one embodiment of the instant invention, a VCO buffer circuit comprises:

a first loading means receiving a first signal for loading the VCO at a first input node; a second loading means receiving a second signal for loading the VCO at a second input node; a third loading means coupled to said first loading means for loading the VCO at a third input node to thereby provide balanced load distribution on three nodes of VCO; at least three current controlling means coupled to each other to form a symmetrical configuration and receiving input signals from said first and second loading means for minimizing the variations in the oscillation frequency of the VCO; and a means for buffering the output of said current controlling means.

Further, according to another embodiment of the present invention a method providing a VCO buffer circuit comprises steps of:

loading the VCO at the first input node by a first loading means; loading the VCO at second input node by a second loading means; balancing load distribution on three nodes of the VCO by loading the VCO at the third input node by a third loading means; minimizing variations in the oscillation frequency of the VCO by symmetrically connecting at least three current controlling means to said first and second loading means; and buffering the output of said current controlling means.

Thus, embodiments of the instant invention provide an improved VCO buffer with low supply noise sensitivity to thereby provide improved phase noise performance of the VCO.

Embodiments of the invention will now be described with reference to the accompanying drawings.

FIG. 1 illustrates a conventional circuit diagram of a Ring Voltage Controlled Oscillator (RING/VCO) and VCO buffer.

FIG. 2 illustrates a conventional circuit for loading the nodes of the RING.

FIG. 3 illustrates another conventional circuit for loading the nodes of the RING.

FIG. 4 illustrates another existing circuit of the VCO-buffer.

FIG. 5 illustrates the circuit diagram of the VCO-buffer in accordance with the instant invention.

The following discussion is presented to enable a person skilled in the art to make and use the invention. Various modifications to the embodiments will be readily apparent to those skilled in the art, and the generic principles herein may be applied to other embodiments and applications without departing from the spirit and scope of the present invention. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.

FIGS. 1 , 2 , 3 & 4 have been described under the heading titled, “Background”.

The VCO buffer of the instant invention comprises of a symmetrical current mirror structure that is formed by connecting two current mirror circuits to the first current mirror circuit, as shown in FIG. 4 . Thus the resultant structure of the VCO buffer comprises a symmetrical current mirror circuit configuration between the transistor MN 11 and MN 22 , wherein these transistors receive inputs at the nodes IN 1 and IN 2 respectively. Another input signal is provided to the VCO at the third input node IN 3 for providing balanced load distribution on the three nodes of the VCO.

The first current mirror circuit is formed by MP 11 and M 1 transistors, that generate a first voltage at the node VBUF_PMIR 1 _NEW. The first current mirror configuration is coupled to the first input node IN 1 through NMOS MN 11 . A second current mirror circuit is formed by NMOS transistors M 0 and M 2 and is coupled to the output of the first current mirror circuit for generating a second voltage at node VBUF_NMIR_NEW, which is further connected to a third current mirror circuit formed by the PMOS transistors M 3 and MP 21 to thus form a symmetrical current mirror circuit configuration. This configuration of current mirrors generates a third voltage at the node VBUF_PMIR 2 _NEW. It can be clearly observed therefore that the supply sensitivity is minimized because the nodes IN 1 and IN 2 of the ring are now loaded by two identical current mirror stages. Finally, the cumulative output of the three current mirror stages is produced at the node VBUF_NEW.

A transistorized inverter circuit (MP 44 & MN 44 ) receives the common output of the three current mirror stages. Another inverter circuit (MP 55 & MN 55 ) is connected to the output of the inverter circuit formed by (MP 44 & MN 44 ) for buffering the output of the current mirror stages to thereby adjust the duty cycle of the Voltage Controlled Oscillator. The VCO buffer circuit is powered by DVDD and is connected to the ground at DGND.

If the oscillation frequency of the VCO is fo then the average current per cycle used to charge the drain to gate capacitors of transistors MN 11 and MN 22 which are driven by nodes IN 1 and IN 2 of the RING respectively is given by:

Assuming that the digital supply changes from DVDD to DVDD+ΔDVDD, then the change in average charging current lavch 11 and lavch 22 is given by:

Δ lavch 11=Δ lavch 11=( fo/ 2)* Cgd (Δ Vo 1 l−ΔVo 1 h )  1.14

This implies that the current that is going into the RING for a particular control voltage increases by 2*Δlavch 11 . The value of Δlavch 11 is negative, thus it can be concluded that the current that is going into the RING for a particular control voltage reduces by 2*|Δlavch 11 |.

Further, since |Δlavch 2 |>>Δlavch 1 , 2 *|Δlavch 1 |<<|Δlavch 1 |+|Δlavch 2 |, the change in the current going into the RING (due to change in digital supply) for the VCO-buffer of the instant invention is much less than that for the VCO-buffer shown in FIG. 4 .

The conventional VCO buffer circuit of FIG. 4 and the VCO buffer according to the instant invention were both simulated with 100 mv jump on the digital supply voltage. The resulting change in frequency of the VCO across all possible corners is tabulated below.

It can be clearly seen from the Table 1 that the VCO buffer circuit of the instant invention reduces the supply noise sensitivity by reducing the amount of change in the charging and discharging currents of the gate to drain capacitances of the transistors loading the VCO. Thus, the VCO buffer circuit of the instant invention leads to less supply sensitivity by loading the nodes IN 1 and IN 2 by two identical stages to form a symmetrical current mirror configuration.

A VCO buffer as described with reference to the embodiment of FIG. 5 may be utilized in a variety of different types of electronic circuits, such as a phase-locked loop as previously mentioned. Such circuits may, in turn, be utilized in a variety of different types of integrated circuits, such as in microprocessors and communications-related integrated circuits.

From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention.