Voltage mode serial interface driver with PVT compensated impedance

The invention relates generally to serial data communication and, more particularly, to serial communication interface drivers.

Conventional high speed serial communication interface drivers typically consume a relatively large amount of power due to the analog biasing requirements (current flows all the time). The relationship between the currents consumed by the driver and the actual signal amplitude generated at the output of the driver can vary widely depending on the driver topology. Examples of conventional serial interface drivers are illustrated in FIGS. 1 and 2 .

FIG. 1 illustrates a CML example including resistors R 1 , R 2 and R 3 , transistors M 1 and M 2 , and output driver 18 . The transistors M 1 and M 2 are controlled by complementary digital inputs INP and INN. The circuit of FIG. 1 effectively has double 50 ohm termination, and the differential pair M 1 , M 2 steers current to the output. Because of current division between the internal (R 1 and R 2 ) and external (R 3 ) termination, only one-fourth of the output bias current I 0 is used to generate the output voltage Vo. A 10 mA output stage bias current is required to produce a 250 mV output swing. In FIG. 1 , the currents I 0 , I 1 and I 2 illustrate the operation of the circuit with transistor M 2 turned on, transistor M 1 turned off and I 0 =10 mA.

FIG. 2 illustrates a prior art LVDS example including transistors M 20 -M 23 , resistors R 3 and R 4 , and output driver 18 . The circuit of FIG. 2 provides improved efficiency over the circuit of FIG. 1 , because the “switch box” formed by transistors M 20 -M 23 steers current to the output more effectively. Due to the double termination provided by R 3 and R 4 , the effective impedance seen by the output driver 18 is 50 ohms differential. In the circuit of FIG. 2 , a 500 mV output swing can be produced from a 10 mA bias current. The currents I 0 , I 1 and I 2 illustrate operation of the circuit of FIG. 2 with transistors M 23 and M 21 turned on, transistors M 20 and M 22 turned off, and I 0 =10 mA.

Comparing the power consumption of the prior art serial interface driver circuits of FIGS. 1 and 2 , to produce a constant output voltage of 500 mV, and assuming a 2.5 V power supply, the circuit of FIG. 1 will have current and power requirements of 20 mA and 50 mW, and the circuit of FIG. 2 will have current and power requirements of 10 mA and 25 mW.

It is desirable in view of the foregoing to provide for serial communication interface drivers with current and power requirements that improve upon the performance of prior art serial communication interface drivers.

Exemplary embodiments of the invention provide a serial communication interface driver wherein the current steering switches are also used to provide termination impedances. The output voltage can be produced by a voltage-dividing current path between two regulated voltages, which provides improved efficiency.

Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or,” is inclusive, meaning and/or; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term “controller” means any device, system or part thereof that controls at least one operation. A controller may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with a controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases.

For a more complete understanding of the present invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which like reference numerals represent like parts:

FIG. 1 diagrammatically illustrates a CML serial interface driver according to the prior art;

FIG. 2 diagrammatically illustrates an LVDS serial interface driver according to the prior art;

FIG. 3 diagrammatically illustrates exemplary embodiments of a serial interface driver according to the invention;

FIG. 4 diagrammatically illustrates exemplary embodiments of the tunable switchable resistances of FIG. 3 ;

FIG. 5 diagrammatically illustrates exemplary embodiments of the primary switchable resistance circuit of FIG. 4 ;

FIG. 6 diagrammatically illustrates further exemplary embodiments of the primary switchable resistance circuit of FIG. 4 ;

FIG. 7 diagrammatically illustrates exemplary embodiments of the auxiliary switchable resistance circuits of FIG. 4 ;

FIG. 8 diagrammatically illustrates further exemplary embodiments of the auxiliary switchable resistance circuits of FIG. 4 .

FIG. 9 diagrammatically illustrates exemplary embodiments of a tuning control circuit for controlling the tunable switchable resistances of FIG. 3 ;

FIG. 10 illustrates exemplary operations which can be performed by the tuning control circuit of FIG. 9 ; and

FIG. 11 diagrammatically illustrates exemplary embodiments of a tuning control circuit which tunes the tunable switchable resistances of FIG. 3 based on variations in the termination resistance.

FIGS. 1 through 11 , discussed herein, and the various embodiments used to describe the principles of the present invention in this patent document are by way of illustration only and should not be construed in any way to limit the scope of the invention. Those skilled in the art will understand that the principles of the present invention may be implemented in any suitably arranged system.

Exemplary embodiments of the invention provide a voltage mode serial communication interface driver wherein the current steering switches also provide termination impedances. The output voltage is produced by a simple voltage divider between two regulated voltages (hence the foregoing phrase “voltage mode” driver), which results in more efficient operation than in the prior art serial interface driver circuits.

This is illustrated diagrammatically in FIG. 3 , wherein tunable switchable resistances shown generally at TSRT 1 , TSRT 2 , TSRB 1 and TSRB 2 provide both “switch box” current-steering functionality and termination impedances. These impedances, together with termination impedance R 3 , form voltage dividers which produce the output voltage across R 3 . When the data+ signal is active, TSRT 1 and TSRB 2 are activated to establish a voltage-dividing current path between the voltage Vtop produced by voltage regulator 304 and the voltage Vbot produced by voltage regulator 305 . The voltage-dividing current path extends from the voltage Vtop at 300 through top tunable switchable resistance TSRT 1 , termination resistor R 3 , and bottom tunable switchable resistance TSRB 2 . When the data+ signal is active, the complementary data-signal is inactive, so the top tunable switchable resistance TSRT 2 , and the bottom tunable switchable resistance TSRB 1 , are inactivated (and thus out of the circuit) while TSRT 1 and TSRB 2 are activated.

Conversely, when the data− signal is active and the data+ signal is inactive, the voltage-dividing current path extends from the output 300 of voltage regulator 304 through top tunable switchable resistance TSRT 2 , termination resistance R 3 , and bottom tunable switchable resistance TSRB 1 , to the output 301 of voltage regulator 305 , with TSRT 1 and TSRB 2 inactivated and out of the circuit.

In some embodiments, the tunable switchable resistances TSRT 1 , TSRT 2 , TSRB 1 and TSRB 2 are designed to present a resistance value of 50 ohms, and Vtop=3.3 volts and Vbot=1.3 volts. In such embodiments, and assuming again the same exemplary termination resistance R 3 =100 ohms as in FIGS. 1 and 2 above, the output voltage across the termination resistor R 3 is 1 volt at a current of 10 mA ((3.3−1.3)/(50+100+50)).

Considering again the 500 mV output example discussed above with respect to prior art FIGS. 1 and 2 , and again assuming a 2.5 volt power supply, if the switchable resistance values are set to 50 ohms, the arrangement of FIG. 3 requires 5 mA and 12.5 mW to produce a constant output voltage of 500 mV.

In some embodiments, the voltage regulators 304 and 305 use conventional folded cascode voltage reference topology. In one exemplary embodiment, Vtop=1.475 V and Vbot=925 mV, which produces an output voltage of 275 mV +/−125 mV and a common mode voltage of 1.2 V +/−0.250 V.

Exemplary embodiments of the invention recognize that resistance values in semiconductor devices can vary due to variable parameters such as PVT (process, voltage, temperature) variations. Accordingly, in some embodiments, the switchable resistances are tunable in order to compensate for variations in resistances due to such variable parameters. As shown in FIG. 3 , each of the top tunable switchable resistances TSRT 1 and TSRT 2 includes a tuning control input 31 driven by a tuning control signal TCT, and each of the bottom tunable switchable resistance TSRB 1 and TSRB 2 includes a tuning control input 32 driven by a tuning control signal TCB. The tuning control signals permit the resistance values presented by TSRT 1 , TSRT 2 , TSRB 1 and TSRB 2 to be suitably tuned (adjusted) to compensate for variations such as PVT variations.

FIG. 4 diagrammatically illustrates exemplary embodiments of the tunable switchable resistances TSRT 1 , TSRT 2 , TSRB 1 and TSRB 2 of FIG. 3 . As shown in FIG. 4 , each of the top tunable switchable resistances TSRT 1 and TSRT 2 , and each of the bottom tunable switchable resistances TSRB 1 and TSRB 2 , includes a primary switchable resistance circuit PSRC connected in parallel with a plurality of auxiliary switchable resistance circuits (ASRC 1 , ASRC 2 , . . . ASRCN). The data+/data− signals are input to PSRC and each of ASRC 1 -ASRCN. Also as shown in FIG. 4 , the tuning control signals TCT and TCB are composite signals that each comprise a plurality of individual control signals TCT 1 -TCTn and TCB 1 -TCBn. The individual control signals TCT 1 -TCTn (TCB 1 -TCBn) are input to the respective auxiliary switchable resistance circuits ASRC 1 -ASRCN.

In some embodiments, N=15, and the nominal impedance values provided by ASRC 1 -ASRCN are larger than the nominal impedance value provided by PSRC. In some embodiments, PSRC is designed to provide at least a desired resistance (e.g. 50 ohms) at the fast, cold (least resistance) corner, and ASRC 1 -ASRCN are designed so that PSRC together in parallel combination with all of ASRC 1 -ASRCN provides no more than the desired resistance at the opposite extreme, namely the slow, hot (highest resistance) corner. Various other parallel combinations of PSRC with one or more but less than all of the ASRCs can be used to provide various other composite impedance values that cover the range of PVT conditions between the fast, cold corner and the slow, hot corner.

FIG. 5 diagrammatically illustrates at PSRCT exemplary embodiments of the primary switchable resistance circuit PSRC of FIG. 4 , designed for use in the top tunable switchable resistances TSRT 1 and TSRT 2 of FIG. 3 . The primary switchable resistance circuit example of FIG. 5 includes an input inverter defined by transistors M 50 and M 51 , a pass gate defined by transistors M 52 and M 53 , and the actual switchable resistance as defined by transistor M 55 . The bulk contacts of the PMOS transistors M 52 , M 54 and M 55 are connected to the chip VDD 50 (for example 2.5 volts), and the bulk contact of PMOS transistor M 50 is connected to the core VDD 51 (for example 1 volt). The NMOS transistors M 51 and M 53 have their bulk contacts connected to VSS. The enable signal EN (and its complement EN′) permit the transistor M 55 to be selectively isolated from the data+ (data−) input. When the signal EN is high, the pass gate at M 52 , M 53 permits the gate of M 55 to be driven by an inverted version of the data+ (data−) input signal. When the EN signal is low, the pass gate M 52 , M 53 isolates transistor M 55 from the inverter M 50 , M 51 , and the PMOS transistor M 54 pulls the gate of transistor M 55 up to chip VDD 50 to ensure that the transistor M 55 is completely off (high impedance state) and thus removed from the circuit of FIG. 3 . In some embodiments, the transistors M 50 -M 55 are sized as follows:

FIG. 6 diagrammatically illustrates at PSRCB exemplary embodiments of the primary switchable resistance circuit PSRC of FIG. 4 , designed for use in the bottom tunable switchable resistances TSRB 1 and TSRB 2 of FIG. 3 . The PSRCB of FIG. 6 is generally similar to the PSRCT of FIG. 5 , except the PMOS transistor M 55 of FIG. 5 is replaced in FIG. 6 with PMOS transistor M 65 having a channel width of 110 u. Also, the bulk contact of transistor M 65 is connected to the source thereof in order to reduce the body effect and improve the “on” resistance of transistor M 65 .

FIG. 7 diagrammatically illustrates at ASRCTn exemplary embodiments of the auxiliary switchable resistance circuits ASRC 1 -ASCRn, designed for use in the top tunable switchable resistances TSRT 1 and TSRT 2 of FIG. 3 . As used herein, n can take the values of 1, 2, . . . N. The ASRCT illustrated in FIG. 7 is generally similar to the PSRCT illustrated in FIG. 5 , except the enable signal EN (EN′) of FIG. 5 is replaced by the corresponding portion of the tuning control signal TCT, namely TCTn and its complement TCTn′. Also, the transistors M 70 -M 75 of the ASRCT of FIG. 7 are sized differently than the corresponding transistors M 50 -M 55 of FIG. 5 . In some embodiments, the transistors of FIG. 7 are sized as follows:

FIG. 8 diagrammatically illustrates at ASRCBn exemplary embodiments of the auxiliary switchable resistance circuits ASRC 1 -ASRCn of FIG. 4 , designed for use in the bottom tunable switchable resistances TSRB 1 and TSRB 2 of FIG. 3 . The ASRCB of FIG. 8 is similar to the ASRCT of FIG. 7 , except the tuning control signal TCTn (TCTn′) of FIG. 7 is replaced by the corresponding portion of the tuning control signal TCB, namely TCBn and its complement TCBn′. The output transistor M 85 has its bulk contact connected to its source, in generally similar fashion to the bulk connection of transistor M 65 in the PSRCB of FIG. 6 . Also, in some embodiments, the sizes of transistors M 80 -M 85 in FIG. 8 differ from the sizes of transistors M 70 -M 75 of FIG. 7 . More specifically, in some embodiments, the transistors M 80 -M 85 of FIG. 8 are sized as follows:

FIG. 9 diagrammatically illustrates exemplary embodiments of a tuning control circuit for producing the tuning control signal TCT used to tune the top tunable switchable resistances TSRT 1 and TSRT 2 of FIG. 3 , and the tuning control signal TCB used to tune the bottom tunable switchable resistances TSRB 1 and TSRB 2 of FIG. 3 . As described above with respect to FIGS. 3 and 4 , in order to tune TSRT 1 , TSRT 2 , TSRB 1 and TSRB 2 appropriately such that each one presents an impedance that is substantially invariant over all operating conditions, each one is constructed as a parallel-connected array including a primary switchable resistance circuit PSRC and a plurality of auxiliary switchable resistance circuits ASRC 1 -ASRCN. In some embodiments, ASRC 1 -ASRCN of a given TSRT or TSRB are designed to have equal impedances, and in other embodiments, ASRC 1 -ASRCN are designed so that their respective impedances represent binary weighted impedances. In any event, the impedances presented by the tunable switchable resistances can be changed by varying the number of ASRCs that are activated. The greater the number of ASRCs activated, the smaller the (nominal) impedance presented by the tunable switchable resistance, and vice versa.

In some embodiments, the primary switchable resistance circuit PSRC is designed such that its impedance is greater than the desired impedance at the PVT corner where the PMOS device impedance is lowest. The auxiliary switchable resistance circuits ASRC 1 -ASRCN are designed to have respective impedances such that they can be switched into parallel combination with the PSRC to achieve a desired impedance resolution. The total number of ASRCs is chosen such that the impedance when all ASRCs are connected in combination with the PSRC is less than the desired impedance at the PVT corner where the PMOS device impedance is highest. These exemplary design criteria ensure that each tunable switchable resistance can be calibrated to a desired impedance value at any set of PVT conditions.

The tuning control circuit of FIG. 9 utilizes two bandgap generated currents. One is a constant current Ik that is substantially invariant relative to PVT conditions, and the other is a current Ipoly which is inversely proportional to the poly sheet resistance of the semiconductor integrated circuit. The current Ipoly is passed through a poly resistor 91 , and thus generates a reference voltage Vref that is substantially invariant relative to PVT conditions. The constant current Ik flows through a control impedance. In some embodiments, the control impedance is constructed as a replica of the tunable switchable resistance that will be tuned. For example, in FIG. 9 , the current Ik flows through a control impedance 92 that is a replica of the top tunable switchable resistance TSRT, and the current Ik also flows through a control impedance 93 that is a replica of the bottom tunable switchable resistance TSRB. The current Ipoly, the poly resistor 91 , and the constant current Ik can be designed such that, when the voltage drop across the control impedance at 92 or 93 is equal to the voltage drop across the poly resistor 91 (Vref), the control impedance 92 or 93 is presenting the desired impedance (for exampled 50 ohms).

Respective comparators compare the voltage drops across the control impedances 92 and 93 to the reference voltage Vref. Tuning control logic (e.g. DSP logic) 94 is responsive to the comparators for generating control signals 95 and 96 . In embodiments that use TSRT and TSRB replica impedances at 92 and 93 , the controls signals 95 and 96 would be TCT and TCB. The control signals 95 and 96 adjust the impedances presented by the control impedances 92 and 93 to the point where the voltage drops across the control impedances are equal to the reference voltage Vref. In embodiments that use replicas of TSRT and TSRB as the control impedances 92 and 93 , the configurations of TCT and TCB that produce voltage drops of Vref across the respective replicas are also output by tuning control logic 94 to the TSRTs and TSRBs of FIG. 3 . This ensures that the tunable switchable resistances of FIG. 3 will provide the desired resistance under the current PVT conditions.

FIG. 10 illustrates exemplary operations which can be performed according to exemplary embodiments of the invention. As shown in FIG. 10 , the PSRC and all of the ASRCs are initially activated at 101 , so that the replica TSRT at 92 (or TSRB at 93 ) will present the lowest possible impedance. At 102 , the voltage across the replica impedance is compared to the reference voltage. If the voltage across the replica impedance is less than the reference voltage at 103 , then the impedance is too low, so one of the ASRCs is deactivated at 104 , after which operations return to 102 . When it is determined at 103 that the voltage drop across the replica impedance is greater than or equal to the reference voltage, the active/inactive status of all TCT (or TCB) bits currently controlling the replica impedance is recorded at 105 . It is thereafter determined at 106 whether an averaging technique is to be utilized. If not, then operations are completed at 107 .

If it is determined at 106 that averaging is to be utilized, then the operations at 101 - 105 can be repeated until it is determined at 108 that the averaging operation is finished. Thereafter, the average number of active TCT (or TCB) bits from all of the averaging passes is computed at 109 . This average number of active bits can then be utilized to produce the TCT/TCB signals for tuning the corresponding tunable switchable resistances of FIG. 3 .

FIG. 11 diagrammatically illustrates exemplary embodiments of a tuning control circuit for tuning the tunable switchable resistances of FIG. 3 based on variations in the termination resistance R 3 . The tuning control circuit of FIG. 11 exploits the fact that the serial communication interface driver of FIG. 3 utilizes a simple voltage divider circuit to generate the output voltage across termination resistance R 3 . Considering the aforementioned exemplary embodiments where R 3 =100 ohms and where the tunable switchable resistances are each designed to present 50 ohms, each of TSRT 1 , TSRT 2 , TSRB 1 and TSRB 2 will account for one-fourth of the total voltage drop between the voltage Vtop produced by the top voltage regulator 304 and the voltage Vbot produced by the bottom voltage regulator 305 .

Accordingly, and as shown in FIG. 11 , four resistors R 4 having the same resistance value are connected in series with one another between the voltage Vtop and the voltage Vbot. In this arrangement, and with data+ or data− active in FIG. 3 , the voltages at 110 and 111 should be the same as the respective voltages at 302 and 303 in FIG. 3 . Accordingly, a comparator 112 is used to compare the voltage at 110 to the voltage at 302 , and a comparator 113 is used to compare the voltage at 111 to the voltage at 303 . Tuning control logic (e.g. DSP logic) 114 is responsive to the outputs of comparators 112 and 113 for suitably adjusting the tuning control signals TCT and TCB to bring the voltages 302 and 303 to the respectively desired levels defined at 110 and 111 . As shown in FIG. 11 , the tuning control logic 114 can, in some embodiments, utilize a control strobe to control the timing of the comparator operations.

The tuning control circuit of FIG. 11 permits the tunable switchable impedances TSRT 1 , TSRT 2 , TSRB 1 and TSRB 2 to be adapted to match the actual external termination impedance R 3 which, for a nominal value of 100 ohms can easily vary from 80 ohms to 120 ohms. This matching provides improved performance with respect to reflections, signal integrity and jitter.

Referring again to the control signals TCT and TCB described with respect to FIGS. 3 , 4 , and 7 - 11 , in some embodiments, the tuning control circuits of FIGS. 9-11 run continuously, periodically updating the tuning control signals TCT and TCB to adjust the impedance as operating conditions change. In order to avoid the possibility of increased jitter or bit errors due to the enabling of transistors during data transitions, some embodiments provide the tuning control signals TCB and TCT as thermometer-coded signals such that only one TCT/TCB bit (and thus only one of the transistors M 75 /M 85 ) at a time can change state.

Although exemplary embodiments of the invention are disclosed with PMOS transistors providing switchable impedances, it will be evident to workers in the art that the switchable impedances can also be implemented with NMOS transistors or combinations of NMOS and PMOS transistors.

Although the present invention has been described with exemplary embodiments, various changes and modifications may be suggested to one skilled in the art. It is intended that the present invention encompass such changes and modifications as fall within the scope of the appended claims.