Semiconductor memory device and method of arranging signal and power lines thereof

This application claims the benefit of priority to Korean Patent Applications P2004-40542, filed Jun. 3, 2004, and P2004-74730, filed Sep. 17, 2004, the disclosures of which are incorporated herein by reference.

1. Field of the Invention

The present invention relates to dynamic random access memory (DRAM) semiconductor devices, and more particularly to methods and apparatus for routing power and signal traces in patterned metal layers overlying such devices.

2. Description of the Related Art

DRAM devices include a memory array, circuitry to access the memory array, and peripheral circuitry to control DRAM operation and communicate with external devices. Typical memory arrays are formed of a repeating pattern of sub memory cell arrays interspersed with a portion of the circuitry used to access the memory array. The remainder of the access circuitry is generally located in a row decoder and a column decoder located at the edges of the memory array.

FIG. 1 shows a typical memory arrangement 100 , comprising a memory array 10 , a column decoder 20 , and a row decoder 30 . The memory array 10 is arranged somewhat like a checkerboard, with sub memory cell arrays (SMCAs) separated vertically by sub word line drivers (SWDs) and separated horizontally by sense amplifiers (SAs) for the memory cells. Each of the sub memory cell arrays comprises a plurality of memory cells (MC), each of which is composed of an access transistor enabled by a sub word line (SWL) and a capacitor to store data. The SAs are separated vertically by conjunction regions (CJs) that contain control signal generation circuitry for the SAs.

The column decoder 20 generates signals on column select lines (CSLs) to select one or more columns of the array for reading or writing according to a supplied column address (CA).

The row decoder 30 responds to a supplied row address to activate memory cells in a row of the array, by selecting one of a plurality of main word line (NWE) and word line select (PX) signals.

Further aspects of FIG. 1 will be explained in conjunction with FIG. 2 , which shows further detail of a portion of array 10 . Two memory cells MC 1 and MC 2 are shown respectively in SMCA 1 and SMCA 2 . Each memory cell comprises a capacitor C connected between a cell plate voltage (Vp) and the source of an access transistor N. Generally, Vp is half of the power supply voltage. The gate of each access transistor (N) is controlled by a corresponding sub word line (SWL), with SWL 1 controlling the MC 1 access transistor and SWL 2 controlling the MC 2 access transistor.

The drain of each access transistor is connected to a corresponding bit line (BL), e.g., BL 1 for MC 1 and BL 2 for MC 2 . Each bit line also connects to other memory cells (not shown) in the respective SMCAs, with access transistors (not shown) connected to other SWLs. A sense amplifier region SA 1 resides between SMCA 1 and SMCA 2 . Referring to SMCA 1 , BL 1 and BL 1 B connect to a precharge circuit PRE 1 in SA 1 , and connect to a pair of sensing bit lines SBL and SBLB through a bit isolation gate ISO 1 . As to SMCA 2 , BL 2 and BL 2 B connect to a precharge circuit PRE 2 in SA 1 , and connect to the pair of sensing bit lines SBL and SBLB through a bit isolation gate ISO 2 . A bit line sense amplifier BLSA and a data input/output gate IOG also connect to sensing bit lines SBL and SBLB.

The bit line sense amplifier amplifies the voltage difference between BL 1 and BL 1 B of the MC 1 memory cell, for instance, in the following sequence, where the memory cell represents one of two logic states (multi-state memory cells also exist and typically use more complicated sense amplifier circuitry). Isolation gate ISO 1 connects BL 1 to SBL and BL 1 B to SBLB. Precharge circuit PRE 1 charges BL 1 and BL 1 B to a voltage midway between the voltage of a discharged capacitor C (representing, for example, logic 0) and the voltage of a charged capacitor C (representing in the same example logic 1). SWL 1 is energized to couple the MC 1 memory cell capacitor to BL 1 . When the cell capacitor was discharged, charge sharing causes the voltage on BL 1 to decrease relative to BL 1 B. When the cell capacitor was charged, charge sharing causes the voltage on BL 1 to increase relative to BL 1 B. After charge sharing is completed, the isolation gate ISO 1 is enabled so that a slight voltage difference between the bit lines BL 1 /BL 1 B is transferred to the sensing bit lines SBL 1 /SBL 1 B. In either case, sense amplifier BLSA is activated during a predetermined period to sense and amplify the slight voltage difference between the bit lines BL 1 /BL 1 B.

Input/output gate IOG, when activated, couples SBL and SBLB to a pair of local input/output lines LIO and LIOB, which also connect to other IO gates in other SA regions (not shown) above and below SA 1 . Herein, the input/output gate IOG is activated responsive to column select line CSL (not shown). A local global input/output gate LGIOG serves to selectively couple LIO and LIOB to a pair of global input/output lines GIO and GIOB when LIO and LIOB are active. Thus the sensed memory cell state is coupled to a peripheral input/output circuit.

From FIGS. 1 and 2 , it can be appreciated that a large number of conductors are routed over memory array 10 . NWE lines route vertically across the array over the sub memory cell arrays, and PX, LIO, and LIOB lines route vertically across the array over the conjunction regions and sense amplifier regions. CSL, GIO, and GIOB lines route horizontally across the array over the sub memory cell arrays. Not shown are power conductors, which must also be routed over the array to provide power for the circuitry in the SA, CJ, and SWD regions.

FIG. 3 shows a region of memory array 10 , with underlying circuit details omitted and overlying metal traces illustrated. On a first metal layer, LIO, PX, and NWE traces are spaced with first power lines P 1 that supply power at different voltage levels needed by the array circuitry. Some of the first power lines P 1 may comprise ground potential voltage lines (VSS) and power supply lines (VCC). Other lines of the first power lines PI may comprise a reference voltage line (Vref), a negative power line (VBB), a boosting voltage line (VPP), etc. On a second metal layer, CSL and GIO traces are spaced with second power lines P 2 that supply power at the different voltage levels. Some of the second power lines P 2 may also comprise ground potential voltage lines (VSS) and power supply lines (VCC). Other lines of the second power lines P 2 may comprise a reference voltage line (Vref), a negative power line (VBB), a boosting voltage line (VPP), etc. Where a P 2 trace overlies a P 1 trace of the same voltage level, the two traces are connected to each other to create a grid. The P 2 traces connect to power supplies located outside of the memory array area of the DRAM device.

FIG. 4 shows a simplified block diagram of the row decoder 30 of FIG. 1 . Row decoder 30 comprises a row address decoder area 30 - 1 and a row address predecoder area 30 - 2 . Within row address decoder area 30 - 1 , each of the illustrated first decoder areas RD 1 generates a word line select signal PX and each of the illustrated second decoder areas RD 2 generates a main word line signal NWE responsive to row addresses RA and pre-decoding row addresses DRA, which are generated in turn by row address predecoder 30 - 2 .

FIG. 5 illustrates a portion of row decoder 30 with the underlying circuit details omitted and overlying metal traces illustrated. Overlying a first decoder area RD 1 on a first metal layer, signal lines S 1 (e.g., PX lines) are flanked by first power lines PVINT 1 and PVSS 1 . Overlying a second decoder area RD 2 on the first metal layer, signal lines S 1 (e.g., NWE lines) are flanked by additional first power lines PVINT 1 and PVSS 1 .

A second metal layer contains signal lines S 2 (e.g., RA and DRA lines) and second power lines PVINT 2 and PVSS 2 . PVINT 2 connects to PVINT 1 where the two overlap, and PVSS 2 connects to PVSS 1 where the two overlap. The PVINT 2 and PVSS 2 traces connect to power supplies located outside of the memory array area of the DRAM device. Under this condition, the power lines cannot be designed with wider lines without increasing the chip area.

As DRAM devices scale to smaller cell dimensions and/or increase the number of cells in a memory array, more signal lines are routed over the memory array and row decoder per unit area in essentially the same area that previously served a smaller number of signal lines. The width of the power lines is therefore decreased proportionally to accommodate the denser array. Decreasing power line width is undesirable, however, as decreased power line width results in greater resistance to current flow, greater voltage drop and power consumption, and reduced power supply stability as current demands fluctuate. The various signal and power lines are also packed closer together as the device scales to smaller dimensions, resulting in an undesirable crosstalk between adjacent lines.

The embodiments described herein adopt a triple-metal-layer DRAM design that improves signal and power line routing considerably as opposed to a dual-metal-layer design. Although others have proposed various schemes to route signals over a memory array using three metal layers, it is believed that the present design addresses the problem with particular attention to the power supply issue, and thus produces a group of novel metal layer arrangements that scale well to smaller cell sizes.

FIG. 1 illustrates a general prior art memory array and row/column decoder arrangement for a DRAM memory device;

FIG. 2 illustrates an enlarged view of a portion of the FIG. 1 memory array, showing additional circuit and signal line details;

FIG. 3 also illustrates an enlarged view of a portion of the FIG. 1 memory array, this time with particular attention to the signal and power trace routing layout for the two metal layers overlying the memory array;

FIG. 4 illustrates an enlarged view of a portion of the FIG. 1 row decoder, showing additional circuit and signal line details;

FIG. 5 also illustrates an enlarged view of a portion of the FIG. 1 row decoder, this time with particular attention to the signal and power trace routing layout for the two metal layers overlying the row decoder;

FIGS. 6–10 illustrate several embodiments showing triple-metal-layer signal and power line routing over a memory array;

FIG. 11–14 illustrate several embodiments showing triple-metal-layer signal and power line routing over a row decoder; and

FIGS. 15 and 16 illustrate several embodiments showing triple-metal-layer signal and power line routing over a column decoder.

The following embodiments use three metal layers over a memory array, row decoder, and/or column decoder. Wider power lines are generally possible with these embodiments, improving power distribution and stability. Various advantages of the embodiments will become apparent from the description of the figures presented below.

FIG. 6 illustrates a first embodiment with signal and power lines routed over a memory array using three layers of metal. The first metal layer contains NWE, PX, LIO signal lines and P 1 power lines, similar to the prior art. The second metal layer contains CSL and GIO signal lines, and no power lines. The third metal layer contains power lines P 3 perpendicular to the P 1 power lines formed with the first metal layer. The P 3 power lines can be made wider than the prior art P 2 power lines formed with the second metal layer because the CSL and GIO lines do not compete for the metal 3 area overlying the memory array. Although for purposes of clarity the feature is not illustrated in FIG. 6 , portions of the P 3 lines can even directly overlie CSL and GIO lines. Connections to power lines P 1 exist in clearances where a P 3 line overlies a P 1 line of the same voltage, and may use a via contact (direct connection between the third metal and the first metal) or intermediate P 2 pad (not shown) to connect to metal 1 . The P 3 lines thus can be routed with reduced resistance and improved power distribution. Spacing between CSL and GIO lines can also be improved due to the lack of P 2 traces, reducing crosstalk and improving signal propagation speed.

FIG. 7 illustrates a second embodiment with signal and power lines routed over a memory array using three layers of metal. In this embodiment, P 1 lines do not exist on metal 1 , and P 2 lines parallel to CSL and GIO on metal 2 distribute power to the memory array circuitry. P 3 lines are arranged on metal 3 , perpendicular to the P 2 lines and connecting to the P 2 lines where a P 3 line and a P 2 line of the same voltage level cross. The P 2 lines can remain relatively thin, while the P 3 lines can be made relatively wide to efficiently carry current to the vicinity where it will be needed.

FIG. 8 illustrates a third embodiment with signal and power lines routed over a memory array using three layers of metal. In this embodiment, thin P 1 power lines are crossed by thin P 2 power lines. P 1 and P 2 lines of the same voltage level connect where they cross. Wider P 3 power lines are routed parallel to the P 2 lines, and generally overlap the P 2 lines of the same voltage level. As the P 3 and P 2 lines overlap along their length, connection between the two lines can be made in long channels or in more frequent, abbreviated vias. The P 3 /P 2 structures have lower resistance per unit length while occupying far less space on the metal layer shared with CSL and GIO.

FIG. 9 illustrates a fourth embodiment with signal and power lines routed over a memory array using three layers of metal. In this embodiment, metal 1 contains thin P 1 power lines routed parallel to NWE lines. Metal 2 contains thin P 2 power lines routed perpendicular to the P 1 power lines and parallel to CSL and GIO lines. Where a P 2 power line crosses a P 1 power line of the same voltage level, the two power lines connect. Metal 3 contains relatively wide P 3 power lines parallel to the P 1 power lines, and preferably routed so as to overlap an underlying P 1 line of the same voltage level. Where a P 3 power line crosses a P 2 power line of the same voltage level, the two power lines connect.

FIG. 10 illustrates a fifth embodiment with signal and power lines routed over a memory array using three layers of metal. This embodiment is similar to the third embodiment ( FIG. 8 ), but the GIO lines are routed on metal 3 instead of metal 2 . This can be an attractive alternate, since overlapping P 2 and P 3 lines can function together as a single conductor with reduced resistance, allowing P 3 to be less wide and leaving room for signal lines on metal 3 . Therefore, the line pitch between CSLs may be larger so that coupling noise can be reduced.

Preferably, but not necessarily, in conjunction with one of the previous embodiments, various embodiments are also provided for routing signal and power lines overlying a row decoder. FIG. 11 illustrates a first row decoder embodiment. Relatively thin power lines PVINT 1 , PVSS 1 are provided on a first metal layer to provide power to underlying row decoder circuitry. For instance, PVINT 1 and PVSS 1 power lines are arranged running from top to bottom towards an outboard area of row decoder area RD 1 , leaving an interior section overlying RD 1 for running signal lines S 1 in first metal. Other row decoder signal lines S 2 are formed on second metal, running perpendicular to the PVINT 1 , PVSS 1 , and S 1 lines. On third metal, relatively wide power lines PVINT 3 and PVSS 3 run parallel to the S 2 lines, with each of PVINT 3 and PVSS 3 overlapping one or more of the signal lines S 2 . Where PVINT 3 overlaps PVINT 1 but not S 2 , a connection is made between the two power lines. Similarly, where PVSS 3 overlaps PVSS 1 but not S 2 , a connection is made between the two power lines. The connection may involve a via partially filled with metal 2 , but no continuous metal 2 power lines exist in the embodiment. The connection may be made directly between metal 3 and metal 1 (via a contact). Advantageously, this arrangement allows extra room on metal 2 to spread or increase the number of lines S 2 , and also provides for power distribution through metal 3 power lines with a much larger cross-section than the prior art metal 2 power lines.

FIG. 12 illustrates a second row decoder embodiment similar to FIG. 11 , but employing additional power lines PVINT 2 and PVSS 2 on metal 2 running parallel to and outboard of signal lines S 2 . Where PVINT 2 overlaps PVINT 1 , a connection is made between the two power lines, and similar connections are made between PVSS 2 and PVSS 1 . PVINT 3 overlaps PVINT 2 (and can also overlap one or more signal lines S 2 ), with connection made between PVINT 3 and PVINT 2 where the two lines overlap. This connection can be an elongated channel or a series of more abbreviated vias spaced along the length of PVINT 3 and PVINT 2 . A similar arrangement and connection exists between PVSS 3 and PVSS 2 .

FIG. 13 illustrates a third row decoder embodiment similar to FIG. 11 . PVINT 1 and PVSS 1 are placed centrally, however, above row decoder area RD 1 , with signal lines S 1 located outboard of PVINT 1 and PVSS 1 . Herein, PVINT 2 and PVSS 2 do not exist on the second metal layer.

FIG. 14 illustrates a fourth row decoder embodiment similar to FIG. 12 . PVINT 1 and PVSS 1 are placed centrally, however, above row decoder area RD 1 , with signal lines S 1 located outboard of PVINT 1 and PVSS 1 . Herein, PVINT 2 and PVSS 2 exist on the second metal layer with the signal line S 2 .

Preferably, but not necessarily, in conjunction with one of the previous embodiments, various embodiments are also provided for routing signal and power lines overlying a column decoder. FIG. 15 illustrates a first column decoder embodiment useful, for instance, with the embodiment of FIG. 10 having GIO lines placed on metal 3 . A column decoder 20 ′ uses signal lines S 1 and power lines PVINT 1 and PVSS 1 located on metal 1 , and signal lines S 2 and power lines PVINT 2 and PVSS 2 located on metal 2 over the metal 1 . On metal 3 , however, the metal 3 GIO lines (and optionally metal 3 power lines, not shown, to supply power to the memory array) overlying the memory array continue directly over the column decoder toward a peripheral I/O circuit (not shown).

FIG. 16 illustrates a second column decoder embodiment similar to FIG. 15 , where GIO lines route over the column decoder on metal 3 . Just past the column decoder, however, each GIO line connects through a via to a GIO line continuing over the memory array on metal 2 , e.g., as depicted in FIGS. 6–9 .

Those skilled in the art will recognize that many other routing permutations can be envisioned that fall within the general framework of the described embodiments. Absolute line widths and spacings have not been discussed, as these are generally a function of device and process requirement. Such minor modifications and implementation details are encompassed within the embodiments of the invention, and are intended to fall within the scope of the claims.

The preceding embodiments are exemplary. Although the specification may refer to “an”, “one”, “another”, or “some” embodiment(s) in several locations, this does not necessarily mean that each such reference is to the same embodiment(s), or that the feature only applies to a single embodiment.