SRAM core cell for light-emitting display

This application claims priority to and the benefit of Korean Patent Application No. 10-2004-0036868 filed on May 24, 2004 in the Korean Intellectual Property Office, the entire content of which is incorporated herein by reference.

(a) Field of the Invention

The present invention relates to a static RAM (SRAM) core cell. More specifically, the present invention relates to a SRAM core cell for a light-emitting display, and is applicable to a data driver of an organic electro-luminescence (EL) light-emitting display device.

(b) Description of the Related Art

The organic EL light-emitting display is a device for displaying an image by controlling a current flowing to an organic material that emits light when the current flows to it. In the organic EL light-emitting display, the organic material is divided by pixels and arranged in a matrix form. The organic EL light-emitting display is promising as a next-generation display device because of its advantages such as low-voltage driving requirement, light weight, slim design, wide viewing angle, rapid response, etc.

FIG. 1 illustrates the principle of light emission of a typical organic EL.

In general, an organic EL light-emitting display, which is a display device that electrically excites a fluorescent organic compound to emit light, drives N×M organic light-emitting cells by voltage or current to represent an image. The organic light-emitting cell has a structure of FIG. 1 that includes an ITO (Indium Tin Oxide) pixel electrode, an organic thin film, and a metal layer. The organic thin film is a multi-layer structure that includes a light-emitting layer (EML), an electron transport layer (ETL), and a hole transport layer (HTL) to keep electrons and holes in good balance and enhance the light-emitting efficiency. The organic thin film may also include an electron injecting layer (EIL) and a hole injecting layer (HIL).

There are typically two driving methods for the organic light-emitting cells: the passive matrix method and the active matrix method using TFTs. The passive matrix method involves selectively driving anode and cathode lines arranged orthogonally to each other, while the active matrix method involves coupling TFTs and capacitors to the respective pixel electrodes and sustaining a voltage according to a capacitor capacity.

FIG. 2 is a schematic block diagram of a typical organic EL display device.

Referring to FIG. 2 , the organic EL display device includes a video controller 210 , a panel controller 220 , a power module 230 , a scan driver 240 , a data driver 250 , and an organic EL panel 260 . The scan driver 240 and the data driver 250 supply various signals to the organic EL panel 260 in the column and row directions via analog and digital interfaces, respectively.

More specifically, various analog signals such as R, G, and B signals and sync signals are fed into the video controller 210 and converted into digital signals. The panel controller 220 controls the converted digital signals and supplies them to the scan driver 240 and the data driver 250 in sequence. The organic EL panel 260 drives N×M organic light-emitting cells by voltage or current using the signals supplied from the scan driver 240 and the data driver 250 , and the power supplied from the power module 230 to represent an image.

FIG. 3 shows a general active matrix organic EL display panel using TFTs.

Referring to FIG. 3 , the organic EL display device includes an organic EL display panel 310 , a data driver 320 , and a scan driver 330 .

The organic EL display panel 310 includes m data lines D 1 , D 2 , . . . , Dm arranged in columns; n scan lines S 1 , S 2 , . . . , Sn arranged in rows; and n×m pixel circuits. The m data lines D 1 , D 2 , . . . , Dm transfer data signals representing image signals to the pixel circuits, and the n scan lines S 1 , S 2 , . . . , Sn transfer selection signals to the pixel circuits. Each pixel circuit is formed in one pixel area 310 - 1 defined by two adjacent ones of the m data lines D 1 , D 2 , . . . , Dm, and two adjacent ones of the n scan lines S 1 , S 2 , . . . , Sn. The pixel circuit includes, for example, transistors 311 and 312 , a capacitor 313 , and an organic EL diode 314 . Here, reference numeral 315 denotes a power voltage Vdd.

More specifically, each pixel circuit 310 - 1 includes the organic EL diode (OLED) 314 , two transistors 311 and 312 , and the capacitor 313 . For example, the two transistors 311 and 312 may be PMOS transistors.

The driving transistor 312 has its source coupled to the power voltage V dd , and the capacitor 313 coupled between its gate and source. The capacitor 313 sustains the gate-source voltage of the driving transistor 312 for a predetermined time period, and the switching transistor 311 transfers a data voltage from the data line Dm to the driving transistor 312 in response to the selection signal from the current scan line Sn.

The organic EL diode 314 has its cathode coupled to a reference voltage V ss , and emits a light corresponding to a current applied through the driving transistor 312 . Here, the power V ss coupled to the cathode of the organic EL diode 314 is lower than the power V dd and can be a ground voltage.

The scan driver 330 sequentially applies the selection signal to the n scan lines S 1 , S 2 , . . . , Sn, while the data driver 320 sequentially applies a data voltage corresponding to the image signal to the m data lines D 1 , D 2 , . . . , Dm.

The scan driver 330 and/or the data driver 320 may be coupled to the organic EL display panel 310 , or mounted as a chip in a tape carrier package (TCP) soldered and coupled to the organic EL display panel 310 . Alternatively, the scan driver 330 and/or the data driver 320 may be mounted as a chip in a flexible printed circuit (FPC) or a film soldered and coupled to the display panel 310 .

Moreover, the scan driver 330 and/or the data driver 320 may be directly mounted on a glass substrate of the organic EL display panel 310 , or substituted by driver circuitry including the same layers of the scan lines, the data lines, and the TFTs on the glass substrate.

FIG. 4 is a circuit diagram of a CMOS SRAM core cell according to prior art.

The CMOS SRAM core cell according to prior art is used with the data driver 320 to implement the organic EL display device as an SOP (System On Package), and is designed as a SRAM having six TFTs. The SRAM stores the data to be displayed on the organic EL panel 260 .

Referring to FIG. 4 , symbols “MP 1 ” and “MP 2 ” denote pull-up transistors, symbols “MN 1 ” and “MN 2 ” denote pull-down transistors, and symbols “MP 3 ” and “MP 4 ” denote pass transistors for a data access. Here, MP 1 to MP 4 are PMOS transistors, and MN 1 and MN 2 are NMOS transistors. The MP 1 and the MN 1 , and the MP 2 and the MN 2 are implemented as CMOS transistors and arranged in a latch configuration.

In the CMOS RAM core cell according to prior art, a plurality of NMOS and PMOS transistors must be formed with a predetermined width and a predetermined length, with a restriction on a design of the layout, allowing no flexibility of design and causing defects in the fabrication process.

In one embodiment, the present invention is a SRAM core cell for a light-emitting display that has an enhanced integration level of a defined layout space by forming the gate channel of a thin film transistor (TFT) constituting the SRAM core cell in an oblique direction.

In one embodiment, the present invention is a SRAM core cell for a light-emitting display that secures a process margin to prevent defects in the fabrication process by enhancing the efficiency of a defined layout space.

In one aspect of the present invention, there is provided a static RAM (SRAM) core cell for a light-emitting display includes a plurality of thin film transistors each having a gate, a source, and a drain as a data memory for a data driver of the light-emitting display. The SRAM core cell includes switching transistors and data memory transistors. The switching transistors are coupled to a bit line and a word line so as to select writing or reading of data. The data memory transistors are coupled to a power voltage (Vdd) or a ground voltage (Vss) so as to enable writing and reading of data. The bit line and the word line are formed in first and second directions, respectively. The channels of the switching transistors and the data memory transistors are formed in an oblique direction with respect to the first and second directions, respectively.

Here, the oblique direction is a clockwise direction or a counterclockwise direction with respect to the first or second direction.

The switching transistors or the data memory transistors arranged in an oblique direction include a polysilicon layer deposited in an oblique direction on a substrate.

In another aspect of the present invention, a SRAM core cell includes six thin film transistors each having a gate, a source, and a drain. The SRAM core cell includes a first switching transistor, a second switching transistor, and first to fourth data memory transistors. The first switching transistor has a gate coupled to a word line, and a source/drain coupled to a first bit line to select an input to the first bit line according to an input signal to the word line. The second switching transistor has a gate coupled to the word line, and a source/drain coupled to a second bit line to select an input to the second bit line according to an input signal to the word line. The first to fourth data memory transistors are coupled to a power voltage or a ground voltage to enable writing or reading of data under the control of the first and second switching transistors. The bit lines and the word line are formed in first and second directions, respectively. The channels of the first and second switching transistors and the first to fourth data memory transistors are formed in an oblique direction with respect to the first and second directions, respectively.

Here, the first and second switching transistors and the first to fourth data memory transistors are arranged in sequence on a layout space of a predetermined area.

In still another aspect of the present invention, a semiconductor device includes a substrate and a plurality of transistors each having a gate and a source/drain formed on an active region deposited on the substrate. The channels of the transistors formed on the active region are formed in an oblique direction with respect to a layout width or length direction on a layout space of a predetermined area.

Here, the oblique direction is a clockwise direction or a counterclockwise direction with respect to the layout width or length direction.

The channels of the transistors formed on the active region and arranged in an oblique direction are preferably arranged in sequence. The transistors arranged in an oblique direction on the active region include a polysilicon layer deposited in an oblique direction with respect to a vertical direction on the substrate.

In one embodiment, the present invention arranges transistors in sequence so as to form a polysilicon layer or channels forming the transistors in an oblique direction in a defined region in designing a SRAM for a data driver of a light-emitting display, thereby enhancing the layout efficiency of the core cell and implementing a light-emitting display device of a high integration level.

The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate an embodiment of the invention, and, together with the description, serve to explain the principles of the invention.

FIG. 1 illustrates the principle of light emission of an organic EL display device.

FIG. 2 is a schematic block diagram of an organic EL display device.

FIG. 3 shows a general active matrix organic EL display panel using TFTs.

FIG. 4 is a circuit diagram of a CMOS SRAM core cell for an EL display device.

FIG. 5 shows a layout of a CMOS RAM core cell for a light-emitting display according to an embodiment of the present invention.

FIG. 6 is a circuit diagram showing the layout part taken in an oblique direction in the CMOS RAM core cell shown in FIG. 5 .

FIG. 7 is a diagram specifically showing the layout taken in an oblique direction in the CMOS RAM core cell according to an embodiment of the present invention in an oblique direction.

Hereinafter, a SRAM core cell for a light-emitting display according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

Referring to FIG. 4 , a SRAM core cell includes two flip-flop circuits for memory (e.g., MP 1 and MN 1 , and MP 2 and MN 2 ), and two switches (e.g., MP 3 and MP 4 ). By applying pulses to word lines to turn a cell transistor on, data transfer is activated between a bit line pair (“Bit” and “Bitb”) and flip-flops. When writing data, a high voltage is applied to one side of the bit line pair, a low voltage being applied to the other side. This is transferred to a memory node (a common source/drain node of MP 1 and NM 1 , and a common source/drain node of MP 2 and MN 2 ) to memorize binary information. When reading data, a voltage sustained at the bit line pair is detected in correspondence to the voltage of nodes and transferred to the exterior. Unlike the DRAM, the SRAM stores data without a refresh operation, i.e., statically by the flip-flop feedback, as long as the power is on. However, the SRAM is relatively expensive because a large number of elements are used to construct one cell, with a memory capacity being about ¼ of the DRAM with the same area.

FIG. 5 shows a layout of a CMOS RAM core cell for light-emitting display according to an embodiment of the present invention.

Referring to FIG. 5 , the CMOS RAM core cell for a light-emitting display according to an embodiment of the present invention is a data memory device for the data driver of a light-emitting device that includes six thin film transistors (MP 1 to MP 4 , and MN 1 and MN 2 ) each having a gate, a source, and a drain. In the figure, reference numerals 511 to 520 denote contact holes respectively. Also, reference numeral 532 denotes a metal line coupled to a power voltage VDD, reference numeral 531 denotes a metal line coupled to a ground voltage VSS, reference numerals 534 and 535 denote a pair of bit lines, and reference numeral 533 denotes a word line. Also, reference numerals 541 to 544 denote metal lines, and reference numerals 551 to 554 denote poly lines, respectively.

Among the six thin film transistors (MP 1 to MP 4 , and MN 1 and MN 2 ), the first switching transistor MP 3 has a gate coupled to a word line 533 , and a source/drain coupled to the first bit line 534 to select an input to the first bit line 534 according to the input signal of the word line 533 .

For example, the word line 533 has a role in a gate poly of the first switching transistor MP 3 , and a metal line across the contact hole 517 and the contact hole 515 has a role in the source/drain of the first switching transistor MP 3 . The layouts of the five transistors (MP 1 , MP 2 , MP 4 , MN 1 and MN 2 ) are formed in the same manner.

The second switching transistor MP 4 has a gate coupled to the word line 533 , and a source/drain coupled to a second bit line 535 , so as to select an input to the second bit line 535 according to the input signal to the word line 533 .

The first to fourth data memory transistors (MP 1 and MN 1 , and MP 2 and MN 2 ) that form a flip-flop as described above are coupled to a power voltage (VDD) or a ground voltage (VSS), so as to enable reading or writing of data under the control of the first and second switching transistors MP 3 and MP 4 .

As illustrated in the figure, the channels of the first and second switching transistors MP 3 and MP 4 , or the first to fourth data memory transistors (MP 1 and MN 1 , and MP 2 and MN 2 ) are formed in an oblique direction. When the direction of the bit lines is a first direction, and that of the word line is a second direction, the channels of the switching transistors and the data memory transistors are formed in an oblique direction with respect to the first and second directions, respectively. The oblique direction may be a clockwise direction or a counterclockwise direction with respect to the first or second direction. In addition, the first and second switching transistors MP 3 and MP 4 , or the first to fourth data memory transistors (MP 1 and MN 1 , and MP 2 and MN 2 ) may be arranged in sequence at the same angle on a defined layout space. As shown in FIG. 5 , the channels of the data memory transistors MN 1 and MP 1 are on one side of the word line 533 , and the channels of the data memory transistors MN 2 and MP 2 are the other side of the word line 533 , with respect to the direction of the word line 533 .

FIG. 6 is a circuit diagram showing the layout part taken in an oblique direction in the CMOS RAM core cell of FIG. 5 .

The SRAM core cell for a light-emitting display according to an embodiment of the present invention includes a plurality of thin film transistors each having a gate, a source, and a drain. The thin film transistors include four PMOS transistors 611 to 614 , and two NMOS transistors 621 and 622 , so as to enable writing or reading of data under the control of bit lines and word lines. As described previously, among the six transistors, MP 1 and MP 2 611 and 612 are pull-up transistors, MN 1 and MN 2 621 and 622 are pull-down transistors, and MP 3 and MP 4 613 and 614 are switching transistors for an access. Here, the MP 1 to MP 4 611 to 614 are PMOS transistors, and the MN 1 and MN 2 621 and 622 are NMOS transistors. In one embodiment, these transistors are arranged in sequence at an angle of 45° on a defined layout space.

FIG. 7 is a diagram specifically showing the layout taken in an oblique direction in the CMOS RAM core cell according to one embodiment of the present invention.

The CMOS SRAM core cell, according to the embodiment of the present invention as shown in FIG. 7 , has a defined layout of 22 μm×20 μm (22 μm in width and 20 μm in length) and includes six thin film transistors as stated above.

In the figure, reference numeral 532 denotes a metal line coupled to a power voltage VDD, reference numeral 531 denotes a metal line coupled to a ground voltage VSS, reference numerals 534 and 535 denote a pair of bit lines, and reference numeral 533 denotes a word line.

Referring to FIG. 7 , the CMOS RAM core cell includes six transistors, i.e., four PMOS transistors 611 to 614 and two NMOS transistors 621 and 622 , and its data write/read is under the control of the bit line pair and the word line. As stated above, the six transistors are arranged in sequence, for example, at an angle of 45° on a defined layout space.

The switching transistors or the data memory transistors arranged in an oblique direction may include a polysilicon layer deposited in an oblique direction on a substrate. Namely, an active region is formed on a polysilicon layer deposited in an oblique direction, and a gate, a source, and a drain are formed in the active region for the above-stated oblique arrangement of the channels.

Furthermore, a semiconductor device having a plurality of transistors formed in an oblique direction on a layout space of a predetermined area can also be implemented according to an embodiment of the present invention. The semiconductor includes a plurality of transistors each having a gate and a source/drain formed on a substrate or on an active region deposited on the substrate. The channels of the transistors on the active region are arranged in an oblique direction on the layout space of a predetermined area. Here, the channels of the transistors formed in an oblique direction on the active region are arranged in sequence and include a polysilicon layer deposited in an oblique direction with respect to the vertical direction on the substrate.

Consequently, the CMOS SRAM core cell for a light-emitting display according to the embodiments of the present invention can have enhanced integration efficiency by forming the channels or the polysilicon layer in an oblique direction.

While this invention has been described in connection with what is presently considered to be the most practical and exemplary embodiment, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

As described above, the present invention arranges transistors in sequence so as to form a polysilicon layer or channels forming the transistors in an oblique direction in a defined region in designing a SRAM for a data driver of a light-emitting display, thereby enhancing the layout efficiency of the core cell and implementing a light-emitting display device of a high integration level.