Clock and data recovery circuits

The invention relates to a clock and data recovery circuit, and in particular to a clock and data recovery circuit employed in communication systems.

In a typical communication system, a transmitter generates data signals according to its clock and transmits the data signals to a receiver through channels. To correctly interpret the data signals, the receiver reads the data signals according to a clock synchronized with the transmitter's clock. The receiver thus requires a clock recovery system to recover the data signal from the transmitter. At least two clock recovery techniques are currently used. First, the transmitter's clock may be transmitted to the receiver on a channel parallel with the channel carrying the data signals. The receiver can then estimate the phase of the data signals from the phase of transmitter's clock. This technique however, is disadvantageous in that it requires an additional channel. Alternately, the phase of the data signals may be recovered directly from information carried in the data signals themselves.

FIG. 1 shows a conventional clock and data recovery circuit. The clock and data recovery circuit 1 comprises a control unit 10 , a gated voltage controlled oscillator (GVCO) 11 , a D flip-flop 12 , and a phase locked loop (PLL) 13 . The PLL 13 comprises a phase/frequency detector 130 , a charge pump 131 , a filter 132 , and a GVCO 133 . The control unit 10 controls the GVCO 11 to receive a data signal D 1 . The phase/frequency detector 130 of the PLL 13 receives a reference clock Cf 1 , and the filter 132 controls the GVCOs 11 and 133 . The GVCOs 11 and 133 respectively output oscillated clocks CK 1 and CK 2 corresponding to the data signal D 1 . The D flip-flop 12 reads the data signal D 1 according to the clock CK 1 , thus estimating the phase of the data signal D 1 correctly.

In ideal conditions, the clock CK 1 synchronizes with the clock CK 2 . However, since the processes of the GVCOs 11 and 133 may not match, difference between the phases of the locks CK 1 and CK 2 is increased with time, such that the D flip-flop 12 may incorrectly trigger the data signal D 1 .

Clock and data recovery circuits are provided. An exemplary embodiment of a clock and data recovery circuit comprises a phase detection circuit, a first oscillator, a second oscillator, and a flip-flop. The clock and data recovery circuit receives an input signal and outputs an output signal in phase with the input signal. The phase detection circuit estimates a significant transition of the input signal and outputs a first detection signal. The first oscillator receives the first detection signal and outputs a first clock. The first oscillator operates in a first mode during a first period and operates sequentially in second and synchronization modes during a second period. The second oscillator receives the first detection signal and outputs a second clock. The second oscillator operates sequentially in the second and synchronization modes during the first period and in the first mode during the second period. The flip-flop receives the input signal and outputs the output signal according to the first and second clocks respectively during the first and second periods.

An exemplary embodiment of a clock and data recovery circuit comprises a phase detection circuit, a first oscillator, a second oscillator, and a flip-flop. The clock and data recovery circuit receives an input signal and outputs an output signal in phase with the input signal. The phase detection circuit estimates a significant transition of the input signal and outputs a detection signal. Each oscillator receives the detection signal and operates alternately in a clock and data recovery mode and a phase-locked mode. The first and second oscillators respectively output first and second clocks. The flip-flop receives the input terminal and outputs the output signal according to the first or second clock. During a first period, the first oscillator operates in the clock and data recovery mode and outputs the first clock to control the flip-flop to output the output signal, and the second oscillator operates in the phase-locked mode to adjust a frequency of the second clock. During the first period, before switching to the clock and data recovery mode, the second oscillator synchronizes the second clock with the first clock.

The invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings, given by way of illustration only and thus not intended to be limitative of the invention.

FIG. 1 shows a conventional clock and data recovery circuit.

FIG. 2 is a block diagram of an embodiment of a clock and data recovery circuit.

FIG. 3 depicts an embodiment of operating modes of the GVCOs in FIG. 2 .

FIG. 4 is a block diagram of an embodiment of a frequency control circuit.

FIG. 5 is a block diagram of an embodiment of a GVCO.

Clock and data recovery circuits are provided. In an exemplary embodiment of a clock and data recovery circuit, as shown in FIG. 2 , a clock and data recovery circuit 2 receives a data signal D 2 from a transmitter (not shown) as its input signal and generates an output signal equal to the input signal. The clock and data recovery circuit 2 comprises a phase detector 20 , gated voltage controlled oscillators (GVCO) 21 and 22 , a multiplexer 23 , a D flip-flop 24 , and a frequency control circuit 25 . The phase detector 20 and the D flip-flop 24 receive the data signal D 2 , and the frequency control circuit 25 receives a reference clock Cf 2 .

The phase detector 20 outputs a detection signal S 20 to the GVCOs 21 and 22 according to the significant transition (rising or falling edges) of the data signal D 2 . The GVCOs 21 and 22 output clocks CK 1 and CK 2 according to the detection signal S 20 respectively to two input terminals of the multiplexer 23 .

Both GVCOs 21 and 22 alternately operate in data/clock recovery mode (first mode) and phase-locked mode (second mode) and respectively output the clocks CK 1 and CK 2 . The GVCOs 21 and 22 operate the different modes at the same time. Before switching to the first mode from the second mode, each GVCO operates in synchronization mode (third mode).

After each GVCO, such as GVCO 21 , operates the first mode M 1 for a period, the frequency of the clock CK 1 may shift due to leakage current of capacitors therein. In the subsequent second mode, the shifted frequency of the clock CK 1 can be adjusted to within a predetermined error range. Before the GVCO 21 switches to the first mode from the second mode, the GVCO 21 operates in the third mode to synchronize the clock CK 1 with the clock CK 2 from the GVCO 22 , thereby avoiding erroneous detection of phase of the data signal D 2 due to the different between the phases of the clocks CK 1 and CK 2 . The GVCOs 21 and 22 operate alternately, such that the frequency error caused by unmatched elements can be compensated for.

Referring to FIGS. 2 and 3 , during a period T 1 , the GVCO 21 operates in a first mode M 1 , while the GVCO 22 operates in a second mode M 2 . Since the GVCO 21 operates in the first mode M 1 , the multiplexer 23 selects the clock CLK 1 to output to a control terminal of the D flip-flop 24 according to a select signal Sel 1 . The D flip-flop 24 triggers the data signal D 2 according to the clock CK 1 and outputs the recovered data signal as the output signal. Since the GVCO 22 operates in the second mode M 2 , the multiplexer 23 selects the clock CK 2 to output to the frequency control circuit 25 according to the select signal Sel 1 . The frequency control circuit 25 outputs a control voltage Vc 2 to the GVCO 22 according to the difference between the reference clock Cf 2 and the clock CK 2 , and the GVCO 22 thus adjusts the frequency of the clock CK 2 to be the same as that of the data signal D 2 or in the predetermined error range. The GVCO 22 then operates in a third mode M 3 . The GVCO 22 receives the clock CK 1 from the GVCO 21 and synchronizes the clock CK 2 with the clock CK 1 .

During a subsequent period T 2 , the GVCO 21 operates in the second mode M 2 , while the GVCO 22 operates in a first mode M 1 . Since the GVCO 21 operates in the second mode M 2 , the multiplexer 23 selects the clock CK 1 to output to the frequency control circuit 25 according to the select signal Sel 1 . The frequency control circuit 25 outputs a control voltage Vc 1 to the GVCO 21 according to the difference between the reference clock Cf 2 and the clock CK 1 , and the GVCO 21 thus adjusts the frequency of the clock CK 1 to be the same as that of the data signal D 2 or in the predetermined error range. The GVCO 21 then operates in the third mode M 3 . The GVCO 21 receives the clock CK 2 from the GVCO 22 and synchronizes the clock CK 1 therewith. Since the GVCO 22 operates in the first mode M 1 , the multiplexer 23 selects the clock CLK 2 to output to the control terminal of the D flip-flop 24 according to the select signal Sel 1 . The D flip-flop 24 triggers the phase of the data signal D 2 according to the clock CK 2 and outputs the recovered data signal as the output signal.

During a period T 3 following the period T 2 , the GVCOs 21 and 22 operate in the respective modes of the period T 1 . During a period T 4 following the period T 3 , the GVCOs 21 and 22 operate in the respective modes of the period T 2 . The GVCOs 21 and 22 operate the respective modes of the periods T 1 and T 2 repeatedly.

As previously described, each GVCO operates in first and second modes alternately. Before switching to the first mode from the second mode, the GVCO operates in a third mode. In other words, each GVCO operates in first, second, third modes sequentially.

Frequency control circuits are provided. An exemplary embodiment of a frequency control circuit 25 , as shown in FIG. 4 , comprises a phase/frequency detector 250 , a charge pump 251 , a de-multiplexer 252 , filters 253 and 254 , and a frequency divider 255 . The filters 253 and 254 can be low pass filters, and provide the voltages Vc 1 and Vc 2 respectively. The frequency divider 255 divides the frequency of the clock generated by the GVCO operating in the second mode M 2 . The divided clock is transmitted to one input terminal of the phase/frequency detector 250 . The other input terminal of the phase/frequency detector 250 receives the reference clock Cf 2 .

During the periods T 1 and T 3 , since the GVCO 22 operates in the second mode M 2 , the frequency divider 255 divides the frequency of the clock CK 2 output from the GVCO 22 . The divided clock CK 2 is transmitted to the phase/frequency detector 250 . The phase/frequency detector 250 outputs a control signal SP to the charge pump 251 according to the difference between the reference clock Cf 2 and the clock CK 2 . The de-multiplexer 252 turns on the path between the charge pump 251 and the filter 254 according a select signal Sel 2 to connect the charge pump 251 to the filter 254 . The charge pump 251 varies the control voltage Vc 2 according to the control signal SP. Thus, the GVCO 22 adjusts the frequency of the clock CK 2 generated by itself according to the control voltage Vc 2 . In other words, during the periods T 1 and T 3 , the operation of the phase/frequency detector 250 , the charge pump 251 , the de-multiplexer 252 , the filter 254 , and the frequency divider 255 is same as the operation of a conventional PLL circuit.

During the periods T 2 and T 4 , since the GVCO 21 operates in the second mode M 2 , the frequency divider 255 divides the frequency of the clock CK 1 output from the GVCO 21 . The divided clock CK 1 is transmitted to the phase/frequency detector 250 . The phase/frequency detector 250 outputs the control signal SP to the charge pump 251 according to the difference between the reference clock Cf 2 and the clock CK 1 . The de-multiplexer 252 turns on the path between the charge pump 251 and the filter 253 according to the select signal Sel 2 to couple the charge pump 251 to the filter 254 . The charge pump 251 varies the control voltage Vc 1 according to the control signal SP. Thus, the GVCO 21 adjusts the frequency of the clock CK 1 generated by itself according to the control voltage Vc 1 . In other words, during the periods T 2 and T 4 , operation of the phase/frequency detector 250 , the charge pump 251 , the de-multiplexer 252 , the filter 253 , and the frequency divider 255 is same as the operation of a conventional PLL circuit.

GVCOs are provided. In an exemplary embodiment of a GVCO, as shown in FIG. 5 , for example, the GVCO 21 comprises multiplexers 50 to 53 and two delay units. In the embodiment in FIG. 5 , the delay units are implemented by inverters 54 and 55 . The phase detector 20 further outputs a detection signal S 21 according to the significant transition of the data signal D 2 , and the detection signal S 21 is delayed from the detection signal S 20 , for example, the detection signal S 21 can be delayed from the detection signal S 20 for ½ unit time. Referring to FIG. 5 , two input terminals of the multiplexer 50 respectively receive clock CK 1 and the detection signal S 20 and the multiplexer 50 is controlled by a select signal Sel 50 . An input terminal of the inverter 54 is coupled to an output terminal of the multiplexer 50 . One input terminal of the multiplexer 51 is coupled to an output terminal of the inverter 54 , and the other input terminal thereof receives the clock CK 2 from GVCO 22 . The multiplexer 51 is controlled by a select signal Sel 51 . An input terminal of the inverter 55 is coupled to an output terminal of the multiplexer 51 , and an output terminal thereof outputs the clock CK 1 .

Two input terminals of the multiplexer 52 respectively receive a low voltage level (digital logic “0”) signal and the detection signal S 21 . The multiplexer 52 is controlled by a select signal Sel 52 and outputs the select signal Sel 50 . Two input terminals of the multiplexer 53 respectively receive a synchronizing signal Sync and a low voltage level (for example digital logic “0” in this embodiment). The multiplexer 53 is controlled by a select signal Sel 53 and outputs the select signal Sel 51 .

During the period T 1 , the GVCO 21 operates in a first mode M 1 . The select signal Sel 52 is at a high voltage level (for example digital logic “1” in this embodiment), so that the multiplexer 52 selects the detection signal S 21 as the select signal Sel 50 . The select signal Sel 53 is at the high voltage level (“1”), so that the multiplexer 53 selects the low voltage level (“0”) signal as the select signal Sel 51 . The multiplexer 50 selects the detection signal S 20 to the input terminal of the inverter 54 according to the select signal Sel 50 at the high voltage level (“1”) or selects the clock CK 1 to output to the input terminal of the inverter 54 according to the select signal Sel 50 at the low voltage level (“0”). The multiplexer 51 selects the signal from the output terminal of the inverter 54 to the input terminal of the inverter 55 according the select signal Sel 51 at the low voltage level (“0”). The inverter 55 outputs the clock CK 1 .

During the period T 2 , the GVCO 21 operates in the second mode M 2 first and then in the third mode. When the GVCO 21 operates in the second mode, the select signals Sel 52 , Sel 53 and the synchronizing signal Sync are at low voltage level (“0”). The multiplexer 52 selects the low voltage level (“0”) signal as the select signal Sel 50 , and the multiplexer 53 selects the synchronizing signal Sync as the select signal Sel 51 . The multiplexer 50 selects the clock CK 1 to output to the input terminal of the inverter 54 according to the select signal Sel 50 at the low voltage level (“0”). The multiplexer 51 selects the signal from the inverter 54 to output to the input terminal of the inverter 55 according the select signal Sel 51 at the low voltage level (“0”). The inverter 55 outputs the clock CK 1 . When the GVCO 21 operates in the second mode M 2 , the frequency control circuit 25 controls the operation frequency of the inverters 54 and 55 by the control voltage Vc 1 to adjust the frequency of the clock CK 1 .

When the GVCO 21 operates in the third mode during the period T 2 , the select signals Sel 52 and Sel 53 are at the low voltage level, and the synchronizing signal Sync is at high voltage level (“1”). The multiplexer 52 selects the low voltage level (“0”) signal as the select signal Sel 50 , and the multiplexer 53 selects the synchronizing signal Sync as the select signal Sel 51 . The multiplexer 50 selects the clock CK 1 to output to the input terminal of the inverter 54 according to the select signal Sel 50 at the low voltage level (“0”). The multiplexer 51 selects the clock CK 2 to output to the input terminal of the inverter 55 according to the select signal Sel 51 at the high voltage level (“1”). The inverter 55 outputs the clock CK 1 , which has been synchronized with the clock CK 2 .

Similarly, the GVCO 22 has the same circuit as FIG. 5 . In the GVCO 22 , the multiplexer 50 receives the clock CK 2 and the detection signal S 20 , the multiplexer 51 receives the signal from the inverter 54 and the clock CK 1 from GVCO 21 . The operation of the GVCO 22 during the periods T 1 to T 3 is as previously described.

Table 1 shows the state of the select signals Sel 50 to Sel 53 and the synchronizing signal Sync during the periods T 1 to T 3 . A logic level “1” represents a high voltage level, a logic level “0” represents a low voltage level, and “X” is referred to as a don't care state.

In same embodiments, when each GVCO operates in the modes M 1 and M 3 , the select signals Sel 52 and Sel 53 have the same voltage level. In practice, the states of the select signals Sel 50 to Sel 53 and the synchronizing signal Sync can be determined according to system requirements, as long as the result of the operation of each GVCO is the same as described.

In some embodiments, each of two GVCOs operates in clock/data recovery mode, phase-locked mode, and synchronization mode alternately. The oscillating frequency of each GVCO can be adjusted precisely, avoiding erroneous estimation of a phase of a data signal.

While the invention has been described in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.