Automatic gain control system with self-adaptive attack and decay time

1. Field of the Invention

The present invention relates, in general, to control systems, and, more particularly, to circuits, systems and methods for providing automatically gain control with self-adaptive attack and decay times.

2. Relevant Background

Automatic gain control (AGC) circuits are common components in a wide variety of analog and digital systems. For example, when reading signals from a disk surface the signal amplitude produced by the read head may vary significantly and benefits from automatic gain control to scale the signal magnitude before further signal processing. In communication systems, receivers, tuners and demodulators often require AGC processing of received signals to account for variations in the receive channel. AGC circuits are also used to prevent saturation in analog-to-digital converters. Other applications for AGC circuits are known. AGC circuit attempt to maintain relatively constant output signal amplitude over a range of signal input variations. This is typically achieved with an AGC which averages the output signal from the receiver and generates a feedback signal, referred to herein as an AGC control signal. The AGC control signal is coupled to control the gain of a variable gain amplifier.

AGC control systems have several characteristics which limit their use in a variety of applications. For example, AGC systems have a characteristic delay in its response to changes in the magnitude of the input signal. This means that the AGC control voltage remains constant for a short time after a change in the input signal level, after which the AGC control voltage follows the change to compensate for the level change. This delay is referred to as the “attack time” when describing the AGC system response to an input signal of increasing magnitude, and is referred to as a “decay time” when describing the AGC system response to an input signal of decreasing magnitude. The conventional AGC technology exhibits different or asymmetric attack and decay times. Normally, fast attack and slow decay are present.

FIG. 1 illustrates a conventional AGC circuit 100 consistent with practice in the prior art. In FIG. 1 , a differential input identified as V INP and V INN is applied to the input of variable gain amplifier (VGA) 101 . VGA 101 produces an amplified output (V OUT ) where the magnitude of the amplification is determined by the magnitude of a signal present on a control node of VGA 101 . As shown in FIG. 1 , conventional AGC circuits generate an AGC control voltage (V AGC ) by charging a capacitor 111 in a resistor-capacitor (RC) circuit. The AGC control voltage is coupled to a control node of a variable gain amplifier 101 . In operation, when the output voltage is larger than a pre-determined reference level, level detector 105 is triggered and closes switch 107 for a specified duration. While switch 107 is closed, a constant current provided by currents source 113 charges capacitor 111 . Usually capacitor 111 is implemented as an external capacitor because it requires a relatively large capacitance that is not practical to implement in an integrated fashion. The voltage on capacitor 111 is coupled to the control node of VGA 101 through buffer 109 .

The attack time is determined by the rate at which the voltage on capacitor 111 can be increased. The increase step voltage on the capacitor in every charge cycle is described by:

Δ ⁢ ⁢ V = ( I · t ) C = I ( fC )

where f is the signal frequency of V INP and V INN . This equation illustrates that the attack time has a direct dependence on the signal frequency. In order to obtain an acceptable attack time, a large capacitance, which must typically be implemented externally, is required. Further, the lower the input signal frequency, the large the capacitor that is required.

It can also be seen in FIG. 1 that the voltage on capacitor 111 is only driven in one direction or sense. A resistor is provided to gradually and continuously drain current away and discharge capacitor 111 . While this has the advantage of simplicity, the rate of current flow through the resistor changes continuously depending on the voltage across the capacitor. Further, while current is being applied through switch 107 , a portion of the current is being drained off by the resistor. As a result, V AGC changes in a non-linear fashion that makes precise control more difficult.

In view of the above it is apparent that there is a need for improved systems, methods and circuits for automatic gain control.

Briefly stated, the present invention involves a method of gain control by amplifying an input signal with a variable gain amplifier to generate an output signal where the gain of the variable gain amplifier is selected based upon a control signal presented at a control input of the variable gain amplifier. When the output signal is larger than the upper boundary, incrementally changing the magnitude of the control signal so as to reduce the gain of the variable gain amplifier in a step-wise linear fashion. When the output signal is smaller than the lower boundary, incrementally changing the magnitude of the control signal so as to increase the gain of the variable gain amplifier in a step-wise linear fashion. The present invention also includes circuits for implementing the method and systems incorporating circuits for implementing the method.

FIG. 1 shows an a prior art automatic gain control circuit;

FIG. 2 shows an automatic gain control circuit in accordance with the present invention;

FIG. 3 shows waveforms illustrating the operation of a timing generator component of an automatic gain control circuit in accordance with the present invention;

FIG. 4 shows waveforms illustrating attack time response of an automatic gain control circuit in accordance with the present invention;

FIG. 5 shows waveforms illustrating decay time response of an automatic gain control circuit in accordance with the present invention;

FIG. 6 shows waveforms illustrating attack time response of an automatic gain control circuit in accordance with the present invention at an alternate frequency as compared to the example of FIG. 4 ; and

FIG. 7 shows waveforms illustrating decay time response of an automatic gain control circuit in accordance with the present invention at an alternate frequency as compared to the example of FIG. 5 .

The present invention is illustrated and described in terms of a particular circuit implementation of an automatic gain control. While the present invention will typically be implemented as a part of an integrated circuit (IC), it is contemplated that the present invention may be implemented as discrete component, as a stand-alone IC, or as part of a system on chip (SOC) or multi-chip system.

FIG. 2 illustrates an exemplary implementation in which the AGC control voltage (V AGC ) is generated by a charge pump 201 that is driven by a timing controller 203 . Clock generator 221 generates a clock pulse T 1 that is synchronized with the frequency of the V OUT signal. Charge pump 201 charges capacitor 211 by applying pulses T 2 and discharges capacitor 211 by applying pulses T 3 . In general, the operating time of the charge pump 201 is relatively short and so the capacitor 211 can be small as compared to capacitor 111 shown in FIG. 1 . This allows capacitor 211 to be implemented as an integrated device in some instances. The instantaneous gain of variable gain amplifier 101 is determined by the V AGC signal as applied through buffer 109 .

Charge pump behavior is determined by the reference voltage values V REF1 , V REF2 and V REF3 . Rectifier 217 rectifies the V OUT signal to produce a signal named V A in the illustrations. In the particular examples, V A is coupled to the inverting input of comparator 207 and 209 , and coupled to the non-inverting input of comparator 205 . V REF1 is coupled to the inverting input of comparator 205 , V REF2 is coupled to the non-inverting input of comparator 207 and V REF3 is coupled to the non-inverting input of comparator 209 . V A is compared to V REF1 by comparator 205 , V REF2 by comparator 207 and V REF3 by comparator 209 .

While V A is between V REF1 and V REF3 , the output voltage V OUT is close to the desired value and so no gain adjustment is required. In this state, the charge pump 201 does not operate. Timing controller 203 produces signals T 2 and T 3 so as to keep switches 219 and 221 in an open state. Accordingly, capacitor 211 is neither charged nor discharged and V AGC remains substantially constant. Consequently, the AGC loop gain remains substantially constant.

When V A goes to a level outside of the “dead zone” defined by V REF1 and V REF3 , the output voltage V OUT has deviated from the desired value and so gain adjustment is required. In the particular example, an increase in V A above V REF1 causes the output of comparator 205 to transition from a logic LOW to a logic HIGH, and a decrease in V A below V REF3 will cause the output of comparator 209 to transition from a logic LOW a logic HIGH. Timing controller 203 is then enabled to generate pulses T 2 or T 3 that close switches 219 or 221 .

During charging, magnitude of the current supplied to capacitor 211 with each pulse of T 2 is determined by variable current source 213 . During discharging, magnitude of the current removed from capacitor 211 with each pulse of T 3 is determined by variable current source 215 . In the particular example, variable current sources 213 and 215 are under control of the output of comparator 207 . Preferably, as the magnitude of the difference between V A and V REF2 becomes larger, current sources 213 / 215 are controlled so as to increase the rate at which capacitor 211 is charged/discharged. In this manner the charge pump intervention is proportional to the difference between V A and V REF2 . When V A is close to V REF2 , charge pump current is small and the variation (increment or decrement) of V AGC is small as well. When V A differs significantly from V REF2 , the charge pump current is high and the increments of increase and decrease in V AGC are large as well. In a particular example, when charge pump 201 is operating it charges with a pulse of T 2 or discharges with a pulse of T 3 twice in each cycle of T 1 . The change in V AGC with each pulse of T 2 /T 3 is described by:

where t is the T 2 /T 3 pulse width, I is the current magnitude of current source 213 / 215 , and C is the value of capacitor 211 . Unlike the prior circuit shown in FIG. 1 , the operating time or pulse width of the T 2 /T 3 pulses is fixed by the clock generator 221 and timing controller 203 . Hence, each pulse will result in a substantially equal change in V AGC , irrespective of the frequency of the input signal. However, T 2 /T 3 may pulse at a wide range of rates and pulse widths to meet the needs of a particular application. The pulse width should be long enough to provide sufficiently rapid charge/discharge of capacitor 211 but at the same time short enough to provide adequately small steps each time T 2 /T 3 are pulsed. Smaller steps provide greater granularity in the control of V AGC . In a particular example, the charge time T 2 is set to near the discharge time T 3 . As a result, the attack time is substantially equal to the release time.

In the example of FIG. 2 , the attack time and decay time (also referred to as a release time) that are substantially equal is provided. The measured attack/decay time achieved by a particular implementation is dependent on the input magnitude because the system undergoes a continuous control action and the charge/discharge time of charge pump 211 is regulated to the same value even though the input signal frequency may vary.

It will be recalled that in the prior art FIG. 1 , when the input frequency was low, the quantity of charging current added to capacitor 111 each cycle was much larger than is the quantity added during each cycle of a higher frequency input signal. As a result, in order to achieve sufficiently small voltage increments in V AGC , a large external capacitor was required for low frequency operation. In accordance with the present invention, since the pulse width of each T 2 /T 3 pulse can be made very short and is independent of the input signal frequency, capacitor 211 (shown in FIG. 2 ) can be made quite small as compared to capacitor 111 in FIG. 1 .

For a case in which there are two T 2 /T 3 pulses per clock, and therefore two incremental steps in the change of V AGC each clock pulse, for a given change in V AGC (i.e., a V AGC change from V AGC1 to V AGC2 ) the attack time (or decay time) can be determined from:

t attack = t decay =  V AGC ⁢ ⁢ 2 - ⁢ ⁢ V AGC ⁢ ⁢ 1  2 ⁢ ⁢ Δ ⁢ ⁢ V AGC ⁢ ( Ts )

where Ts is the signal cycle (i.e., the period for T 2 /T 3 ). From the above equation it is apparent that the decay time can be made substantially equal to the attack time for a given input signal because the current is determined by the input signal amplitude, not the input signal frequency. Moreover, the charge pump solution of the present invention allows control over both the rate of increase in V AGC as well as the rate of decrease in V AGC .

The above equation also shows that the attack or decay time is a multiple “n” of the signal cycle where “n” is an integer indicating the number of T 2 /T 3 pulses. In other words, the V AGC naturally increases or decrease in a step-wise linear fashion rather than prior solutions in which it was difficult or impossible to cause each increment to change V AGC by a uniform amount.

FIG. 3 shows waveforms illustrating the operation of a timing controller 203 . The three waveforms shown in FIG. 3 are aligned in time which is represented on the horizontal axis. The vertical axes represent voltage with exemplary voltage levels indicated on the axes for relative comparisons. FIG. 3 illustrates a situation in which the magnitude of V IN increases from a peak-to-peak value of about 2.5 mV to a peak to peak value of about 30 mV as shown at time point 301 . Charging pump 201 functions to quickly and accurately change the gain of VGA 101 so that V OUT experiences little amplitude variance. The waveform labeled V A shows the rectified V OUT , the waveform labeled T 1 is illustrated as a square-wave superimposed over the V A waveform. It can be seen that T 2 /T 3 pulses are synchronized with the V A waveform.

After time point 301 , V A increases or decrease in magnitude such that it is outside of the window defined by V REF1 and V REF3 . Consequently, current source 213 or 215 is activated, and timing controller 203 begins to generate T 2 or T 3 pulses. The determination of whether a T 2 or T 3 pulse is generated is determined by whether V A is larger than desired, indicating a need to reduce gain, or V A is smaller than desired, which indicates a need to increase gain.

At about time point 302 timing controller 203 beings to generate T 2 or T 3 pulses at times 302 - 313 as shown in the lower waveform of FIG. 3 . In FIG. 3 the T 2 /T 3 pulses are generated on the falling edge of the T 1 clock, however, any convenient arrangement for generating one ore more T 2 /T 3 pulses each clock cycle may be used. FIG. 3 illustrates that V A increases in magnitude immediately after V IN increases in magnitude to the point of clipping at the power supply limits. With in a few cycles, however, V A decreases in magnitude as the gain of VGA 101 is incrementally reduced over time periods 302 - 313 . After time point 313 V A has been reduced to the point that it is within the upper and lower limits set by V REF1 and V REF3 , at which time timing controller ceases generating T 2 or T 3 pulses.

FIG. 4 shows simulated waveforms illustrating attack time response of an automatic gain control circuit in accordance with the present invention with a V IN frequency of 1 kilohertz in an “attack” example where V IN increases from a peak value of about 2.5 mV to a peak value of about 30 mV as in the example of FIG. 3 . In FIG. 4 , V OUT is illustrated rather than V A . In FIG. 4 , V AGC generated is illustrated demonstrating how it increases in a step-wise linear fashion with two increments per clock cycle in the specific implementation. Each increment is substantially equal in magnitude to each other increment, and there is no discernable non-linear decay or discharge that affects the V AGC level. Once the timing controller 203 is deactivated V AGC remains at a substantially steady level.

FIG. 5 shows simulated waveforms illustrating decay time response of an automatic gain control circuit in accordance with the present invention with a V IN frequency of 1 kilohertz in an “release” or “decay” example where V IN decreases from a peak value of about 30 mV to a peak value of about 2.5 mV. In FIG. 5 , V AGC generated is illustrated demonstrating how it decreases in a step-wise linear fashion with two increments per clock cycle in the specific implementation. Each increment is substantially equal in magnitude to each other increment, and there is no discernable non-linear decay or discharge that affects the V AGC level. Once the timing controller 203 is deactivated V AGC remains at a substantially steady level. Significantly, the process of reducing the V AGC value shown in FIG. 5 is substantially analogous to the process of increasing V AGC illustrated in FIG. 4 .

FIG. 6 and FIG. 7 shows simulated waveforms illustrating attack time response ( FIG. 6 ) and decay time response ( FIG. 7 ) of the automatic gain control circuit in accordance with the present invention at an alternate frequency (10 kilohertz) as compared to the examples of FIG. 4 and FIG. 5 . It is apparent that the response times, in terms of signal cycles, are substantially identical. Significantly, the incremental change in V AGC for each signal period is identical to that shown in the 1 kilohertz examples of FIG. 4 and FIG. 5 . In the simulated examples, the total attack response time and total delay response time is scaled linearly with frequency, hence, at 10 kilohertz the response times are 10× shorter than the corresponding times for a 1 kilohertz signal. This is preferable in many cases to the prior art situation in which V AGC , and hence gain response, increases faster at lower signal frequency than it does at higher input frequencies. However, because the change in V AGC for each T 2 /T 3 pulse is uniform over frequency, it is a simple matter to decrease the frequency of T 2 /T 3 pulses so that the attack/decay response times are substantially similar in an absolute sense (e.g., by adding a divider to the T 2 /T 3 pulse generation circuitry so that only one T 2 /T 3 pulse is generated for every ten signal cycles).

Although the invention has been described and illustrated with a certain degree of particularity, it is understood that the present disclosure has been made only by way of example and that numerous changes in the combination and arrangement of parts can be resorted to by those skilled in the art without departing from the spirit and scope of the invention, as hereinafter claimed.