Clock selection circuit and digital processing system for reducing glitches

This application claims the priority of Korean Patent Application No. 2004-24889, filed on Apr. 12, 2004, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.

The present invention relates to a digital processing system which may include two or more clock signal sources, and more particularly, to a clock selection circuit that selects one clock signal from two or more clock signals and outputs the selected clock signal.

For certain types of semiconductor circuits, speed and capacity has increased. Some examples of these types of semiconductor circuits may include, for example, application specific integrated circuits (ASIC), central processing units (CPU), and digital signal processors (DSP). Some of the progress in the speed and capacity of semiconductor circuits may be attributed to system-on-chip (SOC) integration, which may provide a way to integrate a plurality of separate chips into a single chip.

SOC may be integrated into a digital processing system having a plurality of clock signal sources. SOC may also enable a plurality of clock signals generated by a plurality of clock signal sources to be used selectively. A glitch may occur when changing clock signals from a first clock signal to a second clock signal. A clock selection circuit that receives more than one clock signal (i.e., a first and second clock signal), may select one of the two clock signals, and output the selected clock signal. Conventional clock selection circuits that perform clock selection operations may have a high level of power consumption, which may result from the amount of logic gates contained in the circuit. If a clock selection circuit performs a clock selection operation then certain measures may be taken to reduce the likelihood that a glitch occurs.

Exemplary embodiments of the present invention may provide a high-density and/or low power clock selection circuit.

Exemplary embodiments of the present invention may provide a clock selection circuit that reduces the likelihood of glitches when performing a clock selection operation and/or a clock selection circuit that uses fewer logic gates than conventional clock selection circuits, which may reduce the level of power consumption used by the clock selection circuit.

Exemplary embodiments of the present invention may further provide a digital processing system that includes a clock selection circuit.

According to an exemplary embodiment of the present invention a clock selection circuit may receive first and second clock signals, and select and output one of the clock signals. The clock selection circuit may include a first control circuit, a second control circuit, a first disable signal generating circuit, a second disable signal generating circuit, and a logic circuit. The first control circuit may generate a first clock control signal activated for a first specified period, and may output a delayed first clock signal as a first gated clock signal in response to a control signal and/or a first disable signal. The second control circuit may generate a second clock control signal activated for a second specified period, and output a delayed second clock signal as a second gated clock signal in response to an inverted control signal and/or a second disable signal. The first disable signal generating circuit may generate the first disable signal by delaying the second clock control signal for a specified cycle of the delayed first clock signal. The second disable signal generating circuit may generate the second disable signal by delaying the first clock control signal for a specified cycle of the delayed second clock signal. The logic circuit may generate an output clock signal by performing a logic operation on the first and second gated clock signals.

Exemplary embodiments of the present invention may provide the first control circuit generating the first clock control signal activated for a first specified period, and may output a delayed first clock signal as a first gated clock signal during only the first specified period in response to a control signal and/or a first disable signal. The second control circuit may generate a second clock control signal activated for a second specified period, and may output a delayed second clock signal as a second gated clock signal during only the second specified period in response to an inverted control signal and/or a second disable signal.

Exemplary embodiments of the present invention may also provide the first control circuit including a first clock control circuit, a first delay circuit, and a first gating circuit. The first clock control circuit may generate the first clock control signal activated during the first specified period in response to the control signal and/or the first disable signal. The first delay circuit may output the delayed first clock signal by delaying the first clock signal. If the first gating circuit outputs the delayed first clock signal as the first gated clock signal then this output operation may occur during the first specified period of the first clock control signal.

Exemplary embodiments of the present invention may also provide the second control circuit including a second clock control circuit, a second delay circuit, and a second gating circuit. The second clock control circuit may generate the second clock control signal activated during the second specified period in response to the inverted control signal and/or the second disable signal. The second delay circuit may output the delayed second clock signal by delaying the second clock signal. If the second gating circuit outputs the delayed second clock signal as the second gated clock signal then this output operation may occur during the second specified period of the second clock control signal.

Exemplary embodiments of the present invention may also provide the first disable signal generating circuit including a plurality of flip-flops connected in series, the flip-flops each having a clock port into which the delayed first clock signal may be input. Among the plurality of flip-flops in the first disable generating circuit, a second clock control signal may be input to the first flip-flop, and/or the first disable signal may be output from the last flip-flop.

Exemplary embodiments of the present invention may also provide the second disable signal generating circuit including a plurality of flip-flops connected in series, the flip-flops each having a clock port into which the delayed second clock signal may be input. Among the plurality of flip-flops in the second disable generating circuit, a first clock control signal may be input to the first flip-flop, and a second disable signal may be output from the last flip-flop.

Exemplary embodiments of the present invention may also provide the logic circuit including a NAND gate that receives the first and second gated clock signals and outputs the output clock signal.

According to another exemplary embodiment of the present invention a digital processing system may include a digital processing circuit, a first clock signal source, a second clock signal source and a clock selection circuit. The digital processing circuit may operate at a plurality of clock frequencies. The first clock signal source may generate a first clock signal, and the second clock signal source generate a second clock signal. The clock selection circuit may receive and select one of the first and second clock signals, and output the selected clock signal to the digital processing circuit.

Exemplary embodiments of the present invention may provide the first control circuit of the digital processing system generating the first clock control signal activated for a first specified period, and may output a delayed first clock signal as a first gated clock signal during only the first specified period in response to a control signal and/or a first disable signal. The second control circuit may generate a second clock control signal activated for a second specified period, and may output a delayed second clock signal as a second gated clock signal during only the second specified period in response to an inverted control signal and/or a second disable signal.

Exemplary embodiments of the present invention may provide the clock selection circuit of the digital processing system including a first control circuit, a second control circuit, a first disable signal generating circuit, a second disable signal generating circuit, and a logic circuit. The first control circuit may generate a first clock control signal activated for a first specified period, and may output a delayed first clock signal as a first gated clock signal in response to a control signal and/or a first disable signal. The second control circuit may generate a second clock control signal activated for a second specified period, and output a delayed second clock signal as a second gated clock signal in response to an inverted control signal and/or a second disable signal. The first disable signal generating circuit may generate the first disable signal by delaying the second clock control signal for a specified cycle of the delayed first clock signal. The second disable signal generating circuit may generate the second disable signal by delaying the first clock control signal for a specified cycle of the delayed second clock signal. The logic circuit may generate an output clock signal by performing a logic operation on the first and second gated clock signals.

Exemplary embodiments of the present invention may provide the first control circuit of the digital processing system including a first clock control circuit, a first delay circuit, and a first gating circuit. The first clock control circuit may generate the first clock control signal activated during the first specified period in response to the control signal and/or the first disable signal. The first delay circuit may output the delayed first clock signal by delaying the first clock signal. The first gating circuit may output the delayed first clock signal as the first gated clock signal during the first specified period of the first clock control signal.

Exemplary embodiments of the present invention may provide the second control circuit of the digital processing system including a second clock control circuit, a second delay circuit, and a second gating circuit. The second clock control circuit may generate the second clock control signal activated during the second specified period in response to the inverted control signal and/or the second disable signal. The second delay circuit may output the delayed second clock signal by delaying the second clock signal. The second gating circuit may output the delayed second clock signal as the second gated clock signal during the second specified period of the second clock control signal.

Exemplary embodiments of the present invention may also provide the first disable signal generating circuit of the digital processing system including a plurality of flip-flops connected in series, the flip-flops each having a clock port into which the delayed first clock signal may be input. Among the plurality of flip-flops in the first disable generating circuit, a second clock control signal may be input to the first flip-flop, and/or the first disable signal may be output from the last flip-flop.

Exemplary embodiments of the present invention may also provide the second disable signal generating circuit of the digital processing system including a plurality of flip-flops connected in series, the flip-flops each having a clock port into which the delayed second clock signal may be input. Among the plurality of flip-flops in the second disable generating circuit, a first clock control signal may be input to the first flip-flop, and a second disable signal may be output from the last flip-flop.

Exemplary embodiments of the present invention may also provide the logic circuit of the digital processing system including a NAND gate that receives the first and second gated clock signals and outputs the output clock signal.

The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:

FIG. 1 illustrates a block diagram of a digital processing system according to an exemplary embodiment of the present invention;

FIG. 2 illustrates a circuit diagram of a clock selection circuit of FIG. 1 according to an exemplary embodiment of the present invention;

FIG. 3 illustrates a timing diagram of the clock selection circuit illustrated in FIG. 2 ;

FIG. 4 is a graph illustrating an example simulation comparing power consumption of the clock selection circuit illustrated in FIG. 2 and power consumption of a conventional clock selection circuit; and

FIG. 5 is a flow diagram illustrating an example operation of the clock selection circuit according to an exemplary embodiment of the present invention.

Hereinafter, the present invention will be described in detail by explaining exemplary embodiments of the invention with reference to the attached drawings. Like reference numerals in the drawings may represent like elements.

FIG. 1 is a block diagram of a digital processing system according to an exemplary embodiment of the present invention. Referring to FIG. 1 , the digital processing system may include a first clock signal source 11 , a second clock signal source 13 , a clock selection circuit 15 and a digital processing circuit 17 .

The first clock signal source 11 may generate a first clock signal CLK 1 , and the second clock signal source 13 may generate a second clock signal CLK 2 . The first and second clock signal sources may be internal or external clock signal sources.

The clock selection circuit 15 , according to an exemplary embodiment of the present invention, may select one of the first and second clock signals CLK 1 and CLK 2 as an output clock signal CLKOUT. Selecting an output clock signal CLKOUT may be performed in response to a control signal BYPASS received by the clock selection circuit from an external source. If the clock selection circuit performs a selection operation by selecting one of the clock signals CLK 1 and CLK 2 then the output clock signal CLKOUT may be output to the digital processing circuit 17 .

The digital processing circuit 17 may operate with more than one clock frequency. For example, the digital processing circuit 17 may operate in response to the first clock signal CLK 1 and/or the second clock signal CLK 2 . The digital processing circuit 17 may include an application specific integrated circuit (ASIC), a central processing unit (CPU), and/or a digital signal processor (DSP).

The first clock signal CLK 1 and the second clock signal CLK 2 may be synchronous or asynchronous clock signals. Also, the first clock signal CLK 1 and the second clock signal CLK 2 may operate at the same or different clock frequencies.

The control signal BYPASS may be an active high signal that controls the first clock signal CLK 1 and the second clock signal CLK 2 , which may be selectively output to the output clock signal CLKOUT port of the clock selection circuit 15 . A reset signal NRESET may be an active low signal and may provided as input to the clock selection circuit 15 .

FIG. 2 is a circuit diagram of the clock selection circuit 15 of FIG. 1 , according to an exemplary embodiment of the present invention. Referring to FIG. 2 , the clock selection circuit 15 may include, for example, a first control circuit 21 , a second control circuit 23 , a first disable signal generating circuit 25 , a second disable signal generating circuit 27 , and a logic circuit 29 .

The first control circuit 21 , according to an exemplary embodiment of the present invention, may generate a first clock control signal CK 1 Q in response to the control signal BYPASS, a first disable signal CK 1 HD, a first clock signal and/or a second clock control signal from the second control circuit 23 . The first clock control signal CK 1 Q may be activated for a specified period. The first control circuit 21 may output a delayed clock signal CLK 1 D based on a delayed first clock signal CLK 1 . The delayed clock signal CLK 1 D and the first clock control signal CK 1 Q may be used to generate a first gated clock signal CK 1 OUT during the specified period.

The second control circuit 23 , according to an exemplary embodiment of the present invention, may generate a second clock control signal CK 2 Q in response to the control signal BYPASSB (inverted BYPASS), a second disable signal CK 2 HD, a second clock signal and/or a first clock control signal from the first control circuit 21 . The second clock control signal CK 2 Q may be activated for a specified period. The second control circuit 23 may output a delay clock signal CLK 2 D based on a delayed second clock signal CLK 2 . The delayed clock signal CLK 2 D may be used to generate a second gated clock signal CK 2 OUT during the specified period.

The first disable signal generating circuit 25 , according to an exemplary embodiment of the present invention, may generate the first disable signal CK 1 HD. Generating the first disable signal CK 1 HD may include delaying the second clock control signal CK 2 Q, which may be input to the first disable signal generating circuit. The second clock control signal CK 2 Q may be delayed by a cycle of the delay clock signal CLK 1 D. The second disable signal generating circuit 27 may generate the second disable signal CK 2 HD. Generating the second disable signal CK 2 D may include delaying the first clock control signal CK 1 Q, which may be input to the second disable signal generating circuit. The first clock control signal CK 1 Q may be delayed by a cycle of the delay clock signal CLK 2 D.

The first control circuit 21 , according to an exemplary embodiment of the present invention, may include for example, a first clock control circuit 211 , a first delay circuit 213 , and a first gating circuit 215 .

The first clock control circuit 211 , according to an exemplary embodiment of the present invention, may receive the control signal BYPASS, the first disable signal CK 1 HD, the first clock signal CLK 1 and/or the second clock control signal CK 2 Q from the second clock control circuit 231 . The first clock control circuit 211 may generate the first clock control signal CK 1 Q, which may be activated during a specified period. The first clock control circuit 211 may include a NOR gate 211 A for receiving input signals, and may also include a flip-flop 211 B for receiving an output signal of the NOR gate 211 A. The flip-flop 211 B may receive the output of NOR gate 211 A, the clock signal CLK 1 and/or a reset signal NRESET at a reset port RN. The flip-flop 211 B may output the first clock control signal CK 1 Q.

The first delay circuit 213 may delay the first clock signal CLK 1 and/or output the delay signal CLK 1 D. The first delay circuit 213 may be composed of a series chain of inverters, which may be an even number of inverters, for example 213 A through 213 D of FIG. 2 .

The first gating circuit 215 may be composed of a NAND gate that receives the first clock control signal CK 1 Q and the delay signal CLK 1 D and outputs the first gated clock signal CK 1 OUT. The first gated clock signal CK 1 OUT may be activated when the first clock control signal CK 1 Q is activated.

The second control circuit 23 , according to an exemplary embodiment of the present invention, may include for example, a second clock control circuit 231 , a second delay circuit 233 , and a second gating circuit 235 .

The second clock control circuit 231 , according to an exemplary embodiment of the present invention, may receive the control signal BYPASSB (inverted BYBASS), the second disable signal CK 2 HD, the second clock signal CLK 2 and/or the first clock control signal from the first clock control circuit 211 . The second clock control circuit 231 may generate the second clock control signal CK 2 Q, which may be activated during a specified period. The second clock control circuit 231 may include a NOR gate 211 A for receiving input signals, and may also include a flip-flop 231 B for receiving an output signal of the NOR gate 231 A. The flip-flop 231 B may receive the output of NOR gate 231 A, the clock signal CLK 1 and/or a reset signal NRESET at a reset port RN. The flip-flop 231 B may output the second clock control signal CK 2 Q.

The second delay circuit 233 may delay the second clock signal CLK 2 and/or output the delay signal CLK 2 D. The second delay circuit 233 may be composed of a series chain of inverters, which may be an even number of inverters, for example inverters 233 A through 233 D.

The second gating circuit 235 may be composed of a NAND gate that receives the second clock control signal CK 2 Q and the delay signal CLK 2 D and outputs the second gated clock signal CK 2 OUT. The second gated clock signal CK 2 OUT may be activated when the second clock control signal CK 2 Q is activated.

The first disable circuit 25 , according to an exemplary embodiment of the present invention, may include a plurality of flip-flops connected in series, for example 251 , 253 , and 255 . The delay signal CLK 1 D may be input to one or more of the clock ports CK of the plurality of flip-flops. The second clock control signal CK 2 Q may be input to an input port D of a first flip-flop 251 among the plurality of flip-flops. The output ports Q for the first and second flip-flops (i.e., 251 and 253 ) may be coupled to the input ports D of the second and third flip-flops (i.e., 253 and 255 ) respectively. The first disable signal CK 1 HD may be output from an output port Q of the last flip-flop 255 among the plurality of flip-flops 251 , 253 , and 255 of the first disable circuit 25 . Also, a reset signal NRESET may be input to reset ports RN for all of the flip-flops of the first disable circuit 25 .

The second disable circuit 27 , according to an exemplary embodiment of the present invention, may include a plurality of flip-flops connected in series, for example 271 , 273 , and 275 . The delay signal CLK 2 D may be input to one or more of the clock ports CK of the plurality of flip-flops. The first clock control signal CK 1 Q may be input to an input port D of a first flip-flop 271 among the plurality of flip-flops. The output ports Q for the first and second flip-flops may be coupled to the input ports D of the second and third flip-flops respectively. The second disable signal CK 2 HD may be output from an output port Q of the last flip-flop 275 among the plurality of flip-flops 271 , 273 , and 275 of the second disable circuit 27 . Also, a reset signal NRESET may be input to reset ports RN for all of the flip-flops of the second disable circuit 27 .

The first and second disable circuits 25 and 27 , according to an exemplary embodiment of FIG. 2 , have each been illustrated as having three flip-flops. Other examples of disable signal generating circuits, which may be used in the clock selection circuit 15 may include, for example, two, four, or more than four flip-flops.

The logic circuit 29 may be a NAND gate that receives the first gated clock signal CK 1 OUT and the second gated clock signal CK 2 OUT and outputs the output clock signal CLKOUT.

FIG. 3 , according to an exemplary embodiment of the present invention, illustrates a timing diagram of the signals of clock selection circuit 15 . Referring to FIG. 3 , the first clock control signal CK 1 Q, the second clock control signal CK 2 Q, the first disable signal CK 1 HD, and the second disable signal CK 2 HD may all be initially at a logic low state in response to logic high state of reset signal NRESET.

The first clock control signal CK 1 Q, according to an example operation of the first clock control circuit 211 , may be activated to a logic high state once the control signal BYPASS has been activated by the first clock control circuit 21 . CK 1 Q may be activated to a logic high state after a time duration of one cycle of the first clock signal CLK 1 , after the control signal BYPASS has been activated. The first clock control signal CK 1 Q may be activated to a logic high state, for example, for a first specified period, which may correspond to a period when the control signal BYPASS is at a logic high state.

The first gating circuit 215 may invert the delay signal CLK 1 D for a specified time period, for example, only during a time period when the first clock control signal CK 1 Q is at a logic high state. The inverted signal may be output as the first gated clock signal CK 1 OUT.

The second clock control signal CK 2 Q, according to an example operation of the second clock control circuit 231 , may be activated to a logic high state during a specified period, for example, a second specified period, which may correspond to a time period when the control signal BYPASSB (not included in FIG. 3 ) is at a logic high state.

The second gating circuit 235 may invert the delay signal CLK 2 D for a specified time period, for example, only during a time period when the second clock control signal CK 2 Q is at a logic high state. The inverted signal may be output as the second gated clock signal CK 2 OUT.

Logic circuit 29 , according to an exemplary embodiment of FIG. 2 , may perform a NAND operation on the first and second gated clock signals CK 1 OUT and CK 2 OUT, and output a clock signal CLKOUT. The first clock signal CLK 1 may be selected and output as the output clock signal CLKOUT only during a specified time period when the first clock control signal CK 1 Q is at a logic high state. Also the second clock signal CLK 2 may be selected and output as the output clock signal CLKOUT only during a specified time period when the second clock control signal CK 2 Q is at a logic high state. Limiting the time periods when a specified clock signal may be output to a digital processing circuit may reduce the likelihood that glitches occur.

FIG. 4 is a graph representing a comparison between an exemplary embodiment of the present invention and a conventional clock selection circuit. The simulation result illustrates a comparison between the power consumption of the clock selection circuit 15 of the present invention and the power consumption of a conventional clock selection circuit. The clock selection circuit 15 may use less power than the conventional clock selection circuit. Also, the number of logic gates used in the clock selection circuit 15 is about 20% less than the number of logic gates used in the conventional clock selection circuit.

FIG. 5 , according to an exemplary embodiment of the present invention, illustrates an operation of selecting and generating a clock signal, which may be output to a digital processing circuit. Referring to FIG. 5 , a first and second clock control signal are generated S 110 and S 130 , and a first and second gated clock signal are generated S 120 and S 140 . A logic operation may be performed based on the first and second gated clock signals S 150 and as a result an output clock signal may be generated S 160 .

Exemplary embodiments of the present invention have been shown and described with reference to two clock signal sources 11 and 13 , and correspondingly two sets of circuit components (i.e., 211 and 231 , 213 and 233 , 21 and 23 , 25 and 27 ) as illustrated in the clock selection circuit 15 . It will be understood by those of ordinary skill in the art that exemplary embodiments of the present invention may include more than two clock signal sources and/or more than two corresponding sets of circuit components for a clock selection circuit.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims.