Electro-luminescence display panel and driving method thereof

This application claims the benefit of Korean Patent Application No. P2004-22122 filed in Korea on Mar. 31, 2004, which is hereby incorporated by reference.

1. Field of the Invention

This invention relates to an electro-luminescence display (EL) display panel, and more particularly to an EL display panel and a driving method thereof that are adaptive for preventing a life shortening of the EL caused by a direct current (DC).

2. Description of the Related Art

Recently, there have been highlighted various flat panel display devices reduced in weight and bulk that is capable of eliminating disadvantages of a cathode ray tube (CRT). Such flat panel display devices include a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP) and an electro-luminescence (EL) display panel, etc.

The EL display panel of such display devices is a self-luminous device capable of light-emitting a phosphorous material by a re-combination of electrons with holes. The EL display device is generally classified into an inorganic EL device using an inorganic compound as the phosphorous material and an organic EL device using an organic compound as it. Such an EL display panel can be driven a low driving voltage (e.g., 10V) unlike other display devices, and has an excellent recognition because it employs a self-luminescence. Also, the EL display panel can implement an ultra thin film device because it does not need a back light unlike the LCD. Furthermore, the EL display panel has advantages of a wider viewing angle and a faster response speed in comparison to the LCD such that it can be highlighted into a post-generation display device.

The organic EL device is usually comprised of an electron injection layer, an electron carrier layer, a light-emitting layer, a hole carrier layer and a hole injection layer that are disposed between a cathode and an anode. In such an organic EL device, when a predetermined voltage is applied between the anode and the cathode, electrons produced from the cathode are moved, via the electron injection layer and the electron carrier layer, into the light-emitting layer while holes produced from the anode are moved, via the hole injection layer and the hole carrier layer, into the light-emitting layer. Thus, the electrons and the holes fed from the electron carrier layer and the hole carrier layer emit a light by their re-combination at the light-emitting layer.

An active matrix EL display panel employing such an organic EL device is largely classified into an analog driving method and a digital driving method.

The analog driving method of the EL display panel is a driving method that controls a current amount fed to an EL cell by an analog signal having a different level in accordance with a video data signal, that is, by a voltage or current, thereby controlling brightness.

On the other hand, the digital driving method of the EL display panel is a driving method that controls a light-emitting time of the EL cell according to a digital video data signal, thereby controlling brightness. In this case, in order to control a light emitting period of the EL cell, one frame is divided into 1st to 6th sub-frames SF 1 to SF 6 when it is intended to a plurality of sub-frames corresponding to each bit of video data, that is, 6-bit video data as shown in FIG. 1 . Further, since different weighting values are given to light-emitting periods of the 1st to 6th sub-frames SF 1 to SF 6 , a ratio LT1:LT2:LT3:LT4:LT5:LT6 of the light-emitting periods of the 1st to 6th sub-frames SF 1 to SF 6 becomes 1:2:4:8:16:32. The 1st to 4th sub-frames SF 1 to SF 4 other than the 5th and 6th sub-frames SF 5 and SF 6 includes non-light-emitting periods UT 1 , UT 2 , UT 3 and UT 4 that are gradually decreased in opposition to the light-emitting periods LT 1 , LT 2 , LT 3 and LT 4 . The EL cells arranged in a matrix type at the EL display panel are scanned, on a line sequence basis, in each light-emitting period LT 1 to LT 6 of the 1st to 6th sub-frames SF 1 to SF 6 to be turned on in accordance with a data signal, thereby providing a light-emission. On the other hand, the EL cells are scanned, on a line sequence basis, in each non-light-emitting period UT 1 to UT 4 of the 1st to 4th sub-frames SF 1 to SF 4 to be turned off, thereby stopping a light-emission. Accordingly, brightness of the EL device is implemented by combining light-emitting times of the sub-frames turned on in accordance with video data.

FIG. 2 is a detailed circuit diagram of one pixel configuring an active matrix EL display panel for providing a digital driving. FIG. 3 is a driving timing diagram of the first sub-frame SF 1 .

The pixel shown in FIG. 2 is comprised of an EL cell OLED, and a cell driver including three PMOS transistors P 1 , P 2 and P 3 and a storage capacitor Cs for driving the EL cell OLED.

The cell driver includes a storage capacitor Cs connected to a power line PL, a first switching PMOS transistor P 1 connected between a data line DL and the storage capacitor Cs to be controlled by a light-emitting scan line SLp, a second switching PMOS transistor P 2 connected between the power line PL and the storage capacitor Cs to be controlled by a non-light-emitting scan line SLe, and a third driving PMOS transistor P 3 connected between a voltage supply line VDD and the EL cell OLED to be controlled by the storage capacitor Cs.

A writing scan line SLp provides a writing signal, that is, a program signal PS for turning on the first PMOS transistor P 1 in a light-emitting period LT of each sub-frame SF. The first PMOS transistor P 1 is turned on by the program signal PS to charge a data signal into the storage capacitor Cs, thereby turning on or off the third PMOS transistor P 3 in accordance with the charged voltage during the light-emitting period LT.

An erasing scan line SLe provides an erasing signal ES for turning on the second PMOS transistor P 2 in a non-light-emitting period UT of each sub-frame SF. The second PMOS transistor P 2 is turned on by the erasing signal SE to discharge the storage capacitor Cs, thereby turning on the third PMOS transistor P 3 during the non-light-emitting period UT.

Referring to FIG. 3 , the first PMOS transistor P 1 is turned on by a low voltage of the program signal PS in the non-light-emitting period LT 1 of the 1st sub-frame SF 1 . Further, a low voltage (“0”) or a high voltage (“1”) of the data signal is supplied via the turned-on first PMOS transistor P 1 to be charged in the storage capacitor Cs. When the low voltage is charged in the storage capacitor Cs, the third PMOS transistor P 3 is turned on to thereby turn on, that is, light-emit the EL cell OLED during the light-emitting period LT. On the other hand, when the high voltage is charged in the storage capacitor Cs, the third PMOS transistor P 3 does not turn off, that is, light-emit the EL cell OLED during the light-emitting period LT.

Then, the second PMOS transistor P 2 is turned on by a low voltage of the erasing signal SE in the non-light-emitting period UT 1 to supply a high-level voltage VDD from the power line PL to a gate electrode of the third PMOS transistor P 3 , thereby discharging the storage capacitor Cs. Thus, the third PMOS transistor P 3 is turned off, thereby allowing the EL cell OLED to be turned off, that is, to provide a non-light-emission in the non-light-emitting period UT.

However, the related art EL display panel has a problem in that, since it allows a current to be flown only in a forward direction (i.e., anode→cathode) at the EL cell for the purpose of light-emitting the EL cell OLED, a life of the EL cell OLED is shortened due to a direct current (DC).

Furthermore, the EL display panel driven by the digital driving method as shown in FIG. 2 also has a problem in that, since it allows a forward direction current to be flown into the EL cell OLED in accordance with a data signal in the light-emitting period LT while allowing a current to be not flown into the EL cell OLED by floating the anode of the EL cell OLED in the non-light-emitting period UT, a life of the EL cell OLED is shortened due to a direct current (DC).

Accordingly, it is an object of the present invention to provide an EL display panel and a driving method thereof wherein a backward bias can be applied to an EL cell in a non-light-emitting period of each sub-frame, thereby preventing a life shortening of the EL device caused by a direct current.

In order to achieve these and other objects of the invention, an electro-luminescence display panel according to one aspect of the present invention implements a gray level by a combination of light-emitting periods of sub-frames corresponding to each bit of video data, wherein each of pixels includes an electro-luminescence (EL) cell; and a cell driver for allowing a forward current to be flown into the EL cell in accordance with a supplied data signal in a light-emitting period of the sub-frame while allowing a backward bias to be applied to the EL cell in a non-light-emitting period of the sub-frame.

In the electro-luminescence display panel, the cell driver includes a storage capacitor having one electrode connected to a power line; a first switching transistor connected between a data line for supplying said data signal and other electrode of the storage capacitor to be controlled by a writing scan line for supplying a writing signal; a second switching transistor connected to the power line and other electrode of the storage capacitor to be controlled by an erasing scan line for supplying an erasing signal; a driving transistor connected between the power line and the EL cell to be controlled by the storage capacitor; and a backward bias transistor connected between the driving transistor and a backward bias voltage input line to be controlled by the storage capacitor in opposition to the driving transistor.

Herein, the first switching transistor is turned on by said writing signal in the light-emitting period to charge said data signal into the capacitor, and the second switching transistor is turned on by said erasing signal in the non-light-emitting period to discharge said data signal charged in the capacitor.

The driving transistor turned on or off in accordance with said voltage charged in the capacitor in the light-emitting period while being turned off by said discharge of the capacitor in the non-light-emitting period, and allows said forward current to be flown into the EL cell when it is turned on in the light-emitting period.

The backward bias transistor is turned on in opposition to the driving transistor in the non-light-emitting period, thereby applying said backward bias to the EL cell.

Further, the backward bias transistor is turned on when the driving transistor is turned off by said data signal charged in the capacitor in the light-emitting period, thereby applying said backward bias to the EL cell.

The backward bias input line is identical to the erasing scan line.

The erasing scan line applies a turn-on voltage of the second switching transistor as said erasing signal in the non-light-emitting period, and said backward bias is applied, via the backward bias transistor, to the EL cell during a period when said turn-on voltage of said erasing signal is applied.

The first and second switching transistors and the driving transistor are PMOS transistors, and the backward bias transistor is a NMOS transistor.

A method of driving an electro-luminescence display panel according to another aspect of the present invention implementing a gray level by a combination of light-emitting periods of sub-frames corresponding to each bit of video data includes the steps of allowing a forward current to be flown into an electro-luminescence (EL) cell in accordance with a data signal in a light-emitting period of the sub-frame; and allowing a backward bias to be applied to the EL cell in a non-light-emitting period of the sub-frame.

In the method, said light-emitting period includes allowing said backward bias to applied to the EL cell when a non-light-emitting data signal for non-light-emitting the EL cell by said data signal is supplied.

Herein, said light-emitting period includes allowing said data signal to be charged, via the first switching transistor, to a capacitor by a writing scan signal from a writing scan line; and turning on a driving transistor in accordance with a voltage charged in the capacitor, thereby allowing said forward current to be flown into the EL cell.

Said non-light-emitting period includes discharging the capacitor through a second switching transistor by an erasing scan signal from an erasing scan line; and turning off the driving transistor while turning on a backward bias transistor by a discharge of the capacitor, thereby applying said backward bias to the EL cell.

Herein, said light-emitting period includes turning off the driving transistor while turning on the backward bias transistor when said data signal is a non-light-emitting data, thereby applying said backward bias to the EL cell.

The backward bias transistor applies any one of said backward bias voltage and said erasing signal to the EL cell in the non-light-emitting period.

Herein, when the backward bias transistor supplies said erasing signal in the non-light-emitting period, said backward bias is applied to the EL cell only in a period when a turn-on voltage for turning on the second driving transistor by said erasing signal is supplied.

These and other objects of the invention will be apparent from the following detailed description of the embodiments of the present invention with reference to the accompanying drawings, in which:

FIG. 1 is a driving timing diagram of one frame according to a digital driving method of a general EL display panel;

FIG. 2 is a detailed circuit diagram of one pixel configuring the related art EL display panel;

FIG. 3 is a digital driving timing diagram of the EL display panel shown in FIG. 2 ;

FIG. 4 is a detailed circuit diagram of one pixel of an EL display panel according to an embodiment of the present invention;

FIG. 5 is a digital driving timing diagram of the EL display panel shown in FIG. 4 ;

FIG. 6 is a detailed circuit diagram of one pixel of an EL display panel according to another embodiment of the present invention;

FIG. 7 is a digital driving timing diagram of the EL display panel shown in FIG. 6 .

Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to FIGS. 4 to 7 .

FIG. 4 is a detailed circuit diagram of one pixel of an active matrix EL display panel for a digital driving according to an embodiment of the present invention, and FIG. 5 is a driving timing diagram of the 1st sub-frame SF 1 of a plurality of sub-frames SF 1 to SF 6 .

Referring to FIG. 4 , the pixel is comprised of an EL cell OLED, and a cell driver including three PMOS transistors P 1 , P 2 and P 3 , a single of NMOS transistor N 1 and a storage capacitor Cs for driving the EL cell OLED.

The cell driver includes a storage capacitor Cs connected to a power line PL, a first switching PMOS transistor P 1 connected between a data line DL and the storage capacitor Cs to be controlled by a light-emitting scan line SLp, a second switching PMOS transistor P 2 connected between the power line PL and the storage capacitor Cs to be controlled by a non-light-emitting scan line SLe, a third driving PMOS transistor P 3 connected between a voltage supply line VDD and the EL cell OLED to be controlled by the storage capacitor Cs, and a first NMOS transistor N 1 connected between the storage capacitor and a backward bias voltage (V 1 ) input line to be controlled by the storage capacitor Cs.

A writing scan line SLp provides a program signal PS for turning on the first PMOS transistor P 1 in a light-emitting period LT of each sub-frame SF The first PMOS transistor P 1 is turned on by the program signal PS to charge the storage capacitor Cs, thereby turning on or off the third PMOS transistor P 3 in accordance with the charged voltage during the light-emitting period LT; whereas the first NMOS transistor N 1 is operated to the contrary. Thus, when the third PMOS transistor P 3 is turned on in the light-emitting period LT, a high-level voltage VDD is supplied to the EL cell OLED such that a forward current is flown into the EL cell OLED, thereby light-emitting the EL cell OLED. On the other hand, when the first NMOS transistor N 1 is turned on in the light-emitting period LT, a backward bias voltage V 1 is supplied to the EL cell OLED to apply a backward bias to the EL cell OLED, thereby providing an aging of the EL cell OLED

An erasing scan line SLe provides an erasing signal ES for turning on the second PMOS transistor P 2 in a non-light-emitting period UT of each sub-frame SF, and the backward bias voltage (V 1 ) input line supplies a direct current backward bias voltage V 1 remaining at a low-level voltage as shown in FIG. 5 . The second PMOS transistor P 2 is turned on by the erasing signal SE to discharge the storage capacitor Cs, thereby turning on the third PMOS transistor P 3 during the non-light-emitting period UT. On the other hand, the first NMOS transistor N 1 is turned on to apply a backward bias to the EL cell OLED, thereby providing an aging of the EL cell OLED.

Referring to FIG. 5 , the first PMOS transistor P 1 is turned on by a low voltage of the program signal PS in the non-light-emitting period LT 1 of the 1st sub-frame SF 1 . Further, a low voltage (“0”) or a high voltage (“1”) of the data signal is supplied via the turned-on first PMOS transistor P 1 , so that the data signal is charged in the storage capacitor Cs. When the low voltage of the data signal is charged in the storage capacitor Cs, the third PMOS transistor P 3 is turned on during the light-emitting period LT such that a forward current is flown into the EL cell OLED, thereby light-emitting the EL cell OLED. On the other hand, when the high voltage of the data signal is charged in the storage capacitor Cs, the third PMOS transistor P 3 is turned off while the first NMOS transistor N 1 being turned on during the light-emitting period LT such that a backward bias is applied to the EL cell OLED, thereby providing an aging of the EL cell OLED.

Then, the second PMOS transistor P 2 is turned on by a low voltage of the erasing signal SE in the non-light-emitting period UT 1 to supply a high-level voltage VDD from the power line PL, thereby discharging the storage capacitor Cs. Thus, the third PMOS transistor P 3 is turned off while the first NMOS transistor N 1 being turned on during the non-light-emitting period UT 1 such that a backward bias is applied to the EL cell OLED, thereby providing an aging of the EL cell OLED.

As described above, the EL display panel according to the embodiment of the present invention applies a forward current when the EL cell OLED is light-emitted while applying a backward bias when the EL cell OLED is not light-emitted, so that it can prevent a life shortening of the EL cell OLED.

FIG. 6 is a detailed circuit diagram of one pixel in an EL display panel according to another embodiment of the present invention, and FIG. 7 is a driving timing diagram.

The pixel shown in FIG. 6 includes the same elements as the pixel shown in FIG. 4 except that the first NMOS transistor N 1 for applying a backward bias employs an erasing signal ES as a backward bias voltage. Thus, a detailed explanation as to the same elements will be omitted.

The first NMOS transistor N 1 shown in FIG. 6 is connected between the third PMOS transistor P 3 and the erasing scan line SLe to be controlled by the storage capacitor Cs. If the second PMOS transistor P 2 is turned on by a low voltage of the erasing signal ES in the non-light-emitting period UT 1 as shown in FIG. 7 , the first NMOS transistor N 1 is turned on in opposition to the third PMOS transistor P 3 due to a discharge of the storage capacitor Cs. The turned-on first NMOS transistor N 1 supplies a low voltage of the erasing signal ES from the erasing scan line SLe to the EL cell OLED such that a backward current is flown into the EL cell OLED, thereby providing an aging of the EL cell OLED. Herein, the first NMOS transistor N 1 allows a backward bias to be applied to the EL cell OLED only in a period when the low voltage of the erasing signal ES is supplied to the erasing scan line SLe.

For instance, when the erasing signal ES remains at a low voltage during the non-light-emitting period UT 1 as shown in FIG. 7 , the first NMOS transistor N 1 allows a backward bias to be applied to the EL cell OLED during the non-light-emitting period UT 1 . On the other hand, when the erasing signal ES remains at a low voltage only in a portion of the non-light-emitting period UT 1 as shown in FIG. 5 , the first NMOS transistor N 1 allows a backward bias to be applied to the EL cell OLED only in the low voltage period.

As described above, according to the present invention, a forward current is applied when the EL cell is light-emitted while a backward bias being applied when the EL cell is not light-emitted in the digital driving method, so that it becomes possible to prevent a life shortening of the EL cell caused by a direct current.

Although the present invention has been explained by the embodiments shown in the drawings described above, it should be understood to the ordinary skilled person in the art that the invention is not limited to the embodiments, but rather that various changes or modifications thereof are possible without departing from the spirit of the invention. Accordingly, the scope of the invention shall be determined only by the appended claims and their equivalents.