Driving voltage control device

This application claims priority under 35 U.S.C. §119 on Patent Application No. 2004-74284 filed in Japan on Mar. 16, 2004, the entire contents of which are hereby incorporated by reference. The entire contents of Patent Application No. 2005-56026 filed in Japan on Mar. 1, 2005 are also incorporated by reference.

1. Field of the Invention

The present invention relates to a device for controlling a driving voltage for driving a load such as a liquid crystal display panel by an AC driving method, and more particularly to a device capable of quickly increasing/decreasing a voltage value of a driving voltage.

2. Description of the Background Art

In order to drive a liquid crystal display panel of a portable device (e.g., a mobile telephone) by an AC driving method (e.g., line inversion driving method), a conventional liquid crystal display driving device includes a driving voltage control device for controlling a driving voltage supplied to the counter electrode of the liquid crystal display panel. The driving voltage control device inverts the polarity of the driving voltage according to a predetermined timing.

FIG. 16 shows a general configuration of a conventional driving voltage control device 9 . The device 9 includes a timing control section 91 , a VCOM voltage generation section 92 , a VCOMH operational amplifier 93 H, a VCOML operational amplifier 93 L, smoothing capacitors C 94 H and C 94 L, switches SW 1 and SW 2 and an output terminal 95 . The device 9 alternately outputs driving voltages VCOMH and VCOML to the counter electrode (not shown) of the liquid crystal display panel.

The timing control section 91 outputs the control signals Sa and Sb. The control signal Sa indicates the voltage value of the driving voltage VCOMH to be generated by the VCOM voltage generation section 92 . The control signal Sb indicates the voltage value of the driving voltage VCOML to be generated by the VCOM voltage generation section 92 . The timing control section 91 receives a timing signal TIMING, and outputs control signals S 1 and S 2 . The timing signal TIMING indicates the timing, according to which the voltage levels of the control signals S 1 and S 2 are switched from “H level” to “L level” (or from “L level” to “H level”).

The VCOM voltage generation section 92 is configured so as to generate the driving voltages VCOMH and VCOML according to the control signals Sa and Sb output from the timing control section 91 . The VCOM voltage generation section 92 may be, for example, an RDAC (Resistance Digital Analog Converter), and has a configuration as shown in FIG. 2 .

The switch SW 1 is connected between a node N 94 H and the output terminal 95 . The switch SW 2 is connected between a node N 94 L and the output terminal 95 . The switches SW 1 and SW 2 are on when the control signals S 1 and S 2 , respectively, from the timing control section 91 are at “H level”, and off when they are at “L level”.

FIG. 16 shows a panel load C(LC) as the load capacitor of the liquid crystal display panel.

Internal Configuration of VCOMH Operational Amplifier 93 H

FIG. 17 shows an internal configuration of the VCOMH operational amplifier 93 H shown in FIG. 16 . The VCOMH operational amplifier 93 H includes input transistors TA 1 -H to TA 5 -H, output transistors TB 1 -H and TB 2 -H and a phase compensation capacitor CB-H. The input transistors TA 1 -H to TA 5 -H together form a differential stage 93 AH of the VCOMH operational amplifier 93 H. The output transistors TB 1 -H and TB 2 -H and the phase compensation capacitor CB-H together form an output stage 93 BH of the VCOMH operational amplifier 93 H.

Internal Configuration of VCOML Operational Amplifier 93 L

FIG. 18 shows an internal configuration of the VCOML operational amplifier 93 L shown in FIG. 16 . The VCOML operational amplifier 93 L includes input transistors TA 1 -L to TA 5 -L, output transistors TB 1 -L and TB 2 -L and a phase compensation capacitor CB-L. The input transistors TA 1 -L to TA 5 -L together form a differential stage 93 AL of the VCOML operational amplifier 93 L. The output transistors TB 1 -L and TB 2 -L and the phase compensation capacitor CB-L together form an output stage 93 BL of the VCOML operational amplifier 93 L.

Operation

Next, an operation of the driving voltage control device 9 shown in FIG. 16 will be described with reference to FIG. 19 . In the illustrated example, the voltage value of the driving voltage VCOMH is “+3 V” and the voltage value of the driving voltage VCOML is “−3 V”.

In the period t 0 -t 1 , the timing control section 91 keeps the control signal S 1 at “L level” and the control signal S 2 at “H level”. A voltage V 95 at the output terminal 95 is “−3 V”.

At time t 1 , the timing control section 91 brings the control signal S 1 to “H level” and the control signal S 2 to “L level” according to the timing signal TIMING. Thus, the switch SW 1 is turned on, and the output terminal 95 is connected to the VCOMH operational amplifier 93 H. Since the potential V 95 at the output terminal 95 (the potential of the panel load C(LC)) is “−3 V”, a current flows from a VCOMH operational amplifier 13 H to the output terminal 95 (the panel load C(LC)) until the potential V 95 at the output terminal 95 reaches “+3 V” (until the rising time tpH elapses).

At time t 3 , the timing control section 91 brings the control signal S 1 to “L level” and the control signal S 2 to “H level” according to the timing signal TIMING from an external component. Thus, the switch SW 2 is turned on, and the output terminal 95 is connected to the VCOML operational amplifier 93 L. Since a potential V 95 at the output terminal 95 is “+3 V”, a current flows from the output terminal 95 to a VCOML operational amplifier 93 L until the potential V 95 at the output terminal 95 reaches “−3 V” (until the falling time tpL elapses).

In the period t 4 -t 9 , an operation similar to that in the period t 0 -t 4 is performed.

Thus, when inverting the polarity of the driving voltage, the panel load C(LC) needs to be charged/discharged, whereby the potential V 95 at the output terminal 95 slowly increases (or decreases).

Moreover, with the recent increase in the resolution of a liquid crystal display panel, the capacitance value of the panel load C(LC) is increasing. Furthermore, with an increasing demand for a mobile telephone capable of displaying a motion picture, the panel load C(LC) needs to be charged/discharged more quickly. In order to quickly charge/discharge the panel load C(LC) having a large capacitance value (i.e., to shorten the rising time tpH and the falling time tpL), it is necessary to apply a high voltage to an operational amplifier included in the driving voltage control device. In view of this, a transistor with a high breakdown voltage is used as the VCOMH operational amplifier 93 H and the VCOML operational amplifier 93 L shown in FIG. 16 .

Driving voltage control devices in which the bias current of an operational amplifier is controlled so as to reduce the power consumption while the circuit area is reduced so as to prevent an increase in cost are known in the art (see, for example, Japanese Laid-Open Patent Publication No. 2003-216256).

However, the operational amplifiers 93 H and 93 L using transistors with a high breakdown voltage have a large circuit area and a very high power consumption. Therefore, where a liquid crystal display panel of a portable device such as a mobile telephone is driven by a liquid crystal display driver using the driving voltage control device 9 shown in FIG. 16 , for example, since the liquid crystal display driver consumes a very large amount of power, the length of time for which the portable device can be used after being fully charged will be very short.

According to one aspect of the present invention, a driving voltage control device includes: a first differential amplifier circuit for receiving a first input voltage and outputting a first output voltage; a second differential amplifier circuit for receiving a second input voltage and outputting a second output voltage; a control section for selecting one of a first mode and a second mode; and an output section for supplying the first output voltage output from the first differential amplifier circuit to an output node when the first mode is selected by the control section and supplying the second output voltage output from the second differential amplifier circuit to the output node when the second mode is selected by the control section. When the first mode is selected, the control section increases a driving power of the first differential amplifier circuit.

In this driving voltage control device, when the first output voltage is supplied (when the operation is in the first mode), the driving power of the first differential amplifier circuit is increased (the amount of current output from the first differential amplifier circuit (or the amount of current input to the first differential amplifier circuit) is increased). Thus, the output node can be quickly charged/discharged. When the second output voltage is supplied (when the operation is not in the first mode), the driving power of the first differential amplifier circuit is not increased. Therefore, no excessive current flows when the output node does not need to be charged/discharged, whereby the power consumption can be reduced.

Preferably, a period of time for which the driving power of the first differential amplifier circuit is increased is shorter than a period of time for which the control section continuously selects the first mode.

With this driving voltage control device, it is possible to further reduce the power consumption. Moreover, the output node can be charged/discharged more quickly than in the prior art, even if the period of time for which the driving power of the first differential amplifier circuit is increased is shorter than the period of time taken for the voltage value of the voltage at the output node to reach the voltage value of the first output voltage.

Preferably, when the first mode is selected, the control section increases the driving power of the first differential amplifier circuit according to a voltage value of a voltage at the output node.

With this driving voltage control device, it is possible to determine whether or not the voltage at the output node has reached a predetermined voltage value by referring to the voltage value of the voltage at the output node. For example, the control section can determine whether or not the voltage at the output node has reached the voltage value of the first output voltage. Thus, it is possible to shorten the period of time for which the driving power of the first differential amplifier circuit is increased, thereby further reducing the power consumption.

Preferably, when the first mode is selected, the control section increases the driving power of the first differential amplifier circuit until the voltage at the output node reaches a first voltage value.

With this driving voltage control device, it is possible to further reduce the power consumption. The output node can be charged/discharged more quickly than in the prior art, even if the absolute value of the first voltage value is smaller than the absolute value of the voltage value of the first output voltage.

Preferably, the control section includes: a mode selector section for selecting one of the first and second modes; a comparator section for comparing the voltage at the output node with a first comparative voltage having the first voltage value; and a driving power adjustment section for increasing the driving power of the first differential amplifier circuit according to the mode selected by the mode selector section and a comparison result from the comparator section.

With this driving voltage control device, the driving power adjustment section can determine whether the first or second output voltage is supplied from the output section by referring to the mode being selected by the mode selector section. Moreover, the driving power adjustment section can determine whether or not the voltage at the output node has reached the first voltage value by referring to the comparison result from the comparator section. Thus, it is possible to shorten the period of time for which the driving power of the first differential amplifier circuit is increased, thereby further reducing the power consumption.

Preferably, the control section increases a driving power of the first differential amplifier circuit when the first mode is selected, and increases a driving power of the second differential amplifier circuit when the second mode is selected.

With this driving voltage control device, the driving power of one differential amplifier circuit (the differential amplifier circuit required to supply the output voltage to the output section) is increased, and the driving power of the other differential amplifier circuit (the differential amplifier circuit not required to supply the output voltage to the output section) is not increased. Thus, the output node can be charged/discharged quickly and the power consumption can be reduced.

Preferably, the control section includes: a mode selector section for selecting one of the first and second modes; a voltage selector section for selecting one of a first comparative voltage having the first voltage value and a second comparative voltage having the second voltage value according to the mode selected by the mode selector section; a comparator section for comparing the voltage at the output node with the voltage selected by the voltage selector section; and a driving power adjustment section for increasing the driving power of the first or second differential amplifier circuit according to the mode selected by the mode selector section and a comparison result from the comparator section.

With this driving voltage control device, the comparator section can determine whether or not the voltage value of the voltage at the output node has reached a voltage value suitable for the mode being selected.

Preferably, the first differential amplifier circuit includes: a first differential stage; first and second output transistors connected in series with each other between a first reference node receiving a first reference voltage and a second reference node receiving a second reference voltage; and a first adjustment transistor. The first output transistor is connected between the first reference node and the second output transistor, and receives at a gate thereof an output of the first differential stage. The second output transistor is connected between the first output transistor and the second reference node, and receives at a gate thereof a voltage applied to a first voltage supply node. The first differential stage outputs a voltage having a voltage value according to a difference between a voltage at a first interconnection node and the first input voltage, the first interconnection node being present between the first output transistor and the second output transistor. When the first mode is selected, the control section sets a connection state of the first adjustment transistor to a first connection state. In the first connection state, the first adjustment transistor is connected between the first reference node and the first interconnection node, and receives at a gate thereof the output of the first differential stage.

In this driving voltage control device, the voltage occurring at the first interconnection node is output as the first output voltage. When the operation is in the first mode, a current flows not only between the first output transistor and the first interconnection node, but also between the first adjustment transistor and the first interconnection node. Therefore, the current flowing between the first reference node and the first interconnection node increases. Thus, the output node can be quickly charged/discharged. When the operation is not in the first mode, no current flows between the first reference node and the first interconnection node. Therefore, no excessive current flows when the output node does not need to be charged/discharged, whereby the power consumption can be reduced.

Preferably, the first differential amplifier circuit includes: a first differential stage; first and second output transistors connected in series with each other between a first reference node receiving a first reference voltage and a second reference node receiving a second reference voltage; and a first adjustment transistor. The first output transistor is connected between the first reference node and the second output transistor, and receives at a gate thereof an output of the first differential stage. The second output transistor is connected between the first output transistor and the second reference node, and receives at a gate thereof a voltage applied to a first voltage supply node. The first differential stage outputs a voltage having a voltage value according to a difference between a voltage at a first interconnection node and the first input voltage, the first interconnection node being present between the first output transistor and the second output transistor. When the first mode is selected, the control section sets a connection state of the first adjustment transistor to a first connection state. In the first connection state, the first adjustment transistor is connected between the first interconnection node and the second reference node, and receives at a gate thereof the voltage applied to the first voltage supply node.

In this driving voltage control device, the voltage occurring at the first interconnection node is output as the first output voltage. When the operation is in the first mode, a current flows not only between the second output transistor and the first interconnection node, but also between the first adjustment transistor and the first interconnection node. Therefore, the current flowing between the second reference node and the second interconnection node increases. Thus, the output node can be quickly charged/discharged. When the operation is not in the first mode, no current flows between the first adjustment transistor and the first interconnection node. Therefore, no excessive current flows when the output node does not need to be charged/discharged, whereby the power consumption can be reduced.

Preferably, the first differential amplifier circuit includes: first and second input transistors connected in series with each other between a first reference node receiving a first reference voltage and a second reference node receiving a second reference voltage; third and fourth input transistors connected in series with each other between the first reference node and the second reference node; a fifth input transistor connected between a first interconnection node and the second reference node, and receives at a gate thereof a voltage applied to a first voltage supply node, the first interconnection node being present between the second input transistor and the fourth input transistor; a first adjustment transistor; and a first output stage. The first input transistor is connected between the first reference node and the second input transistor, and a gate of the first input transistor is connected to a drain of the first input transistor. The second input transistor is connected between the first input transistor and the first interconnection node, and receives at a gate thereof an output of the first output stage. The third input transistor is connected between the first reference node and the fourth input transistor, and a gate of the third input transistor is connected to the gate of the first input transistor. The fourth input transistor is connected between the third input transistor and the first interconnection node, and receives at a gate thereof the first input voltage. The first output stage outputs the first output voltage having a voltage value according to a voltage at a second interconnection node between the third input transistor and the fourth input transistor. When the first mode is selected, the control section sets a connection state of the first adjustment transistor to a first connection state. In the first connection state, the first adjustment transistor is connected between the first interconnection node and the second reference node, and receives at a gate thereof the voltage applied to the first voltage supply node.

In this driving voltage control device, the output of the first output stage is output as the first voltage. When the operation is in the first mode, a current flows not only between the fifth input transistor and the second interconnection node, but also between the first adjustment transistor and the second interconnection node. Therefore, the current flowing between the second reference node and the second interconnection node increases, whereby the voltage received by the first output stage can be quickly increased/decreased. Thus, it is possible to shorten the amount of time required for charging/discharging the output node. When the operation is not in the first mode, no current flows between the first adjustment transistor and the second interconnection node. Therefore, no excessive current flows when the output node does not need to be charged/discharged, whereby the power consumption can be reduced.

Preferably, the first differential amplifier circuit further includes a second adjustment transistor. When the first mode is selected, the control section sets the connection state of the first adjustment transistor to the first connection state and sets a connection state of the second adjustment transistor to a second connection state. In the second connection state, the second adjustment transistor is connected between the first interconnection node and the second reference node, and receives at a gate thereof a voltage applied to the first voltage supply node.

With this driving voltage control device, not only the current flowing between the first interconnection node and the first reference node is increased, but also the current flowing between the first interconnection node and the second reference node is increased, whereby it is possible to suppress an oscillation. Moreover, by setting the second adjustment transistor according to the first adjustment transistor (e.g., setting the size ratio (relationship of W/L ratios of each transistors) between the first adjustment transistor and the second adjustment transistor to be the same as that between the first output transistor and the second output transistor), it is possible to reduce the offset voltage that the first differential amplifier circuit has.

As described above, when the first output voltage is supplied (when the operation is in the first mode), the driving power of the first differential amplifier circuit is increased (the amount of current output from the first differential amplifier circuit (or the amount of current input to the first differential amplifier circuit) is increased). Thus, the output node can be quickly charged/discharged. When the second output voltage is supplied (when the operation is not in the first mode), the driving power of the first differential amplifier circuit is not increased. Therefore, no excessive current flows when the output node does not need to be charged/discharged, whereby the power consumption can be reduced.

FIG. 1 shows a general configuration of a driving voltage control device 1 according to a first embodiment of the present invention.

FIG. 2 shows an internal configuration of a VCOM voltage generation section 12 shown in FIG. 1 .

FIG. 3 shows an internal configuration of the VCOMH operational amplifier 13 H shown in FIG. 1 .

FIG. 4 shows an internal configuration of the VCOML operational amplifier 13 L shown in FIG. 1 ,

FIG. 5 is a waveform diagram showing control signals S 1 to S 4 and the voltage at an output terminal 15 .

FIG. 6A shows a variation of the driving power adjustment section 100 H shown in FIG. 3 .

FIG. 6B shows a variation of the driving power adjustment section 100 H shown in FIG. 3 .

FIG. 6C shows a variation of the driving power adjustment section 100 L shown in FIG. 4 .

FIG. 6D shows a variation of the driving power adjustment section 100 L shown in FIG. 4 .

FIG. 7 shows an internal configuration of a VCOMH operational amplifier 23 H used in a second embodiment of the present invention.

FIG. 8 shows an internal configuration of a VCOML operational amplifier 23 L used in the second embodiment of the present invention.

FIG. 9A shows a variation of the driving power adjustment section 200 H shown in FIG. 7 .

FIG. 9B shows a variation of the driving power adjustment section 200 H shown in FIG. 7 .

FIG. 9C shows a variation of the driving power adjustment section 200 L shown in FIG. 8 .

FIG. 9D shows a variation of the driving power adjustment section 200 L shown in FIG. 8 .

FIG. 10 shows an internal configuration of a VCOMH operational amplifier 33 H used in a third embodiment of the present invention.

FIG. 11 shows an internal configuration of a VCOML operational amplifier 33 L used in the third embodiment of the present invention.

FIG. 12A shows a variation of the driving power adjustment section 300 H shown in FIG. 10 .

FIG. 12B shows a variation of the driving power adjustment section 300 H shown in FIG. 10 .

FIG. 12C shows a variation of the driving power adjustment section 300 L shown in FIG. 11 .

FIG. 12D shows a variation of the driving power adjustment section 300 L shown in FIG. 11 .

FIG. 13 shows a general configuration of a driving voltage control device 4 according to a fourth embodiment of the present invention.

FIG. 14 shows an internal configuration of the timing generation section 42 shown in FIG. 13 .

FIG. 15 is a waveform diagram showing the control signals S 1 to S 4 and the voltage at an output terminal.

FIG. 16 shows a general configuration of the conventional driving voltage control device 9 .

FIG. 17 shows an internal configuration of the VCOMH operational amplifier 93 H shown in FIG. 16 .

FIG. 18 shows an internal configuration of the VCOML operational amplifier 93 L shown in FIG. 16 .

FIG. 19 is a waveform diagram showing the control signals S 1 and S 2 and the voltage at an output terminal 95 .

Preferred embodiments of the present invention will now be described in detail with reference to the drawings. Like elements are denoted by like reference numerals throughout the various figures, and will not be described repeatedly.

First Embodiment

General Configuration

FIG. 1 shows a general configuration of a driving voltage control device 1 according to a first embodiment of the present invention. The device 1 includes a timing control section 11 , a VCOM voltage generation section 12 , the VCOMH operational amplifier 13 H, the VCOML operational amplifier 13 L, smoothing capacitors C 14 H and C 14 L, the switches SW 1 and SW 2 and the output terminal 15 . The device 1 controls the driving voltages VCOMH and VCOML for driving a liquid crystal display panel by an AC driving method (e.g., line inversion driving method). For example, the driving voltage control device 1 alternately outputs the driving voltages VCOMH and VCOML according to a predetermined timing.

The timing control section 11 outputs the control signals Sa and Sb. The control signal Sa indicates the voltage value of the driving voltage VCOM to be generated by the VCOM voltage generation section 12 . The control signal Sb indicates the voltage value of the driving voltage VCOML to be generated by the VCOM voltage generation section 12 . The timing control section 11 receives a timing signal TIMING, and outputs the control signals S 1 to S 4 . The timing signal TIMING indicates the timing according to which the driving voltage output from the output terminal 15 is switched from VCOMH to VCOML (or from VCOML to VCOMH). The timing control section 11 switches the voltage levels of the control signals S 1 to S 4 from “H level” to “L-level” (or from “L level” to “H level”).

The VCOM voltage generation section 12 generates the driving voltage VCOMH having a voltage value according to the control signal Sa output from the timing control section 11 . The VCOM voltage generation section 12 generates the driving voltage VCOML having a voltage value according to the control signal Sb output from the timing control section 11 .

The VCOMH operational amplifier 131 forms a voltage follower circuit, and outputs the driving voltage VCOMH generated by the VCOM voltage generation section 12 . The driving power (the amount of current input/output per unit time) of the VCOMH operational amplifier 13 H is adjusted according to the control signal S 3 output from the timing control section 11 .

The VCOML operational amplifier 13 L forms a voltage follower circuit, and outputs the driving voltage VCOML generated by the VCOM voltage generation section 12 . The driving power (the amount of current input/output per unit time) of the VCOML operational amplifier 13 L is adjusted according to the control signal S 4 output from the timing control section 11 .

The smoothing capacitor C 14 H is provided for the purpose of smoothing the fluctuation in the output of the VCOMH operational amplifier 13 H, and is connected between a node N 14 H (a node between the VCOMH operational amplifier 13 H and the output terminal 15 ) and a ground node. The smoothing capacitor C 14 L is provided for the purpose of smoothing the fluctuation in the output of the VCOML operational amplifier 13 L, and is connected between a node N 14 L (a node between the VCOML operational amplifier 13 L and the output terminal 15 ) and a ground node.

The switch SW 1 is connected between the node N 14 H and the output terminal 15 . The switch SW 2 is connected between the node N 14 L and the output terminal 15 . The switches SW 1 and SW 2 are on when the control signals S 1 and S 2 , respectively, from the timing control section 11 are at “H level”, and off when they are at “L level”.

The output terminal 15 supplies the potential at the node N 14 H (the driving voltage VCOMH) or the potential at the node N 14 L (the driving voltage VCOML) to the counter electrode (not shown) of the liquid crystal display panel.

FIG. 1 shows the panel load C(LC) as the load capacitor of the liquid crystal display panel.

Internal Configuration of VCOM Voltage Generation Section 12

FIG. 2 shows an internal configuration of the VCOM voltage generation section 12 shown in FIG. 1 . The VCOM voltage generation section 12 includes ladder resistors 111 H and 111 L, selector sections 112 H and 112 L and the output terminals 113 H and 113 L.

The ladder resistor 111 H, the selector section 112 H and the output terminal 113 H together form a so-called “RDAC” (Resistance Digital Analog Converter). The ladder resistor 111 H is connected between a reference node VREFH and a reference node VSS, and generates a plurality of divided voltages by dividing the voltage between the reference node VREFH and the reference node VSS. The selector section 112 H selects one of the divided voltages generated by the ladder resistor 111 H according to the control signal Sa output from the timing control section 11 . The output terminal 113 H outputs the divided voltage selected by the selector section 112 H as the driving voltage VCOMH.

The ladder resistor 111 L, the selector section 112 L and the output terminal 113 L together form a so-called “RDAC”. The ladder resistor 111 L is connected between the reference node VSS and a reference node VREFL, and generates a plurality of divided voltages by dividing the voltage between the reference node VSS and the reference node VREFL. The selector section 112 L selects one of the divided voltages generated by the ladder resistor 111 L according to the control signal Sb output from the timing control section 11 . The output terminal 113 L outputs the divided voltage selected by the selector section 112 L as the driving voltage VCOML.

Internal Configuration of VCOMH Operational Amplifier 13 H

FIG. 3 shows an internal configuration of the VCOMH operational amplifier 13 H shown in FIG. 1 . The VCOMH operational amplifier 13 H includes the input transistors TA 1 -H, TA 2 -H, TA 3 -H, TA 4 -H and TA 5 -H, the output transistors TB 1 -H and TB 2 -H, the phase compensation capacitor CB-H and a driving power adjustment section 100 H.

Differential Stage 13 AH

The input transistors TA 1 -H to TA 5 -H together form a differential stage 13 AH of the VCOMH operational amplifier 13 H.

The input transistor TA 5 -H is connected between a power supply node and a ground node, and receives at the gate thereof a bias voltage Va supplied to a bias voltage supply node NVa.

The input transistors TA 1 -H and TA 2 -H are connected in series with each other between a power supply node and the input transistor TA 5 -H. The input transistor TA 1 -H is connected between the power supply node and the input transistor TA 2 -H, with the gate and drain thereof being connected to each other. The input transistor TA 2 -H is connected between the input transistor TA 1 -H and the input transistor TA 5 -H.

The input transistors TA 3 -H and TA 4 -H are connected in series with each other between a power supply node and the input transistor TA 5 -H. The input transistor TA 3 -H is connected between the power supply node and the input transistor TA 4 -H, and the gate thereof is connected to the gate of the input transistor TA 1 -H. The input transistor TA 4 -H is connected between the input transistor TA 3 -H and the input transistor TA 5 -H.

Output Stage 13 BH

The output transistors TB 1 -H and TB 2 -H and the phase compensation capacitor CB-H together form an output stage 13 BH of the VCOMH operational amplifier 13 H.

The output transistors TB 1 -H and TB 2 -H are connected in series with each other between a power supply node and a ground node. The output transistor TB 1 -H is connected between the power supply node and the output transistor TB 2 -H, and the gate thereof is connected to a node N 13 AH. The node N 13 AH is an interconnection node between the input transistor TA 3 -H and the input transistor TA 4 -H. The output transistor TB 2 -H is connected between the output transistor TB 1 -H and the ground node, and receives at the gate thereof the bias voltage Va supplied to the bias voltage supply node NVa. The phase compensation capacitor CB-H is connected between the gate of the output transistor TB 1 -H and a node N 13 BH. The node N 13 BH is an interconnection node between the output transistor TB 1 -H and the output transistor TB 2 -H.

The input transistor TA 4 -H receives at the gate thereof a voltage Vin (the driving voltage VCOMH) from an external component (the VCOM voltage generation section 12 ). The input transistor TA 2 -H receives at the gate thereof the voltage at the node N 13 BH.

Driving Power Adjustment Section 100 H

The driving power adjustment section 100 H includes an inverter 101 H, switching transistors Sa 102 H and Sb 102 H and an adjustment transistor T 103 H.

The inverter 101 H inverts the control signal S 3 from an external component (the timing control section 11 ).

The switching transistors Sa 102 H and Sb 102 H are connected in series with each other between a power supply node and the node N 13 AH. The switching transistor Sa 102 H is connected between the power supply node and the switching transistor Sb 102 H, and receives at the gate thereof the control signal S 3 from an external component (the timing control section 11 ). The switching transistor Sb 102 H is connected between the switching transistor Sa 102 H and the node N 13 AH, and receives at the gate thereof a signal output from the inverter 101 H.

The adjustment transistor T 103 H is connected between the power supply node and the node N 13 BH, and the gate thereof is connected to a node N 102 H. The node N 102 H is an interconnection node between the switching transistor Sa 102 H and the switching transistor Sb 102 H.

The control signal S 3 being at “L level” is a voltage that activates the switching transistors Sa 102 H and Sb 102 H (P-channel transistors), and the control signal S 3 being at “H level” is a voltage that does not activate the switching transistors Sa 102 H and Sb 102 H (P-channel transistors).

Internal Configuration of VCOML Operational Amplifier 13 L

FIG. 4 shows an internal configuration of the VCOML operational amplifier 13 L shown in FIG. 1 . The VCOML operational amplifier 13 L includes the input transistors TA 1 -L, TA 2 -L, TA 3 -L, TA 4 -L and TA 5 -L, the output transistors TB 1 -L and TB 2 -L, the phase compensation capacitor CB-L and a driving power adjustment section 100 L.

Differential Stage 13 AL

The input transistors TA 1 -L to TA 5 -L together form a differential stage 13 AL of the VCOML operational amplifier 13 L.

The input transistor TA 5 -L is connected between a ground node and a power supply node, and receives at the gate thereof a bias voltage Vb supplied to a bias voltage supply node NVb.

The input transistors TA 1 -L and TA 2 -L are connected in series with each other between a ground node and the input transistor TA 5 -L. The input transistor TA 1 -L is connected between the ground node and the input transistor TA 2 -L, with the gate and drain thereof being connected to each other. The input transistor TA 2 -L is connected between the input transistor TA 1 -L and the input transistor TA 5 -L.

The input transistors TA 3 -L and TA 4 -L are connected in series with each other between a ground node and the input transistor TA 5 -L. The input transistor TA 3 -L is connected between the ground node and the input transistor TA 4 -L, and the gate thereof is connected to the input transistor TA 1 -L. The input transistor TA 4 -L is connected between the input transistor TA 3 -L and the input transistor TA 5 -L.

Output Stage 13 BL

The output transistors TB 1 -L and TB 2 -L and the phase compensation capacitor CB-L together form an output stage 13 BL of the VCOML operational amplifier 13 L.

The output transistors TB 1 -L and TB 2 -L are connected in series with each other between a ground node and a power supply node. The output transistor TB 1 -L is connected between the ground node and the output transistor TB 2 -L, and the gate thereof is connected to a node N 13 AL. The node N 13 AL is an interconnection node between the input transistor TA 3 -L and the input transistor TA 4 -L. The output transistor TB 2 -L is connected between the output transistor TB 1 -L and the power supply node, and receives at the gate thereof the bias voltage Vb supplied to the bias voltage supply node NVb. The phase compensation capacitor CB-L is connected between the gate of the output transistor TB 1 -L and a node N 13 BL. The node N 13 BL is an interconnection node between the output transistor TB 1 -L and the output transistor TB 2 -L.

The input transistor TA 4 -L receives at the gate thereof the voltage Vin (the driving voltage VCOML) from an external component (the VCOM voltage generation section 12 ). The input transistor TA 2 -L receives at the gate thereof the voltage at the node N 13 BL.

Driving Power Adjustment Section 100 L

The driving power adjustment section 100 L includes an inverter 101 L, switching transistors Sa 102 L and Sb 102 L and an adjustment transistor T 103 L.

The inverter 101 L inverts the control signal S 4 from an external component (the timing control section 11 ).

The switching transistors Sa 102 L and Sb 102 L are connected in series with each other between a ground node and the node N 13 AL. The switching transistor Sa 102 L is connected between the ground node and the switching transistor Sb 102 L, and receives at the gate thereof a signal output from the inverter 101 L. The switching transistor Sb 102 L is connected between the switching transistor Sa 102 L and the node N 13 AL, and receives at the gate thereof the control signal S 4 from an external component (the timing control section 11 ).

The adjustment transistor T 103 L is connected between the ground node and the node N 13 BL, and the gate thereof is connected to a node N 102 L. The node N 102 L is an interconnection node between the switching transistor Sa 102 L and the switching transistor Sb 102 L.

The control signal S 4 being at “H level” is a voltage that activates the switching transistors Sa 102 L and Sb 102 L (N-channel transistors), and the control signal S 4 being at “L level” is a voltage that does not activate the switching transistors Sa 102 L and Sb 102 L (N-channel transistors).

Operation of VCOMH Operational Amplifier 13 H

Next, an operation of the VCOMH operational amplifier 13 H shown in FIG. 3 will be described.

When the control signal S 3 is at “L level”, the switching transistor Sa 102 H is on. When the control signal S 3 is at “L level”, the inverter 101 H outputs an inverted version of the control signal S 3 (“H level”), whereby the switching transistor Sb 102 H is off. Therefore, the gate of the adjustment transistor T 103 H is connected to the power supply node, and thus the gate and the source of the adjustment transistor T 103 H will be at the same potential, whereby no current flows through the adjustment transistor T 103 H.

When the control signal S 3 is at “H level”, the switching transistor Sa 102 H is off. When the control signal S 3 is at “H level”, the inverter 101 H outputs an inverted version of the control signal S 3 (“L level”), whereby the switching transistor Sb 102 H is on. Since the gate of the adjustment transistor T 103 H is connected to the node N 13 AH, a current flows from the adjustment transistor T 103 H to the node N 13 BH. For example, assume that a drain current whose current value is twice as high as that of a drain current that flows through the output transistor TB 1 -H when the same gate voltage is applied to the adjustment transistor T 103 H and to the output transistor TB 1 -H flows through the adjustment transistor T 103 H. Then, as compared with a case where a drain current flows only through the output transistor TB 1 -H (i.e., where the control signal S 3 is at “L level”), a drain current that is three times as high will flow from the power supply node to the node N 13 BH.

Thus, when the control signal S 3 is at “H level”, the current flowing from the power supply node to the node N 13 BH increases. In other words, the driving power of the output transistor-TB 1 -H increases.

Operation of VCOML Operational Amplifier 13 L

Next, an operation of the VCOML operational amplifier 13 L shown in FIG. 4 will be described.

When the control signal S 4 is at “L level”, the inverter 101 L outputs an inverted version of the control signal S 4 (“H level”), whereby the switching transistor Sa 102 L is on. Moreover, when the control signal S 4 is at “L level”, the switching transistor Sb 102 L is off Therefore, the gate of the adjustment transistor T 103 L is connected to the ground node, and thus the gate and the source of the adjustment transistor T 103 L will be at the same potential, whereby no current flows through the adjustment transistor T 103 L.

When the control signal S 4 is at “H level”, the inverter 101 L outputs an inverted version of the control signal S 4 (“L level”), whereby the switching transistor Sa 102 L is off. Moreover, when the control signal S 4 is at “H level”, the switching transistor Sb 102 L is on. Therefore, the gate of the adjustment transistor T 103 L is connected to the node N 13 AL, whereby a current flows from the node N 13 BL to the adjustment transistor T 103 L.

Thus, when the control signal S 4 is at “H level”, the current flowing from the node N 13 BL to the ground node increases. In other words, the driving power of the output transistor TB 1 -L increases.

Operation of Driving Voltage Control Device 1

Next, an operation of the driving voltage control device 1 shown in FIG. 1 will be described with reference to FIG. 5 . In the illustrated example, the voltage value of the driving voltage VCOMH is “+3 V” and the voltage value of the driving voltage VCOML is “−3 V”.

In the period t 0 -t 1 , the timing control section 11 keeps the control signal S 1 at “L level” and the control signal S 2 at “H level”. Moreover, in the period t 0 -t 1 , a voltage V 15 at the output terminal 15 is “−3 V”.

At time t 1 , the timing control section 11 brings the control signal S 1 to “H level” and the control signal S 2 to “L level” according to the timing signal TIMING from an external component. Thus, the switch SW 1 is turned on, and the output terminal 15 is connected to the VCOMH operational amplifier 13 H. Since the voltage V 15 at the output terminal 15 (the potential of the panel load C(LC)) is “−3 V”, a current flows from the VCOMH operational amplifier 13 H to the output terminal 15 (the panel load C(LC)) until the voltage V 15 at the output terminal 15 reaches the voltage value of the driving voltage VCOMH (“+3 V”) (until the rising time tpH elapses). Moreover, at time t 1 , the timing control section 11 brings the control signal S 3 to “H level”. This increases the driving power of the VCOMH operational amplifier 13 H, thereby increasing the current flowing from the VCOMH operational amplifier 13 H to the output terminal 15 (the panel load C(LC)).

At time t 2 , the timing control section 11 brings the control signal S 3 to “L level”. Thus, the driving power of the VCOMH operational amplifier 13 H returns back to the normal power.

At time t 3 , the timing control section 11 brings the control signal S 1 to “L level” and the control signal S 2 to “H level” according to the timing signal TIMING from an external component. Thus, the switch SW 2 is turned on, and the output terminal 15 is connected to the VCOML operational amplifier 13 L. Since the voltage V 15 at the output terminal 15 is “+3 V”, a current flows from the output terminal 15 to the VCOML operational amplifier 13 L until the voltage V 15 at the output terminal 15 reaches the voltage value of the driving voltage VCOML (“−3 V”) (until the falling time tpL elapses). Moreover, at time t 3 , the timing control section 11 brings the control signal S 4 to “H level”. This increases the driving power of the VCOML operational amplifier 13 L, thereby increasing the current flowing from the output terminal 15 to the VCOML operational amplifier 13 L.

At time t 4 , the timing control section 11 brings the control signal S 4 to “L level”. Thus, the driving power of the VCOML operational amplifier 13 L returns back to the normal power.

Then, in the period t 4 -t 9 , an operation similar to that in the period t 0 -t 4 is performed.

As described above, the driving power of the operational amplifier is increased when the output terminal 15 (the panel load C(LC)) needs to be charged/discharged. When the voltage V 15 at the output terminal 15 (the potential of the panel load C(LC)) is stable, the driving power of the operational amplifier is not increased.

Effects

As described above, the driving power of the VCOMH operational amplifier 13 H (or the VCOML operational amplifier 13 L) is increased when the driving voltage output from the output terminal 15 is switched from one to another, whereby the panel load C(LC) can be quickly charged/discharged. Thus, the rising time tpH (or the falling time tpL) can be shortened.

When the voltage V 15 at the output terminal 15 (the potential of the panel load C(LC)) is stable, the driving power is not increased. Thus, no excessive current flows between the VCOMH operational amplifier 13 HH (or the VCOML operational amplifier 13 L) and the output terminal 15 when the output terminal 15 (the panel load C(LC)) does not need to be charged/discharged, whereby the power consumption can be reduced.

While the present embodiment is directed to a case where the on period of the control signals S 3 and S 4 is ½ that of the control signals S 1 and S 2 , the present invention is not limited to this. The advantageous effects of the present invention can be obtained as long as the on period of the control signals S 3 and S 4 is shorter than or equal to that of the control signals S 1 and S 2 .

Similar effects can be obtained by using a driving power adjustment section 100 H- 1 shown in FIG. 6A or a driving power adjustment section 10011 - 2 shown in FIG. 6B , instead of the driving power adjustment section 100 H shown in FIG. 3 . A switching transistor Sc 102 H shown in FIG. 6A is connected between the adjustment transistor T 103 H and the node N 13 BH, and receives at the gate thereof the output of the inverter 101 H. A switching transistor Sd 102 H shown in FIG. 6B is connected between a power supply node and the adjustment transistor T 103 H, and receives at the gate thereof the output of the inverter 101 H. Thus, the advantageous effects of the present invention can be obtained as long as a current flows between the adjustment transistor T 103 H and the node N 13 BH when the control signal S 3 is at “H level”.

Similarly, similar effects can be obtained by using a driving power adjustment section 100 L- 1 shown in FIG. 6C or a driving power adjustment section 100 L- 2 shown in FIG. 6D , instead of the driving power adjustment section 100 L shown in FIG. 4 . A switching transistor Sc 102 L shown in FIG. 6C is connected between the adjustment transistor T 103 L and the node N 13 BL, and receives at the gate thereof the control signal S 4 . A switching transistor Sd 102 L shown in FIG. 6D is connected between a ground node and the adjustment transistor T 103 L, and receives at the gate thereof the control signal S 4 . Thus, the advantageous effects of the present invention can be obtained as long as a current flows between the adjustment transistor T 103 L and the node N 13 BL when the control signal S 4 is at “H level”.

Moreover, the internal configuration of the VCOM voltage generation section 12 is not limited to that shown in FIG. 2 . For example, the driving voltage VCOMH may be directly supplied from a predetermined power supply to the VCOMH operational amplifier 13 H.

Second Embodiment

When only the driving power of the output transistor TB 1 -H is increased in the VCOMH operational amplifier 13 H, an oscillation may occur. This similarly applies to the VCOML operational amplifier 13 L.

General Configuration

A driving voltage control device according to a second embodiment of the present invention includes a VCOMH operational amplifier 231 H shown in FIG. 7 and a VCOML operational amplifier 23 L shown in FIG. 8 , instead of the VCOMH operational amplifier 13 H and the VCOML operational amplifier 13 L shown in FIG. 1 . Other than this, the configuration is similar to that shown in FIG. 1 .

Internal Configuration of VCOMH Operational Amplifier 23 H

FIG. 7 shows an internal configuration of the VCOMH operational amplifier 23 H used in the present embodiment. The VCOMH operational amplifier 23 H includes a driving power adjustment section 200 H, in addition to the VCOMH operational amplifier 13 H shown in FIG. 3 .

The driving power adjustment section 200 H includes an inverter 201 H, switching transistors Sa 202 H and Sb 202 H and an adjustment transistor T 203 H.

The inverter 201 H inverts the control signal S 3 from an external component (the timing control section 11 ).

The switching transistors Sa 202 H and Sb 202 H are connected in series with each other between a ground node and the bias voltage supply node NVa. The switching transistor Sa 202 H is connected between the ground node and the switching transistor Sb 202 H, and receives at the gate thereof a signal output from the inverter 201 H. The switching transistor Sb 202 H is connected between the switching transistor Sa 202 H and the bias voltage supply node NVa, and receives at the gate thereof the control signal S 3 from an external component (the timing control section 11 ).

The adjustment transistor T 203 H is connected between the ground node and the node N 13 BH, and the gate thereof is connected to a node N 202 H. The node N 202 H is an interconnection node between the switching transistor Sa 202 H and the switching transistor Sb 202 H.

The control signal S 3 being at “L level” is a voltage that activates the switching transistors Sa 102 H and Sb 102 H (P-channel transistors) and does not activate the switching transistors Sa 202 H and Sb 202 H (N-channel transistors), and the control signal S 3 being at “H level” is a voltage that does not activate the switching transistors Sa 102 H and Sb 102 H (P-channel transistors) and activates the switching transistors Sa 202 H and Sb 202 H (N-channel transistors).

Internal Configuration of VCOML Operational Amplifier 23 L

FIG. 8 shows an internal configuration of the VCOML operational amplifier 23 L used in the present embodiment. The VCOML operational amplifier 23 L includes a driving power adjustment section 200 L, in addition to the VCOML operational amplifier 13 L shown in FIG. 4 .

The driving power adjustment section 200 L includes an inverter 201 L, switching transistors Sa 202 L and Sb 202 L and an adjustment transistor T 203 L.

The inverter 201 L inverts the control signal S 4 from an external component (the timing control section 11 ).

The switching transistors Sa 202 L and Sb 202 L are connected in series with each other between a power supply node and the bias-voltage supply node NVb. The switching transistor Sa 202 L is connected between the power supply node and the switching transistor Sb 202 L, and receives at the gate thereof the control signal S 4 from an external component (the timing control section 11 ). The switching transistor Sb 202 L is connected between the switching transistor Sa 202 L and the bias voltage supply node NVb, and receives at the gate thereof a signal output from the inverter 201 L.

The adjustment transistor T 203 L is connected between the power supply node and the node N 13 BL, and the gate thereof is connected to a node N 202 L. The node N 202 L is an interconnection node between the switching transistor Sa 202 L and the switching transistor Sb 202 L.

The control signal S 4 being at “H level” is a voltage that activates the switching transistors Sa 102 L and Sb 102 L (N-channel transistors) and does not activate the switching transistors Sa 202 L and Sb 202 L (P-channel transistors), and the control signal S 4 being at “L level” is a voltage that does not activate the switching transistors Sa 102 L and Sb 102 L (N-channel transistors) and activates the switching transistors Sa 202 L and Sb 202 L (P-channel transistors).

Operation of VCOMH Operational Amplifier 23 H

Next, an operation of the VCOMH operational amplifier 23 H shown in FIG. 7 will be described. The operation of the VCOMH operational amplifier 23 H is similar to that of the VCOMH operational amplifier 13 H shown in FIG. 3 except for the operation of the driving power adjustment section 200 H.

When the control signal S 3 is at “L level”, the inverter 201 H outputs an inverted version of the control signal S 3 (“H level”), whereby the switching transistor Sa 202 H is on. Moreover, when the control signal S 3 is at “L level”, the switching transistor Sb 202 H is off. Therefore, the gate of the adjustment transistor T 203 H is connected to the ground node, and thus the gate and the source of the adjustment transistor T 203 H will be at the same potential, whereby no current flows through the adjustment transistor T 203 H.

When the control signal S 3 is at “H level”, the inverter 201 H outputs an inverted version of the control signal S 3 (“L level”), whereby the switching transistor Sa 202 H is off. Moreover, when the control signal S 3 is at “H level”, the switching transistor Sb 202 H is on. Therefore, the gate of the adjustment transistor T 203 H is connected to the bias voltage supply node NVa, whereby a current flows from the node N 13 BH to the adjustment transistor T 203 H.

Thus, when the control signal S 3 is at “H level”, the current flowing from the node N 13 BH to the ground node increases. In other words, the driving power of the output transistor TB 1 -H increases, and the driving power of the output transistor TB 2 -H also increases.

Operation of the VCOML Operational Amplifier 23 L

Next, an operation of the VCOML operational amplifier 23 L shown in FIG. 8 will be described.

When the control signal S 4 is at “L level”, the switching transistor Sa 202 L is on. Moreover, when the control signal S 4 is at “L level”, the inverter 201 L outputs an inverted version of the control signal S 4 (“H level”), whereby the switching transistor Sb 202 L is off. Therefore, the gate of the adjustment transistor T 203 L is connected to the power supply node, and thus the gate and the source of the adjustment transistor T 203 L will be at the same potential, whereby no current flows through the adjustment transistor T 203 L.

When the control signal S 4 is at “H level”, the switching transistor Sa 202 L is off. Moreover, when the control signal S 4 is at “H level”, the inverter 201 L outputs an inverted version of the control signal S 4 (“L level”), whereby the switching transistor Sb 202 L is on. Therefore, the gate of the adjustment transistor T 203 L is connected to the bias voltage supply node NVb, whereby a current flows from the adjustment transistor T 203 L to the node N 13 BL.

Thus, when the control signal S 4 is at “H level”, the current flowing from the power supply node to the node N 13 BL increases. In other words, the driving power of the output transistor TB 1 -L increases, and the driving power of the output transistor TB 2 -L also increases.

Effects

As described above, the driving power of the VCOMH operational amplifier 23 H (or the VCOML operational amplifier 23 L) is increased when the driving voltage output from the output terminal 15 is switched from one to another, whereby the panel load C(LC) can be quickly charged/discharged. Thus, the rising time tpH (or the falling time tpL) can be shortened.

When the voltage V 15 at the output terminal 15 (the potential of the panel load C(LC)) is stable, the driving power is not increased. Thus, no excessive current flows between the VCOMH operational amplifier 23 H (or the VCOML operational amplifier 23 L) and the output terminal 15 when the output terminal 15 (the panel load C(LC)) does not need to be charged/discharged, whereby the power consumption can be reduced.

Moreover, by increasing the driving power of the output transistor TB 2 -H (or TB 2 -L) along with the increase in the driving power of the output transistor TB 1 -H (or TB 1 -L), it is possible to suppress an oscillation.

Moreover, by setting the adjustment transistor T 203 H (T 203 L) according to the adjustment transistor T 103 H (T 103 L) (e.g., setting the size ratio (relationship of W/L ratios of each transistors) between the adjustment transistor T 103 H (T 103 L) and the adjustment transistor T 203 H (T 203 L) to be the same as that between the output transistor TB 1 -H (TB 1 -L) and the output transistor TB 2 -H (TB 2 -L)), it is possible to reduce the offset voltage that the VCOMH differential amplifier circuit 23 H (VCOMH differential amplifier circuit 23 L) has.

Effects similar to those of the VCOMH operational amplifier 13 H shown in FIG. 3 can be obtained also when only the driving power adjustment section 200 H is provided without providing the driving power adjustment section 100 H in the VCOMH operational amplifier 23 H shown in FIG. 7 . Moreover, effects similar to those of the VCOML operational amplifier 13 L shown in FIG. 4 can be obtained also when only the driving power adjustment section 200 L is provided without providing the driving power adjustment section 100 L in the VCOML operational amplifier 23 L shown in FIG. 8 .

Similar effects can be obtained by using the driving power adjustment section 200 H- 1 shown in FIG. 9A or the driving power adjustment section 200 H- 2 shown in FIG. 9B , instead of the driving power adjustment section 200 H shown in FIG. 7 . The switching transistor Sc 202 H shown in FIG. 9A is connected between the adjustment transistor T 203 H and the node N 13 BH, and receives at the gate thereof the control signal S 3 . The switching transistor Sd 202 H shown in FIG. 9B is connected between a ground node and the adjustment transistor T 203 H, and receives at the gate thereof the control signal S 3 . Thus, the advantageous effects of the present invention can be obtained as long as a current flows between the adjustment transistor T 203 H and the node N 13 BH when the control signal S 3 is at “H level”.

Similarly, similar effects can be obtained by using the driving power adjustment section 200 L- 1 shown in FIG. 9C or the driving power adjustment section 200 L- 2 shown in FIG. 9D , instead of the driving power adjustment section 200 L shown in FIG. 8 . The switching transistor Sc 202 L shown in FIG. 9C is connected between the adjustment transistor T 203 L and the node N 13 BL, and receives at the gate thereof the output of the inverter 201 L. The switching transistor Sd 202 L shown in FIG. 9D is connected between a power supply node and the adjustment transistor T 203 L, and receives at the gate thereof the output of the inverter 201 L. Thus, the advantageous effects of the present invention can be obtained as long as a current flows between the adjustment transistor T 203 L and the node N 13 BL when the control signal S 4 is at “H level”.

Third Embodiment

General Configuration

A driving voltage control device according to a third embodiment of the present invention includes a VCOMH operational amplifier 33 H shown in FIG. 10 and a VCOML operational amplifier 33 L shown in FIG. 11 , instead of the VCOM operational amplifier 13 H and the VCOML operational amplifier 13 L shown in FIG. 1 . Other than this, the configuration is similar to that shown in FIG. 1 .

Internal Configuration of VCOMH Operational Amplifier 33 H

FIG. 10 shows an internal configuration of the VCOMH operational amplifier 33 H used in the present embodiment. The VCOMH operational amplifier 33 H includes a driving power adjustment section 300 H, instead of the driving power adjustment section 100 H shown in FIG. 3 .

The driving power adjustment section 300 H includes an inverter 301 H, switching transistors Sa 302 H and Sb 302 H and an adjustment transistor T 303 H.

The inverter 301 H inverts the control signal S 3 from an external component (the timing control section 11 ).

The switching transistors Sa 302 H and Sb 302 H are connected in series with each other between a ground node and the bias voltage supply node NVa. The switching transistor Sa 302 H is connected between the ground node and the switching transistor Sb 302 H, and receives at the gate thereof a signal output from the inverter 301 H. The switching transistor Sb 302 H is connected between the switching transistor Sa 302 H and the bias voltage supply node NVa, and receives at the gate thereof the control signal S 3 from an external component (the timing control section 11 ).

The adjustment transistor T 303 H is connected between the ground node and the drain of the input transistor TA 5 -H, and the gate thereof is connected to a node N 302 H. The node N 302 H is an interconnection node between the switching transistor Sa 302 H and the switching transistor Sb 302 H.

Internal Configuration of VCOML Operational Amplifier 33 L

FIG. 11 shows an internal configuration of the VCOML operational amplifier 33 L used in the present embodiment. The VCOML operational amplifier 33 L includes a driving power adjustment section 300 L, instead of the driving power adjustment section 100 L shown in FIG. 4 .

The driving power adjustment section 300 L includes an inverter 301 L, switching transistors Sa 302 L and Sb 302 L and an adjustment transistor T 303 L.

The inverter 301 L inverts the control signal S 4 from an external component (the timing control section 11 ).

The switching transistors Sa 302 L and Sb 302 L are connected in series with each other between a power supply node and the bias voltage supply node NVb. The switching transistor Sa 302 L is connected between the power supply node and the switching transistor Sb 302 L, and receives at the gate thereof the control signal S 4 from an external component (the timing control section 11 ). The switching transistor Sb 302 L is connected between the switching transistor Sa 302 L and the bias voltage supply node NVb, and receives at the gate thereof a signal output from the inverter 301 L.

The adjustment transistor T 303 L is connected between the power supply node and the drain of the input transistor TA 5 -L, and the gate thereof is connected to a node N 302 L. The node N 302 L is an interconnection node between the switching transistor Sa 302 L and the switching transistor Sb 302 L.

Operation of VCOMH Operational Amplifier 33 H

Next, an operation of the VCOMH operational amplifier 33 H shown in FIG. 10 will be described.

When the control signal S 3 is at “L level”, the inverter 301 H outputs an inverted version of the control signal S 3 (“H level”), whereby the switching transistor Sa 302 H is on. Moreover, when the control signal S 3 is at “L level”, the switching transistor Sb 302 H is off. Therefore, the gate of the adjustment transistor T 303 H is connected to the ground node, and thus the gate and the source of the adjustment transistor T 303 H will be at the same potential, whereby no drain current flows through the adjustment transistor T 303 H.

When the control signal S 3 is at “H level”, the inverter 301 H outputs an inverted version of the control signal S 3 (“L level”), whereby the switching transistor Sa 302 H is off. Moreover, when the control signal S 3 is at “H level”, the switching transistor Sb 302 H is on. Therefore, the gate of the adjustment transistor T 303 H is connected to the bias voltage supply node NVa, whereby the current flowing through the input transistors TA 3 -H and TA 4 -H increases. Thus, the current flowing from the node N 13 AH to the phase compensation capacitor CB-H increases.

Thus, when the control signal S 3 is at “H level”, the current flowing from the node N 13 AH to the phase compensation capacitor CB- 1 increases, whereby the amount of time required for charging the phase compensation capacitor CB-H is shortened.

Operation of VCOML Operational Amplifier 33 L

Next, an operation of the VCOML operational amplifier 33 L shown in FIG. 11 will be described.

When the control signal S 4 is at “L level”, the switching transistor Sa 302 L is on. Moreover, when the control signal S 4 is at “L level”, the inverter 301 L outputs an inverted version of the control signal S 4 (“H level”), whereby the switching transistor Sb 302 L is off. Therefore, the gate of the adjustment transistor T 303 L is connected to the power supply node, and thus the gate and the source of the adjustment transistor T 303 L will be at the same potential, whereby no current flows through the adjustment transistor T 303 L.

When the control signal S 4 is at “H level”, the switching transistor Sa 302 H is off Moreover, when the control signal S 4 is at “H level”, the inverter 301 L outputs an inverted version of the control signal S 4 (“L level”), whereby the switching transistor Sb 302 L is on. Therefore, the gate of the adjustment transistor T 303 L is connected to the bias voltage supply node NVb, whereby the current flowing through the input transistors TA 3 -L and TA 4 -L increases. Thus, the current flowing from the phase compensation capacitor CB-L to the node N 13 AL increases.

Thus, when the control signal S 4 is at “H level”, the current flowing from the phase compensation capacitor CB-L to the node N 13 AL increases, whereby the amount of time required for discharging the phase compensation capacitor CB-L is shortened.

Effects

As described above, when the driving voltage output from the output terminal 15 is switched from one to another, the phase compensation capacitor CB-H can be charged quickly (or the phase compensation capacitor CB-L can be discharged quickly). Therefore, the potential at the node N 13 BH can be increased quickly (or the potential at the node N 13 BL can be decreased quickly), whereby the panel load C(LC) can be quickly charged/discharged. Thus, the rising time tpH (or the falling time tpL) can be shortened.

When the potential V 15 at the output terminal 15 (the potential of the panel load C(LC)) is stable, the driving power is not increased. Thus, no excessive current flows between the VCOMH operational amplifier 33 H (or the VCOML operational amplifier 33 L) and the output terminal 15 when the output terminal 15 (the panel load C(LC)) does not need to be charged/discharged, whereby the power consumption can be reduced.

The driving power adjustment section 100 H shown in FIG. 3 and the driving power adjustment section 200 H shown in FIG. 7 may be further provided to the VCOMH operational amplifier 33 H shown in FIG. 10 . With such a configuration, the panel load C(LC) can be charged/discharged even more quickly.

The driving power adjustment section 100 L shown in FIG. 4 and the driving power adjustment section 200 L shown in FIG. 8 can be further provided to the VCOML operational amplifier 33 L shown in FIG. 11 .

Similar effects can be obtained by using a driving power adjustment section 300 H- 1 shown in FIG. 12A or a driving power adjustment section 300 H- 2 shown in FIG. 12B , instead of the driving power adjustment section 300 H shown in FIG. 10 . A switching transistor Sc 302 H shown in FIG. 12A is connected between the adjustment transistor T 303 H and the drain of the input transistor TA 5 -H (the interconnection node between the input transistor TA 2 -H and the input transistor TA 4 -H), and receives at the gate thereof the control signal S 3 . A switching transistor Sd 302 H shown in FIG. 12B is connected between a ground node and the adjustment transistor T 303 H, and receives at the gate thereof the control signal S 3 . Thus, the advantageous effects of the present invention can be obtained as long as a current flows between the adjustment transistor T 303 H and the input transistors TA 2 -H and TA 4 -H when the control signal S 3 is at “H level”.

Similarly, similar effects can be obtained by using a driving power adjustment section 300 L- 1 shown in FIG. 12C or a driving power adjustment section 300 L- 2 shown in FIG. 12D , instead of the driving power adjustment section 300 L shown in FIG. 11 . A switching transistor Sc 302 L shown in FIG. 12C is connected between the adjustment transistor T 303 L and the drain of the input transistor TA 5 -L (the interconnection node between the input transistor TA 2 -L and the input transistor TA 4 -L), and receives at the gate thereof the output of the inverter 301 L. A switching transistor Sd 302 L shown in FIG. 12D is connected between a power supply node and the adjustment transistor T 303 L, and receives at the gate thereof the output of the inverter 301 L. Thus, the advantageous effects of the present invention can be obtained as long as a current flows between the adjustment transistor T 303 L and the input transistors TA 2 -L and TA 4 -L when the control signal S 4 is at “H level”.

Fourth Embodiment

General Configuration

FIG. 13 shows a general configuration of a driving voltage control device 4 according to a fourth embodiment of the present invention. The device 4 includes a timing control section 41 and a timing generation section 42 , instead of the timing control section 11 shown in FIG. 1 . Other than this, the configuration is similar to that shown in FIG. 1 .

As does the timing control section 11 , the timing control section 41 outputs the control signals Sa and Sb to the VCOM voltage generation section 12 , and outputs the control signals S 1 and S 2 according to the timing control signal TIMING from an external component.

The timing generation section 42 outputs the control signals S 3 and S 4 according to the voltage level of the control signal S 1 and the voltage value of the voltage V 15 at the output terminal 15 .

Internal Configuration of Timing Generation Section 42

FIG. 14 shows an internal configuration of the timing generation section 42 shown in FIG. 13 .

The timing generation section 42 includes the input nodes N 42 H and N 42 L, a ladder resistor 401 , a switch 402 , a comparator 403 and AND circuits 404 H and 404 L.

The input node N 42 H receives the driving voltage VCOM generated by the VCOM voltage generation section 12 . The input node N 42 L receives the driving voltage VCOML generated by the VCOM voltage generation section 12 .

The ladder resistor 401 is connected between the input node N 42 H and the input node N 42 L, and generates a plurality of divided voltages by dividing the voltage between the input node N 42 H and the input node N 42 L.

The switch 402 receives one of the divided voltages generated by the ladder resistor 401 as an H-level reference voltage VrH and another one of the divided voltages whose voltage value is lower than the H-level reference voltage VrH as an L-level reference voltage VrL, and receives the control signal S 1 from an external component (the timing control section 41 ). The switch 402 outputs the H-level reference voltage VrH from the ladder resistor 401 to the comparator 403 when the control signal S 1 is at “H level”, and outputs the L-level reference voltage VrL from the ladder resistor 401 to the comparator 403 when the control signal S 1 is at “L level”.

The comparator 403 receives at the non-inverted input terminal thereof the voltage output from the switch 402 (the H-level reference voltage VrH or the L-level reference voltage VrL), and receives at the inverted input terminal thereof the voltage V 15 from an external component (the output terminal 15 ). Moreover, the comparator 403 outputs a determination signal S 403 indicating “H level” when the voltage V 15 from an external component (the output terminal 15 ) is lower than the voltage output from the switch 402 , and outputs the determination signal S 403 indicating “L level” when the voltage V 15 from the external component (the output terminal 15 ) is higher than the voltage output from the switch 402 .

The AND circuit 404 H receives at one input terminal thereof the control signal S 1 from an external component (the timing control section 41 ), and receives at the other input terminal thereof the determination signal S 403 output from the comparator 403 . Moreover, the AND circuit 404 H outputs the control signal S 3 indicating “H level” when the control signal S 1 from an external component (the timing control section 41 ) and the determination signal S 403 output from the comparator 403 both indicate “H level”, and otherwise outputs the control signal S 3 indicating “L level”.

The AND circuit 404 L receives at one input terminal thereof an inverted version of the control signal S 1 from an external component (the timing control section 41 ), and receives at the other input terminal thereof an inverted version of the determination signal S 403 output from the comparator 403 . Moreover, the AND circuit 404 L outputs the control signal S 4 indicating “H level” when the control signal S 1 from an external component (the timing control section 41 ) and the determination signal S 403 output from the comparator 403 both indicate “L level”, and otherwise outputs the control signal S 4 indicating “L level”.

Operation

Next, an operation of the timing generation section 42 shown in FIG. 14 will be described with reference to FIG. 15 . In the illustrated example, the voltage value of the H-level reference voltage VrH is “+2.5 V”, and the voltage value of the L-level reference voltage VrL is “−2.5 V”.

In the period t 0 -t 1 , the timing control section 41 keeps the control signal S 1 at “L level” and the control signal S 2 at “H level”. Moreover, in the period t 0 -t 1 , the voltage V 15 at the output terminal 15 is “−3 V”. Since the control signal S 1 is at “L-level”, the switch 402 outputs the L-level reference voltage VrL (−2.5 V) to the comparator 403 . Moreover, the voltage V 15 at the output terminal 15 is “−3 V”. Since the voltage value of the voltage V 15 at the output terminal 15 (−3 V) is lower than that of the L-level reference voltage VrL (−2.5 V), the comparator 403 outputs the determination signal S 403 indicating “H level”. The control signal S 1 indicates “L level” while the determination signal S 403 from the comparator 403 indicates “H level”, whereby the AND circuit 404 H outputs the control signal S 3 indicating “L level”, and the AND circuit 404 L outputs the control signal S 4 indicating “L level”.

At time t 1 , the timing control section 41 brings the control signal S 1 to “H level” and the control signal S 2 to “L level”. Since the control signal S 1 indicates “H level”, the switch 402 outputs the H-level reference voltage VrH (+2.5 V) to the comparator 403 . Moreover, the voltage V 15 at the output terminal 15 is “−3 V”. Since the voltage value of the voltage V 15 at the output terminal 15 (−3 V) is lower than the voltage value of the H-level reference voltage VrH (+2.5 V), the comparator 403 outputs the determination signal S 403 indicating “H level”. The control signal S 1 indicates “H level” while the determination signal S 403 from the comparator 403 indicates “H level”, whereby the AND circuit 404 H outputs the control signal S 3 indicating “H level” and the AND circuit 404 L outputs the control signal S 4 indicating “L level”.

The voltage V 15 at the output terminal 15 is lower than “+2.5 V” until the charging time trH elapses from time t 1 . Therefore, the comparator 403 keeps outputting the determination signal S 403 indicating “H level”. The control signal S 1 indicates “H level” while the determination signal S 403 from the comparator 403 indicates “H level”, whereby the AND circuit 404 H outputs the control signal S 3 indicating “H level” and the AND circuit 404 L outputs the control signal S 4 indicating “L level”.

The voltage V 15 at the output terminal 15 reaches “+2.5 V” when the charging time trH elapses from time t 4 . Thereafter, as the voltage value of the voltage V 15 becomes higher than the voltage value of the H-level reference voltage VrH (+2.5 V), the comparator 403 outputs the determination signal S 403 indicating “L level”. The control signal S 1 indicates “H level” while the determination signal S 403 from the comparator 403 indicates “L level”, whereby the AND circuit 404 H outputs the control signal S 3 indicating “L level” and the AND circuit 404 L outputs the control signal S 4 indicating “L level”.

At time t 3 , the timing control section 41 brings the control signal S 1 to “L level” and the control signal S 2 to “H level”. Since the control signal S 1 indicates “L level”, the switch 402 outputs the L-level reference voltage VrL (−2.5 V) to the comparator 403 . Moreover, the voltage V 15 at the output terminal 15 indicates a voltage value of “+3 V”. Since the voltage value of the voltage V 15 at the output terminal 15 (+3 V) is higher than the voltage value of the L-level reference voltage VrL (−2.5 V), the comparator 403 outputs the determination signal S 403 indicating “L level”. The control signal S 1 indicates “L level” while the determination signal S 403 from the comparator 403 indicates “L level”, whereby the AND circuit 404 H outputs the control signal S 3 indicating “L level” and the AND circuit 404 L outputs the control signal S 4 indicating “H level”.

The voltage V 15 at the output terminal 15 is higher than “−2.5 V” until the discharging time trL elapses from time t 3 . Therefore, the comparator 403 keeps outputting the determination signal S 403 indicating “L level”. The control signal S 1 indicates “L level” while the determination signal S 403 from the comparator 403 indicates “L level”, whereby the AND circuit 404 H outputs the control signal S 3 indicating “L level” and the AND circuit 404 L outputs the control signal S 4 indicating “H level”.

The voltage V 15 at the output terminal 15 reaches “−2.5 V” when the discharging time trL elapses from time t 3 . Thereafter as the voltage value of the voltage V 15 becomes lower than the voltage value of the L-level reference voltage VrL (−2.5 V), the comparator 403 outputs the determination signal S 403 indicating “H level”. The control signal S 1 indicates “L level” while the determination signal S 403 from the comparator 403 indicates “H level”, whereby the AND circuit 404 H outputs the control signal S 3 indicating “L level” and the AND circuit 404 L outputs the control signal S 4 indicating “L level”.

Then, in the period t 4 -t 9 , an operation similar to that in the period t 0 -t 4 is performed.

Effects

As described above, when the potential at the output terminal 15 (the potential at the panel load C(LC)) reaches a predetermined reference value, the driving power of the VCOMH operational amplifier 13 H (or the VCOML operational amplifier 13 L) returns back to the normal power. Thus, it is possible to further reduce the power consumption.

The VCOMH operational amplifier 23 H shown in FIG. 7 and the VCOML operational amplifier 23 L shown in FIG. 8 may be used instead of the VCOMH operational amplifier 13 H and the VCOML operational amplifier 13 L shown in FIG. 13 . Moreover, the VCOMH operational amplifier 33 H shown in FIG. 10 and the VCOML operational amplifier 33 L shown in FIG. 11 may be used instead of the VCOMH operational amplifier 13 H and the VCOML operational amplifier 13 L shown in FIG. 13 .

The ladder resistor 401 may be implemented by means of the ladder resistor 111 H and the ladder resistor 111 L shown in FIG. 2 .

While the H-level reference voltage VrH and the L-level reference voltage VrL are generated by the ladder resistor 401 in the present embodiment, they may be generated by any other suitable method. Moreover, the voltage values of the H-level reference voltage VrH and the L-level reference voltage VrL may be determined arbitrarily.

In any of the embodiments above, the VCOMH and VCOML operational amplifiers may be class-A or class-AB operational amplifiers, or the like. With any operational amplifier, the advantageous effects of the present invention can be obtained as long as the driving power of the differential stage or the output stage is optimized by a control signal.

While the time segments T 1 to T 9 are shown to be equal in length in various waveform diagrams for the sake of simplicity, the present invention is not limited to this.

The driving voltage control device of the present invention is useful in applications such as a driving voltage control device for controlling driving voltages for driving loads such as liquid crystal display panels by an AC driving method.