CMOS reference voltage circuit

This application is a divisional of U.S. patent application Ser. No. 10/091,776, filed Mar. 5, 2002, now U.S. Pat. No. 6,900,689, issued May 31, 2005.

This invention relates to a reference voltage circuit. More particularly, it relates to a CMOS reference voltage circuit which is preferably formed on a semiconductor integrated circuit and outputs a temperature-independent reference voltage.

Up to now, there have been a large number of publications regarding a reference voltage circuit which demonstrates a temperature independent characteristic by canceling a temperature dependent characteristic and which outputs a reference voltage of the order of 1.2 V.

First, the operation of a conventional reference voltage circuit is explained.

FIG. 10 shows an example of a conventional CMOS (Complementary MOS) reference voltage circuit. The reference voltage is obtained by inserting a resistor in a current loop of a reference current circuit which is termed a PTAT (Proportional to Absolute Temperature) current source circuit since in general the reference current circuit outputs the current proportional to temperature.

In FIG. 10 , it is assumed that a transistor Q 1 is a unit transistor and that the emitter area of a transistor Q 2 is K 1 times that of the unit transistor (K 1 >1).

If the base width modulation is neglected, the relationship between the collector current IC to the base-to-emitter voltage VBE of a transistor is given by:

IC=K·IS exp( VBE/VT )  (1)

where IS is the saturation current of a unit transistor and VT is the thermal voltage, which is given by:

VT=kT/q

where

q is the magnitude of the unit electron charge,

k is Boltzmann's constant,

T is absolute temperature in kelvins, and

K is the emitter area ratio referenced to the unit transistor.

Assuming that the DC current amplification factor of a transistor is sufficiently close to 1, and the base current is neglected, we shall find the following relationships:

VBE 1= VT ln { IC 1/ IS}   (2)

VBE 2= VT ln ( IC 2/( K 1· IS ))  (3)

VBE 1= VBE 2+ R 1· IC 2  (4)

where ln { } is a logarithmic function.

By solving the equation (2) to (4), we obtain

VT ln { K 1 ·IC 1 /IC 2}= R 1 ·IC 2  (5)

It is noted that, since transistors Q 1 and Q 2 controls the common gate voltage of transistors M 3 and M 4 through an operational amplifier 20 so that the equation (4) will be held valid, the transistors Q 1 and Q 2 are self-biased, and hence the drain currents ID 3 and ID 4 of the transistors M 3 and M 4 are equal to each other and

ID3=ID4=IC1=IC2  (6)

From the equation (5), we shall therefore have the following equation:

ID 3 =ID 4 =IC 1 =IC 2 =VT ln ( K 1)/ R 1  (7)

The drain current ID 3 of the transistor M 3 is converted by the resistor R 2 to a voltage and becomes the reference voltage VREF. That is, the reference voltage VREF is expressed as follow.

In the equation (8), the base-to-emitter voltage VBE 1 of the transistor Q 1 , which is driven by the PTAT reference current, has a negative temperature characteristic on the order of approximately −1.9 mV/° C., which is slightly less than −2 mV, while the thermal voltage VT has a positive temperature characteristic of 0.0853 mV/° C.

Accordingly, in order that the output reference voltage VREF will not exhibit a temperature dependent characteristic, the cancellation of temperature dependency of the output reference voltage VREF may be performed by a combination of a voltage exhibiting a positive temperature characteristic and a voltage exhibiting a negative temperature characteristic.

That is, the value of (R 2 /R 1 ) ln (K 1 ) is 22.3, while that of (R 2 /R 1 )VT ln (K 1 ) is 0.57V.

If the base-to-emitter voltage VBE 1 is 0.7 V,

{ VBE 1+( R 2/ R 1) VT ln ( K 1)}=1.27V

Up to now, in the reference voltage circuit for outputting the reference voltage not exhibiting this sort of temperature characteristic, an operational amplifier is used in a feedback circuit, and a resistor is introduced in a current loop of the PTAT current source circuit, so that a desired resistance ratio is required. The voltage drop across a resistor on the order of approximately 0.6 V is needed for one resistor. Thus, if it is desired to diminish the driving current of a transistor connected in a diode configuration, a large resistance value is required, thus increasing a chip size.

A reference voltage circuit, exemplified first and foremost by a bias voltage of the circuitry, arranged in a large number of LSIs, including digital LSIs, such as memory devices, to say nothing of an analog LSI, is routinely used. In particular, a reference voltage circuit, which outputs a voltage not exhibiting a temperature dependent characteristic, is generally termed “a band gap reference voltage circuit”.

The output voltage of a band gap reference voltage circuit is close to 1.205 V, which is the band gap voltage of Silicon at 0° K.

Since the CMOS process nowadays is predominantly used, realization of a circuit with part elements that can be readily manufactured by the CMOS process has been desired. In particular, it is more desirable that a standard digital CMOS process can smoothly realize a circuit. In such case, however, a high precision resistance ratio or a high resistance leads to an increase of a chip size.

Accordingly, it is an object of the present invention to provide a reference voltage circuit for outputting a reference voltage not exhibiting a temperature characteristic, which can be implemented only using transistors without adopting a high precision resistance ratio or a high resistance to simplify the circuit structure.

A CMOS reference voltage circuit in accordance with one aspect of the present invention comprises first and second diode-connected transistors(or diodes), which are grounded, and are driven respectively by two constant currents, bearing a constant current ratio, and means for amplifying a differential voltage between output voltages of the first and second diode-connected transistors(or diodes) by a predetermined constant factor and summing the resulting amplified voltage to an output voltage of the first or second diode-connected transistor(or diode), in which said means for amplification and summation includes first and second operational transconductance amplifiers (OTAs) and a current mirror circuit, in which the first OTA is fed with the differential voltage, the second OTA has a first input terminal(−) fed with an output voltage from the first or second diode-connected transistor (or diode) and a second input terminal(+) connected to an output terminal and driven with a current proportional to the output current of said first OTA, an output terminal voltage of the second OTA being an output reference voltage.

In accordance with the present invention, the transconductance gm 1 of the first OTA gm 1 is equal to the transconductance gm 2 of the second OTA (gm 1 =gm 2 ), and the current ratio of the input current to the output current in the current mirror circuit is set to 1:K 2 , where K 2 >1, to produce a desired amplification factor.

In accordance with the present invention, the current ratio of the input current to the output current in the current mirror circuit is equal (1:1) and the transconductance gm 1 of the first OTA 1 and that gm 2 of the second OTA 2 are set so that gm 1 =K 2 ×gm 2 , where K 2 >1, to obtain a desired amplification factor.

In accordance with the present invention, the current ratio of the input current to the output current in the current mirror circuit is set to 1:K 2 , where K 2 >1, and the transconductance gm 1 of the first OTA 1 and that gm 2 of the second OTA 2 are set so that gm 1 =K 3 ×gm 2 , where K 3 >1, to obtain a desired amplification factor.

A CMOS reference voltage circuit in accordance with another aspect of the present invention, comprises first and second diode-connected transistors (or diodes), which are grounded, and are driven respectively by two constant currents, bearing a constant current ratio, and means for amplifying a differential voltage between output voltages of the first and second diode-connected transistors (or diodes) by a predetermined constant factor and summing the resulting amplified voltage to an output voltage of the first or second diode-connected transistor (or diode), in which the means for amplification and summation includes (K 2 +1) differential pairs, K 2 being an integer not less than 1, the first differential pair being fed with the differential voltage, one of differential pair transistors of the second differential pair being fed with an output voltage of the first or second diode-connected transistor, the other of the differential pair transistors being diode-connected and being driven with the current proportional to the output current of one of the transistors of the first differential pair, output voltages of diode-connected transistors of the second to number K 2 differential pairs are fed to one of the differential pair transistors of the third to the number (K 2 +1) differential pairs, respectively, the other transistors of the differential pair transistors being diode-connected and driven by currents proportional to the output current of the one transistor of the first differential pair, with the first to number (K 2 +1) differential pairs being driven with the (K 2 +1) constant currents bearing a certain constant current ratio relative to one another, with the differential input voltages of the second to number (K 2 +1) differential pairs being summed together to produce a desired amplification factor.

A CMOS reference voltage circuit in accordance with another aspect of the present invention comprises first and second diode-connected transistors (or diodes), which are respectively grounded, and are driven by two constant currents, bearing a constant current ratio, and means for amplifying a differential voltage of output currents of the first and second diode-connected transistors (or diodes) by a preset factor and summing the resulting amplified voltage to an output voltage of the first or second diode-connected transistor (or diode), in which said means for amplification and summation includes (K 2 +1) differential pairs, with the first differential pair being fed with the differential voltage, one of differential pair transistors of the second differential pair being fed with an output voltage of the first or second diode-connected transistor, the other of the differential transistors being diode-connected, the differential transistors of the third to number K 2 differential pairs being diode-connected, the one diode-connected differential transistor of a given stage being driven by the constant current with the other diode-connected differential transistor of a preceding stage, the other diode-connected transistor being driven with the current proportional to the output current of the first differential pair, the first to number (K 2 +1) differential pairs being driven with (K 2 +1) constant currents bearing a certain constant current ratio to one another, with the differential input voltages of the second to number (K 2 +1) differential pairs being summed together to produce a desired amplification factor.

A CMOS reference voltage circuit in accordance with another aspect of the present invention comprises first and second diode-connected transistors (or diodes), which are grounded, and respectively driven with two constant currents, bearing a constant current ratio, and means for amplifying a differential voltage of output voltages of the first and second diode-connected transistors (or diodes) by a preset factor and summing the resulting amplified voltage to an output voltage of the first or second diode-connected transistor (or diode), in which said means for amplification and summation is made up of two differential pairs, one of the differential transistors of a second one of the differential pairs being fed with an output voltage of the first or second diode-connected transistors (or diodes), the other differential transistor being diode-connected and being driven with the current proportional to the output current of one of the transistors of the first differential pair, the first differential pair and the second differential pair being driven with two constant currents having a constant current ratio to each other, an operating input voltage range of the second differential pair being a constant number tuple of the operating input voltage range of the first differential pair to produce a desired amplification factor.

In accordance with the present invention, the first diode-connected transistor (or diode) is equal to the second diode-connected transistor (or diode), with the ratio of respective driving currents not being equal to 1.

In accordance with the present invention, the size of the first diode-connected transistor (or diode) is K 1 times the size of the second diode-connected transistor (or diode), with the driving current ratio not being equal to 1.

In accordance with the present invention, the size of the first diode-connected transistor (or diode) differs from the size of the second diode-connected transistor (or diode), with the driving current ratio being equal to 1.

In accordance with the present invention, the gate W/L ratio of each transistor of the first differential pair is K 2 times the gate W/L ratio of each transistor of the second differential pair, W and L being the gate width and the gate length of the transistor, respectively, the driving current of the second differential pair being K 3 times the driving current of the third differential pair, the output current of the first differential pair being multiplied by K 3 to drive the diode-connected transistor of the second differential pair to produce the desired amplification factor.

The present invention is constituted by a grounded diode-connected transistor, (or diode) driven at a constant current, and an operational amplifier having a voltage follower type offset, for receiving an output voltage of the diode-connected transistor (or diode).

In accordance with the present invention, the operational amplifier is driven with the constant current, each of two transistors making up an input differential pair has a gate W/L ratio of 1:K2, and the gate W/L ratio of the two transistors forming an active load operating as a load to the two transistors is K3:1, with offset values being summed together.

In accordance with the present invention, each of two transistors making up an input differential pair has a gate W/L ratio of K 2 :1, and the gate W/L ratio of the two transistors forming an active load operating as a load to the two transistors is 1:K 3 , with offset values being subtracted.

Still other objects and advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description in conjunction with the accompanying drawings wherein only the preferred embodiments of the invention are shown and described, simply by way of illustration of the best mode contemplated of carrying out this invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawing and description are to be regarded as illustrative in nature, and not as restrictive.

FIG. 1 shows a circuit structure of an embodiment of the present invention;

FIG. 2 illustrates the operation of multiplication of a reference voltage circuit embodying the present invention;

FIG. 3 illustrates the operation of multiplication of the reference voltage circuit embodying the present invention;

FIG. 4 illustrates the operation of multiplication of the reference voltage circuit embodying the present invention;

FIG. 5 shows a circuit structure of a second embodiment of the present invention;

FIG. 6 shows a circuit structure of a third embodiment of the present invention;

FIG. 7 shows a circuit structure of a fourth embodiment of the present invention;

FIG. 8 shows a circuit structure of a fifth embodiment of the present invention;

FIG. 9 shows a modification of the fifth embodiment of the present invention; and

FIG. 10 shows the structure of a reference voltage circuit employing a conventional operational amplifier.

The preferred embodiments of the present invention will now be described. If two transistors, both of which have emitters grounded and are connected in diode configuration, are driven by a current mirror circuit, and the current densities of the two transistors are made different from each other to produce different base-to-emitter voltages VBEs, a differential voltage ΔVBE of the base-to-emitter voltages of the two transistors is proportional to absolute temperature, and hence a voltage proportional to the thermal voltage VT is obtained.

On the other hand, the base-to-emitter voltage VBE of a transistor has a negative temperature characteristic on the order of approximately −2 mV/° C. to −1.9 mV/° C.

In general, in a conventional reference voltage circuit, a reference voltage circuit which outputs a constant voltage not exhibiting a temperature dependent characteristic, is realized by weight-summing the voltage VTPAT proportional to absolute temperature and the voltage VIPTAT inversely proportional to absolute temperature.

This constant voltage is of a voltage value such that VPTAT+VIPTAT≈1.2V or thereabout.

In the conventional reference voltage circuit, this weight summation of the voltages VPTAT and VIPTAT is realized by a resistor inserted on a PTAT current path of VIPTAT, and is termed “ΔV multiplier”.

In accordance with the present invention, the weight summation is not realized by a resistor, but by a differential pair.

An embodiment of the present invention is shown in FIG. 1 , showing two OTAs (operational transconductance amplifiers) 11 and 12 , in which a differential input voltage is proportional to an output current and in which a transconductance exhibits a linear characteristic. Across these OTAs, the current (K 2 ×gm 1 ΔVBE) having a predetermined constant ratio K 2 to an output current (gm 1 ΔVBE) of the first OTA 11 , which is proportional to a differential voltage VBE (=VBE 2 −VBE 1 ) of the base-to-emitter voltage VBE of two bipolar transistors Q 1 and Q 2 , is caused to flow into the second OTA 12 to produce a voltage corresponding to the differential voltage ΔVBE multiplied by a constant value, that is VPTAT (=K 2 ×gm 1 ΔVBE/gm 2 ). In the second OTA 12 , the base-to-emitter voltage VBE 2 of the transistor Q 2 is summed to VPTAT and the resulting voltage is output to produce a desired constant voltage VREF not exhibiting a temperature dependent characteristic.

In a modification of the present invention, as shown in FIGS. 5 and 6 , plural differential pairs are connected in a cascaded configuration so that differential voltages applied to the differential input terminals of the respective differential pairs will be made equal to each other and equal to the differential voltage ΔV. From the differential pair of the last stage, a voltage equal to an integer number multiple of the differential voltage ΔV is obtained as a voltage proportional to absolute temperature.

Alternatively, an embodiment of the invention described by FIG. 7 has a transfer curve (transfer characteristic) of the differential pairs possibly normalized by a square root of a ratio of the driving current I 0 to a transconductance parameter βof the differential transistor, or √{square root over ( )}(I 0 /β), and thus may be constant.

That is, if a normalized current equal to the normalized current flowing through one transistors of the first differential pairs M 1 and M 2 by the voltage applied to the first differential pairs M 1 and M 2 is caused to flow through one transistors of the second differential pair M 3 and M 4 , the voltage across input terminals of the second differential pair is multiplied with the ratio of the standardized voltages of the two differential pairs, or divided by the ratio of the standardized voltages of the two differential pairs if the ratio is less than 1.

Therefore, the summation may be made as the voltage applied to the other input terminal of the second differential pair is multiplied with the voltage applied across the input terminals of the first differential pair.

Alternatively, as shown in FIG. 8 , an offset voltage VOS, generated in a voltage follower circuit, made up of an unbalanced differential pair, including unbalanced input differential pairs MM 1 and MM 2 , active load devices MM 3 and MM 4 , an output stage MM 5 and phase compensation circuits RC and CC, is obtained as a voltage VPTAT which is proportional to absolute temperature. In the operational amplifier which is driven with a constant current, the gate W/L ratio (gate width/gate length ratio) of the two transistors MM 1 and MM 2 constituting the input differential pair is 1:K 2 , and the gate W/L ratio of two transistors MM 3 and MM 4 (of a current mirror circuit configuration) forming an active load operating respectively as a load for two transistors MM 1 and MM 2 , is K 3 :1, and the offset is added to an input voltage to the voltage follower circuit to produce an output reference voltage VREF. Alternatively, the gate W/L ratio of the two transistors forming the input differential pair is K 2 :1, while the gate W/L ratio of the two transistors forming an active load operating as a load for the two transistors is 1:K 3 , and an offset is subtracted from an input voltage to produce an output reference voltage VREF.

Such a configuration may also be used which includes a source-grounded MOS transistor MM 10 , having its drain and gate connected to one end and the other end of the resistor R 1 , respectively, a source-grounded MOS transistor MM 11 having its gate connected to the drain of the MOS transistor MM 10 and a current mirror circuit, having its input end connected to a drain of the MOS transistor MM 11 , and adapted for supplying the constant current to the MOS transistor MM 10 , a common source of the first and second MOS transistors MM 1 and MM 2 of the differential pair, a MOS transistor MM 5 of a source follower configuration and to the collector of the bipolar transistor Q 1 .

Referring to the drawings, certain preferred embodiments of the present invention are explained in detail. FIG. 1 shows a circuit configuration of an embodiment of the present invention, as applied to a CMOS reference voltage circuit. As shown in FIG. 1 , this circuit includes first and second emitter-grounded transistors Q 1 and Q 2 , each of which has a base connected to a collector and is provided with a constant current at the collector, first and second operational transconductance amplifiers (abbreviate to OTAs) 11 and 12 , each of which outputs current corresponding to the voltage difference between the voltage at a positive phase (non-inverting) input terminal (+) and that at a reverse phase (inverting) input terminal (−), and a current mirror circuit 13 which has a ratio of the current input to the input end to the current output from the output end equal to a predetermined value K 2 . The reverse phase input terminal (−) and the positive phase input terminal (+) of the first OTA 11 are connected to the collectors(more precisely the connection nodes of the collectors and the bases) of the first and second transistors Q 1 and Q 2 , respectively. The OTA 11 has its output terminal connected to an input end of the current mirror circuit 13 . An output end of the current mirror circuit 13 and the collector of the second transistor Q 2 are connected to the positive phase input terminal (+) and the reverse phase input terminal (−) of the second OTA 12 , respectively, while the output terminal of the second OTA 12 is connected to the positive phase input terminal (+) of the second OTA 12 . The reference voltage VREF is output at an output terminal of the second OTA 12 .

It is assumed that, in the embodiment shown in FIG. 1 , the emitter area of the transistor Q 1 is K 1 times the emitter area of the transistor Q 2 . The collectors of the transistors Q 1 and Q 2 are connected to drains of the P-channel MOS transistors M 200 and M 300 , that is output terminals of a current mirror circuit (made up of P-channel MOS transistors M 100 , M 200 and M 300 ) which receives a constant current I 0 from a constant current source 14 at its input terminal, and the current I 0 flows through collectors of the transistors Q 1 and Q 2 .

If the DC current amplification factor of the transistors is sufficiently close to unity and the base current is neglected, from the above equation (1), the base-to-emitter voltages VBE 1 and VBE 2 of the transistors Q 1 and Q 2 are expressed as follows:

The differential voltage ΔVBE between the base-to-emitter voltages VBE 1 and VBE 2 is given by:

That is, if the emitter grounded two transistors Q 1 and Q 2 , both connected in diode configuration, are driven by the current mirror circuit, the densities of currents which flow respectively through the two transistors are rendered different as are the base-to-emitter voltages, and the differential voltage ΔVBE between the base-to-emitter voltages of the two transistors Q 1 and Q 2 is taken, the differential voltage ΔVBE is proportional to absolute temperature, thus producing a voltage proportional to the thermal voltage VT.

Also, as may be seen from the equation (12), in order to set current densities of two transistors different to produce a voltage differential between the base-to-emitter voltages of the two transistors Q 1 and Q 2 , any of the following methods may be effectively used:

the emitter areas of the two transistors Q 1 and Q 2 are rendered different, as the driving currents supplied to the collectors of the two transistors Q 1 and Q 2 are kept equal;

the emitter areas of the two transistors Q 1 and Q 2 are rendered equal to each other and the driving currents supplied to the collectors of the two transistors Q 1 and Q 2 are rendered different; or

both the driving currents and emitter areas of the two transistors Q 1 and Q 2 are rendered different.

Next, a multiplication-summation circuit, employing two OTASs, is described.

The first OTA 11 has a transconductance gm 1 and receives the differential voltage VBE to draw the current gm 1 ΔVBE. The second OTA 2 has a transconductance gm 2 and has a reverse phase input terminal (−) for receiving the base-to-emitter voltage VBE 2 of one of the transistors, while having a positive phase input terminal (+) connected in common with its output terminal and driven with a current K 2 ×gm 1 ΔVBE through the current mirror circuit 13 .

In order for the two OTAs to have the function of the voltage multiplication circuit, the OTAs need to be equal in transconductance (gm 1 =gm 2 ), as shown in FIG. 2 . If the current ratio (that is, input current value: mirror current value) of the current mirror circuit 13 is set to 1:K 2 (K 2 >1), the voltage gain is K 2 and, since the output current of the second OTA 12 is

K2×gm1ΔVBE  (12),

the input differential voltage of the second OTA 12 is the output current divided by transconductance gm 2 , so that we have

Since in the second OTA, the output terminal for outputting the reference voltage VREF, is connected to the positive phase input terminal (+), the voltage of the reverse phase input terminal (−) is VBE 2 and ΔV=(VREF−VBE 2 ), the reference voltage VREF is given by:

In the equation (14), the base-to-emitter voltage VBE 2 of the transistor Q 2 , driven with the constant current I 0 , has a negative temperature characteristic on the order of approximately −2 mV/° C., while the thermal voltage VT has a positive temperature characteristic on the order of approximately 0.0853 mV/° C.

Thus, in order for the output reference voltage VREF not to exhibit a temperature dependent characteristic, the temperature dependent characteristic might be cancelled with a voltage exhibiting a positive temperature characteristic and a voltage exhibiting a negative temperature characteristic.

That is, the value of K 2 ln (K 1 ) is 23.45, with the value of K 2 ·VT ln (K 1 ) being 0.61V. If VBE 2 is 0.7V,

{ VBE 2 +K 2 ·VT ln ( K 1)}=1.31 V.

Alternatively, in order for these two OTA to have the function of a voltage multiplication circuit, as shown in FIG. 3 , it is also sufficient if the two conductance values differ from each other such that

gm 1 =K 2 gm 2( K 2>1)

and, when the current ratio of the current mirror circuit is set to 1:1, the voltage gain is K 2 , such that a differential voltage K 2 ΔV is obtained as an output voltage:

K ⁢ ⁢ 2 ⁢ Δ ⁢ ⁢ V = ⁢ gm ⁢ ⁢ 1 ⁢ Δ ⁢ ⁢ VBE / gm ⁢ ⁢ 2 = ⁢ K ⁢ ⁢ 2 ⁢ Δ ⁢ ⁢ VBE ( 15 )

Thus we have

In the equation (16), the base-to-emitter voltage VBE 2 of the transistor Q 2 , driven with the constant current I 0 , has a negative temperature characteristic on the order of approximately −2 mV/° C., while the thermal voltage VT has a positive temperature characteristic on the order of approximately 0.0853 mV/° C. Thus, in order for the output reference voltage VREF not to exhibit a temperature dependent characteristic, the temperature dependent characteristic might be cancelled with a voltage a exhibiting positive temperature characteristic and a voltage exhibiting a negative temperature characteristic.

That is, the value of K 2 ln (K 1 ) is 23.45, with the value of K 2 ·VT ln (K 1 ) being 0.61V. If VBE 2 is 0.7V, we have

{ VBE 2+ K 2· VT ln ( K 1)}=1.31 V.

Alternatively, in order for the two OTA to have the function of a voltage multiplication circuit, as shown in FIG. 4 , it is also sufficient if the two conductance values differ from each other, as shown in FIG. 4 , such that

gm 1 =K 3 gm 2( K 3>1)

and, when the current ratio of the current mirror circuit is set to 1:K 2 , the voltage gain is K 4 , such that a differential voltage K 4 ΔV

K ⁢ ⁢ 4 ⁢ Δ ⁢ ⁢ V = ⁢ K ⁢ ⁢ 2 ⁢ gm ⁢ ⁢ 1 ⁢ Δ ⁢ ⁢ VBE / gm ⁢ ⁢ 2 = ⁢ K ⁢ ⁢ 2 · K ⁢ ⁢ 3 ⁢ Δ ⁢ ⁢ VBE ( 17 )

is obtained as the output voltage.

Thus, we have

In the equation (18), the base-to-emitter voltage VBE 2 of the transistor Q 2 , driven with the constant current I 0 , has a negative temperature characteristic on the order of approximately −2 mV/° C., while the thermal voltage VT has a positive temperature characteristic on the order of approximately 0.0853 mV/° C. Thus, in order for the output reference voltage VREF not to exhibit a temperature dependent characteristic, the temperature dependent characteristic might be canceled by a voltage exhibiting a positive temperature characteristic and a voltage exhibiting a negative temperature characteristic.

That is, the value of K 2 ·K 3 ln (K 1 ) is 23.45, with the value of K 2 ·K 3 ·VT ln (K 1 ) being 0.61V. If VBE 2 is 0.7V, we have

{ VBE 2 +K 2 ·K 3 ·VT ln ( K 1)}=1.31 V.

The second embodiment of the present invention will now be described. FIG. 5 shows a circuit configuration of a second embodiment of the CMOS reference voltage circuit according to the present invention. Referring to FIG. 5 , this embodiment includes first and second diode-connected common emitter transistors Q 1 and Q 2 , driven by two constant currents having a constant current ratio. The present embodiment also includes (K 2 +1) differential pairs as means for amplifying the differential voltage of the output voltages of the transistors Q 1 and Q 2 by a preset factor and summing the so amplified differential voltage to the output voltage (collector voltage) of the transistors Q 1 and Q 2 .

The first differential pair M 1 and M 2 receives as a differential input a differential voltage of output voltages of the transistors Q 1 and Q 2 .

An output voltage (collector voltage) of the transistor Q 2 is applied to the gate of one transistors M 3 of the second differential pair M 3 and M 4 , with the other transistor M 4 of the second differential pair being connected in a diode configuration. The second differential pair is driven with the current proportional to the output current of the one transistor M 2 of the first differential pair.

In the third to number (K 2 +1) differential pairs, output voltages of the other diode-connected transistors M 4 to M(2K 2 ) of the preceding second to number K 2 differential pairs are fed to the gates of the one transistors of the third to number (K 2 +1) differential pairs. These other transistors of the differential pairs are connected in diode configuration and are driven with the current proportional to the output current of the one transistor M 2 of the first differential pair.

The first to number (K 2 +1) differential pairs are driven with constant (K 2 +1) currents respectively.

The output voltage of the diode-connected transistor M(2K 2 +2), of the transistors of the number (K 2 +1) differential pair, is output as the reference voltage VREF. The differential input voltages of the second to number (K 2 +1) differential pairs are summed together to attain a desired amplification factor.

Referring to FIG. 5 , (K 2 +4) pieces of P-channel MOS transistors MP 1 and MP 2 to MP(K 2 +4), having sources connected in common to a power supply VDD and having gates connected in common, form a first mirror circuit having (K 2 +3) outputs. The P-channel MOS transistor MP 1 , the drain of which is connected to its gate has its drain connected to a constant current source 15 . A constant current I 0 is the input current to the first current mirror circuit. From the drains of the P-channel MOS transistors MP 2 and MP 3 , the constant current is fed to the collectors of the first and second transistors Q 1 and Q 2 , whereas, from the drains of the P-channel MOS transistors MP 4 to MP(K 2 +4), the constant current is supplied to the sources of the first to number (K 2 +1) differential pairs. An N-channel MOS transistors MN 01 , having a source grounded, a drain connected to its gate and having the drain connected to the transistor M 2 , and N-channel MOS transistors MN 02 , MN 03 , . . . and MN 0 (K 2 +1) having sources grounded and having gates connected in common to the gate of the transistor MN 01 , make up a second current mirror circuit.

The gates of the transistors M 1 and M 2 , forming a first differential pair, are supplied with the differential voltage ΔVBE between the base-to-emitter voltages VBE 1 and VBE 2 of the first and second diode-connected common emitter transistors Q 1 and Q 2 . The drain of the transistor M 1 is grounded, while the drain of the transistor M 2 is connected to the drain of the N-channel MOS transistor MN 01 which forms an input end of the second current mirror circuit.

Regarding transistors M 3 and M 4 , which forms the second differential pair, the gate of the transistor M 3 is connected to the collector of the transistor Q 2 , and hence fed with the base-to-emitter voltage VBE 2 of the transistor Q 2 . The gate and the drain of the other transistor M 4 are connected in common (in a diode configuration) and connected to the drain of the N-channel MOS transistor MN 02 , while the transistor M 4 is driven with a current proportional to the current flowing through the other transistor M 2 forming the first differential pair. The input differential voltage, applied to the gates of the transistors M 3 and M 4 of the second differential pair, is equal to the input differential voltage applied to the gates of the transistors M 1 and M 2 of the first differential pair, and is equal to ΔVBE. The gate voltage of the MOS transistor M 4 is the gate voltage of the MOS transistor M 3 (the base-to-emitter voltage VBE 2 of the transistor Q 2 ) summed with ΔVBE, this voltage (VBE 2 +ΔVBE) being also fed to the gate of the one transistor M 5 of the third differential pair. The other transistor M 6 of the third differential pair is connected in a diode configuration and is connected to the drain of the output transistor MN 03 of the second current mirror circuit. The differential voltage, fed to the gates of the transistors M 5 and M 6 , is equal to the input differential voltage, applied to the gates of the transistors M 1 and M 2 of the first differential pair, and is equal to ΔVBE. The gate voltage of the transistor M 6 is the gate voltage of the transistor M 5 (VBE 2 +ΔVBE) summed with ΔVBE (VBE 2 +2ΔVBE), this voltage being input to the gate of one transistor of a fourth differential pair, not shown. The same holds for the third to number (K 2 +1) differential pairs. In each of the third to number (K 2 +1) differential pair, the differential input voltage is equal and the output voltage is higher by ΔVBE than the output voltage of the differential pair of the previous stage. The output voltage of the diode-connected other transistor of the number n stage differential pair is

VBE 2+( n −1)×Δ VBE.

The reference voltage VREF, which is an output voltage of the other diode-connected transistor M (2K 2 +2) of the number (K 2 +1) differential pair, is given by:

VBE 2 +K 2 ×ΔVBE.

Thus,

In the equation (19), the base-to-emitter voltage VBE 2 of the transistor Q 2 , driven with the constant current I 0 , has a negative temperature characteristic on the order of approximately −2 mV/° C., while the thermal voltage VT has a positive temperature characteristic on the order of approximately 0.0853 mV/° C.

Thus, in order for the output reference voltage VREF not to exhibit a temperature characteristic, it is sufficient if a voltage exhibiting a positive temperature characteristic and a voltage exhibiting a negative temperature characteristic cancels the temperature characteristic.

That is, the value of K 2 ln ( K 1 ) is 23.45, with the value of K 2 ·VT ln (K 1 ) being 0.61V.

If VBE 2 is 0.7V,

{ VBE 2 +K 2 ·VT ln ( K 1)}=1.31 V.

A third embodiment of the present invention is explained. FIG. 6 is a circuit diagram showing a third embodiment of the CMOS reference voltage circuit according to the present invention. Referring to FIG. 6 , the present embodiment includes first and second diode-connected transistors Q 1 and Q 2 , respectively grounded and driven by two constant currents having a constant current ratio to each other. As means for amplifying the differential voltage of the transistors Q 1 and Q 2 by a certain factor and summing the resulting amplified differential voltage to an output voltage of the first or second diode-connected transistor Q 1 or Q 2 , (K 2 +1) differential pairs are arranged.

The first differential pair M 1 and M 2 is fed with a differential voltage of the output voltages of the transistors Q 1 and Q 2 , while the second differential pair M 3 and M 4 is configured so that an output voltage of the transistor Q 2 is applied to the one transistor M 3 of the differential pair, with the other transistor M 4 thereof being connected in a diode configuration.

The differential transistors M 5 and M 6 to M(2K 2 −1) and M(2K 2 ) of the third to number K 2 differential pairs are all connected in a diode configuration, in such a manner that a diode-connected transistor of the differential pair of the front stage and the diode-connected transistor of the differential pair of the back side stage are driven at a constant current with a constant current ratio K 2 , while the number M(2K+1) and M(2K+2) transistors of the number (K 2 +1) differential pair are all connected in a diode configuration. The diode connected number M(2K 2 +1) transistor is driven at a constant current along with the diode-connected transistor M (2K 2 ) of the front stage, while the diode-connected other transistor M(2K 2 +2) is driven with the current proportional to one output current of the first differential pair.

The number 1 to number (K 2 +1) differential pairs is driven at a constant current (K 2 +1) with a constant current ratio. The desired amplification factor is achieved by summing all of the differential input voltages of the second to number (K 2 +1) differential pairs.

Referring to FIG. 6 , (K 2 +4) common gate P-channel MOS transistors MP 1 , MP 2 to MP(K 2 +4), having respective sources connected to a power supply VDD in common, constitute a first current mirror circuit having (K 2 +3) outputs. The P-channel MOS transistor MP 1 , having its drain connected to its gate has the drain connected to a constant current source 16 with a constant current I 0 being an input current to the first current mirror circuit. The drains of the P-channel MOS transistors MP 2 and MP 3 output a constant current to the collectors of the first and second transistors Q 1 and Q 2 , while the drains of the P-channel MOS transistors MP 4 to MP(K 2 +4) output a constant current to the common source of the number 1 to number K 2 +1 differential pairs. The transistor MN 01 , having its source grounded, having its drain connected to its gate, having the drain connected to the constant current source IO and fed with the sink current, and the N-channel MOS transistors MN 04 , MN 05 and MN 0 (K 2 +1), having the sources grounded and having the gates to the gate of the transistor MN 01 in common, constitute a second current mirror circuit. The transistor MN 02 , having its source grounded, having its drain connected to its gate, and having the drain connected to the drain of the transistor M 2 , and an N-channel MOS transistor MN 03 , having its source grounded and having its gate connected to the gate of the transistor MN 02 in common, constitute a third current mirror circuit.

In FIG. 6 , the first differential pair, made up of P-channel MOS transistors M 1 and M 2 , is fed with a differential input voltage corresponding to a differential voltage ΔVBE between the base-to-emitter voltage VBE 1 of the transistor Q 1 and the base-to-emitter voltage VBE 2 of the transistor Q 2 .

Also, in the second differential pair, made up of the transistors M 3 and M 4 , the transistor M 3 has its gate fed with the base-to-emitter voltage VBE 2 of the transistor Q 2 , while the transistor M 4 has its gate connected to its drain in a diode configuration and also connected to a gate of the transistor M 5 which constitutes a third differential pair and has its gate connected to its drain in a diode configuration. The transistor M 4 and M 5 are driven with a constant current.

The third to number K 2 differential pairs are configured in similar manner. The diode-connected transistor M(2K 2 +2) of the number K 2 +1 last-stage differential pair has its drain connected to the drain of the output transistor MN 03 of the third current mirror circuit, and is driven by the current proportional to that flowing in the transistor M 2 of the first differential pair.

The first differential pair (made up of transistors M 1 and M 2 ) is driven by the transistor MP 4 with a current Io proportional to the constant current I 0 . If a differential voltage ΔVBE is differentially input to the first differential pair, and the drain currents flowing through the transistors M 1 and M 2 of the first differential pair are I 1 and I 2 , we have

I 1 +I 2 =Io.

The common source of the transistors M(2K 2 +1) and M (2K 2 +2) of the last-stage number (K 2 +1) differential pair is fed with the current Io from the transistor MP(K 2 +4), the drain of the transistor M(2K 2 +2) is driven by the transistor MN 03 with the current I 2 , with the current Io−I 2 =I 1 flowing through the drain of the transistor M(2K 2 +1). The differential input voltage of the number (K 2 +1) is ΔVBE, with the gate voltage of the transistor M(2K 2 +1) being lower by ΔVBE than the gate voltage of the transistor M(2K 2 +2).

The drains of the transistor M(2K 2 +1) of the number (K 2 +1) differential pair and the drain of the transistor M(2K 2 ) of the number (K 2 ) differential pair are connected in common to the drain of the output transistor MN 0 (K 2 +3) of the second current mirror circuit. Since these transistors are driven with the current Io proportional to the constant current I 0 , the current flowing through the drain of the transistor MP(2K 2 ) is Io−I 1 =I 2 , while the current flowing through the drain of the transistor MP(2K 2 −1) is Io−I 2 =I 1 . As in the case of the first differential pair, the differential input voltage is ΔVBE, with the gate voltage of the transistor MP(2K 2 −1) being lower by ΔVBE than the gate voltage of the transistor M(2K 2 ). In this manner, the gate voltages of the diode-connected transistors are lowered stepwise by ΔVBE up to the second differential pair M 3 and M 4 .

Since the voltage input to the gate of the transistor M 3 of the second differential pair is the base-to-emitter voltage VBE 2 of the transistor Q 2 , the drain (gate) voltage of the transistor M 4 of the second differential pair is VBE 2 +ΔVBE, so that the output voltage VREF of the transistor M(2K 2 +2) of the number (K 2 +1) stage differential pair is

In the equation (20), the base-to-emitter voltage VBE 2 of the transistor Q 2 , driven with the constant current Io, has a negative temperature characteristic on the order of approximately −2 mV/° C., while the thermal voltage VT has a positive temperature characteristic of 0.0853 mV/° C.

Therefore, in order that the output reference voltage VREF will not exhibit a temperature characteristic, it is sufficient if a voltage exhibiting a positive temperature characteristic and a voltage exhibiting a negative temperature characteristic ekes out the temperature characteristic. That is, the value of K 21 ln (K 1 ) is 23.45, while that of K 2 ·VT ln (K 1 ) is 0.57V.

If VBE 2 is 0.7 V,

{ VBE 2 +K 2 ·VT ln ( K 1)}=1.31 V.

A fourth embodiment of the present invention is now explained. FIG. 7 shows a circuit structure of a fourth embodiment of a CMOS reference current circuit of the present invention. In the present embodiment, a multiplication summation circuit employing two differential pairs is described.

The embodiment shown in FIG. 7 includes first and second diode-connected transistors Q 1 and Q 2 , both of which have emitters, grounded and are driven with two constant currents bearing a constant current ratio to each other. The present embodiment also includes means, made up of two differential pairs, for amplifying the differential voltage of the output voltages of the two transistors Q 1 and Q 2 by a preset constant factor and summing the result to an output voltage from the transistor Q 2 .

The differential pair mad e up of P-channel MOS transistors M 1 and M 2 receives a differential voltage of output voltages of the transistors Q 1 and Q 2 . An output voltage of the transistor Q 2 is applied to the gate of the P-channel MOS transistor M 3 making up a second differential pair along with the diode-connected P-channel MOS transistor M 4 . The drain of the transistor M 4 is driven with a current proportional to an output current of the first differential pair, that is the drain current of the transistor M 2 (K 3 tuple current). The common source of the first and second differential pairs is driven with two constant currents, having a certain current ratio to each other. A desired amplification factor is realized by setting the operating input voltage range of the second differential pair so as to be a preset constant number tuple of that of the first differential pair. In FIG. 7 , P-channel MOS transistors MP 5 to MP 9 , which have their sources connected in common to a power supply VDD and have their gates connected in common, constitute a first current mirror circuit. The P-channel MOS transistor MP 9 , having its drain connected to its gate has the drain connected to a constant current source 17 , with the constant current I 0 being an input current to the current mirror circuit. From the drains of the P-channel MOS transistors MP 5 and MP 7 , constant currents are fed to the collectors of the first and second transistors Q 1 and Q 2 , and from the drains of the P-channel MOS transistors MP 6 and MP 8 , constant currents are fed to the commonly connected sources of the first and second differential pairs respectively. An N-channel MOS transistor MN 10 , having a source grounded, having a drain and a gate connected to each other and having the drain connected to the drain of the transistor M 2 , and an N-channel MOS transistor MN 11 , having a source grounded and having a gate connected to the gate of the transistor MN 10 , constitute a second current mirror circuit.

It is assumed that a transconductance parameter β is equal for both the transistors M 1 and M 2 , forming the first differential pair, and that the two transistors are driven at the constant current I 0 , where the transconductance parameter β is given by:

β=μ( Cox/ 2)( W/L )

where μ is the effective mobility of the carrier, Cox is the capacity of a gate oxide film per unit area and W and L are a gate width and a gate length, respectively. The gate W/L ratio of the transistors M 1 and M 2 , forming the first differential pair, where W and L denote the gate width and the gate length, respectively, is set so as to be K 2 times the gate W/L ratio of the transistors M 3 and M 4 forming the second differential pair.

The respective drain currents ID 1 and ID 2 of the transistors M 1 and M 2 are given by:

I D1 =β( V GS1 −V TH ) 2   (21)

I D2 =β( V GS2 −V TH ) 2   (22),

respectively. In the above equations, V GS1 and V GS2 denote the gate-to-source voltages of the transistors M 1 and M 2 respectively and V TH is a threshold voltage.

The sources of the transistors M 1 and M 2 are connected to the drain of the P-channel MOS transistor MP 6 , forming an output of the first current mirror circuit. From the conditions for the driving current,

I D1 +I D2 =I 0   (23)

By solving equation (21) to (23), ID 1 and I D2 are given by the following equation (24) and (25):

In the above equations, ΔV=V GS1 −V GS2 .

If the equation (24) and (25) are normalized with the current I 0 , the following equation (26) and (27) are obtained:

In the second differential pair, made up by the transistors M 3 and M 4 , the above equations are given by:

The above normalization enables the application not only to the first differential pair, made up of the transistors M 1 and M 2 , but also to the second differential pair, made up of the transistors M 3 and M 4 .

It is assumed that, with the first differential pair, comprised of the transistors M 1 and M 2 ,

x 1 =ΔV 1 /√{square root over (I 0 /( K 2 β))}

and, with the second differential pair, made up of the transistors M 3 and M 4 ,

x 2 =ΔV 2 /√{square root over ( K 3 I 0 /β)}

Since the drain current ID 2 of the transistor M 2 is K-tupled to flow through the transistor M 4 , with the current ratio in the second current mirror circuit being K 3 , the normalized input voltages are equal to each other, so that x 1 =x 2 . Consequently,

Δ ⁢ ⁢ V 2 = Δ ⁢ ⁢ V 1 ⁢ K 3 ⁢ I 0 β I 0 ( K 2 ⁢ β ) = K 2 ⁢ K 3 ⁢ Δ ⁢ ⁢ V 1 ( 30 )

with the multiplication coefficient being

√{square root over (K 2 K 3 )}

Since

ΔV 1 =ΔV=ΔVBE=VT ln ( K 1)  (31)

V REF =V BE2 +ΔV 2 =V BE2 +√{square root over ( K 2 K 3 )} V T ln ( K 1 )  (32)

The thermal voltage VT has a positive temperature characteristic of 0.0853 mV/° C. If, assuming that the transistor Q 2 is being driven with the constant current I 0 , exhibiting a low temperature characteristic, the temperature characteristic of the base-to-emitter voltage VBE of the transistor Q 2 is −2.0 mV/° C., and if it is desired for the output reference voltage VREF not to display a temperature characteristic, it is sufficient if the temperature characteristic are cancelled out by a voltage exhibiting a positive temperature characteristic and a voltage exhibiting a negative temperature characteristic.

That is, the value of Sqrt(K 2 ×K 3 )×in(K 1 ) is 23.447, where the function Sqrt( ) denotes √{square root over ( )}( ).

The value of Sqrt(K 2 ×K 3 )×VT ln (K 1 ) is 0.60 V at ambient temperature.

If VBE 2 is 0.7V,

{ VBE 2 +Sqrt ( K 2 K 3)× VT ln ( K 1)}=1.3 V.

Specifically,

K 1 =10, K 2 =8, and K 3 =13.

A fifth embodiment of the present invention is now explained. FIG. 8 shows a circuit structure of a fifth embodiment of the present invention.

In FIG. 8 , transistors MM 1 to MM 7 constitute a voltage follower type operational amplifier with a resistance for compensation RC and a capacity for compensation CC. The W/L ratio of input differential transistors M 1 and M 2 is set to 1:K 2 , and the W/L ratio of active load transistors M 3 , and M 4 , operating as loads, is set to K 3 :1, so that input offset is produced. The transistors M 1 and M 2 , having sources connected in common to a drain of the constant current source transistor MM 6 , form a differential pair. The transistor MM 3 , connected to the drain of transistor MM 1 , and having its source grounded, and the transistor MM 4 , having its drain connected to the drain of the transistor MM 2 , having its source grounded and having its gate connected to the gate of the transistor MM 3 , form a current mirror circuit operating as a load for the differential pair. The drain of the transistor MM 2 , forming an output of the differential pair, is connected to the gate of the transistor MM 5 , the drain of which is connected to a drain of the constant current source transistor MM 7 . An output voltage VREF is taken at a drain of the transistor MM 5 , operating as an output terminal. The output terminal is connected to the gate of the transistor MM 2 that operates as an inverting input terminal of the differential pair. A resistor RC for phase compensation and a capacity CC are connected across the drain and the gate of the transistor MM 5 . A base-to-emitter voltage VBE of the transistor Q 1 is input to a non-inverting input terminal of the differential pair.

Since a correct resistance value is not required of the resistor RC for phase compensation, the resistor is usually replaced by a P-channel MOS transistor and an N-channel MOS transistor.

The drain currents ID 1 and ID 2 of the respective transistors MM 1 and MM 2 are given by:

I D1 =β( V GS1 −V TH ) 2   (33)

I D2 =K3β( V GS2 −V TH ) 2   (34)

The following relationship holds:

I D1 +I D2 =I 0   (35)

Also, we can postulate:

V OS =V GS1 −V GS2   (36)

Moreover, from the conditions of the active load transistors MM 3 and MM 4 , we have

K 3 I D1 =I D2   (37)

Solving the equations (35) and (37),

I D1 =I 0 K 3/( K 3+1)  (38)

I D2 =I 0 /( K 3+1)  (39).

Thus, solving the above equation, we obtain:

Since the respective terms containing Kj are constants not dependent on the temperature, the temperature characteristic of the term of Sqrt(I 0 /β) are at issue. Since mobility μ exhibits temperature dependent characteristic in the case of the MOS transistor, the temperature dependency of the transconductance parameter β may be given by the following equation:

where β 0 is the value of β 0 at an ambient temperature (300 K). Of the temperature characteristic of the term Sqrt(I 0 /β), the temperature characteristic of the term β have become apparent. Next, the temperature characteristic of the constant current I 0 must be defined.

The generally used MOS reference current circuit may be implemented by self-biasing non-linear current mirror circuits, such as Nagata current mirror circuit, Widlar current mirror circuit, or an reverse Widlar current mirror circuit, as shown in FIG. 8 .

FIG. 8 shows a MOS reference current circuit, which is made up of a self-biased Nagata current mirror circuit.

A circuit comprised of a transistor MM 10 , having a source grounded, a drain connected to one end of a resistor R 1 and having a gate connected to the opposite end of the resistor R 1 , a transistor MM 11 , having a source grounded and having a gate connected to the drain of the transistor MM 10 , and the resistor R 1 , makes up a Nagata current mirror circuit. Here, with the transistors MM 13 and MM 12 forming a current source, the transistors MM 10 and MM 11 and the resistor R 1 form a self-biased Nagata current mirror circuit.

Here, the transistor MM 10 is assumed to be a unit transistor, and the ratio of the gate width W to gate length L, or (W/L), of the transistor MM 11 , is assumed to be K 1 times that of the unit transistor, where K 1 >1.

In the MOS Nagata current mirror circuit, shown in FIG. 8 , the device is assumed to exhibit satisfactory matching, the channel length modulation and the substrate effect are neglected, and the relationship between the drain current and the gate-to-source voltage of the MOS transistor is assumed to follow the square rule. Then, the drain current ID 1 of the MOS transistor MM 10 is given by:

I D1 =β( V GS10 −V TH ) 2   (42).

The drain current ID 2 of the MOS transistor MM 11 is given by:

I D2 =K 1β( V GS11 −V TH ) 2   (43)

There is also the following relationship:

V GS10 =V GS11 +R 1 I D10   (44).

Solving the equation (44) from the equation (42), the relationship between the input and output currents of the MOS Nagata current mirror circuit is given by:

The MOS Nagata current mirror circuit features a region where the output current (mirror current) is monotonously increased against the input current (reference current), a peak point and a region where the output current (mirror current) is monotonously decreased against the input current (reference current).

On differentiating ID 11 with respect to ID 10 , the ID 11 reaches a peak point at

ID 11 =K 1 ×ID 10/4 for ID 10=1/(4 R 1 2 β).

Thus, if K 1 =4,

ID11=ID10.

It is noted that transistors MM 11 and MM 10 make up a current mirror circuit, while the transistors MM 13 and MM 12 drive MM 10 and MM 11 , respectively. Thus, the transistors MM 11 and MM 10 make up a MOS self-biased Nagata reference current circuit, with

I D10 =I D11   (46)

Thus,

Δ V GS =V GS10 −V GS11 =R 1 I D10   (47)

Solving the equation (39) from the equation (37),

where K 1 is a constant not having a temperature characteristic. Since mobility μ exhibits a temperature characteristic in the case of the MOS transistor, the temperature dependency of the transconductance parameter β may be represented by the following equation:

β 0 is the value of β 0 at an ambient temperature (300K). Therefore,

The temperature coefficient of 1/β is 5000 ppm/° C. at ambient temperature. This value is approximately 1.5 times 3333 ppm/° C., which is the value of the temperature coefficient of the thermal voltage VT of the bipolar transistor.

Also, the transistor MM 12 forms a current mirror circuit with the transistor MM 13 , so that

I D12 =I D13   (51).

That is, the output current I 0 of the CMOS reference voltage circuit may be found by:

where K 1 is a constant not having a temperature characteristic. The temperature characteristic of 1/β is approximately proportional to temperature, as mentioned above, and is 5000 ppm/° C. at ambient temperature. This value is approximately 1.5 times 3333 ppm/° C., which is the value of the temperature characteristic of the thermal voltage VT of the bipolar transistor.

Thus, it may be seen that, if a temperature coefficient of the resistor R 1 is less than or equal to 5000 ppm/° C. and linear as regards the temperature, the drain current ID 10 exhibits a positive temperature coefficient, with the output current I 0 of the reference current circuit, output by the current mirror circuit, being proportional to temperature, so that the circuit operates as a PTAT current source circuit.

Although a startup circuit is needed for starting-up the self-bias circuit, this is omitted for simplicity in the previous explanation on the operation. For a simplified startup circuit, references may be made to the publication such as JP PATENT KOKAI JP-A-8-314561(Patent 2800720), by the same inventor as the present application.

The output current of the CMOS reference current circuit is as shown in the equation (52), while its temperature characteristic has now become apparent. Consequently, by substituting the equation (52) into the equation (40), we obtain:

V os = 1 R 1 ⁢ β ⁢ ( 1 - 1 K 1 ) ⁢ K 3 K 3 + 1 ⁢ ( 1 - 1 K 2 ⁢ K 3 ) = 1 R 1 ⁢ β 0 ⁢ ( T T 0 ) 3 2 ⁢ ( 1 - 1 K 1 ) ⁢ K 3 K 3 + 1 ⁢ ( 1 - 1 K 2 ⁢ K 3 ) ( 53 )

where the respective terms containing Kj are constants not exhibiting a temperature characteristic and an offset voltage VOS is determined by the resistor R 1 determining the current value of the CMOS reference voltage circuit, the temperature characteristic of 1/β which is 5000 ppm/° C. at ambient temperature. If the temperature characteristic of the resistor R 1 is sufficiently smaller than 5000 ppm/° C., the offset voltage exhibits a temperature characteristic of 5000 ppm/° C. at ambient temperature. This value is approximately 1.5 times 3333 ppm/° C., which is the value of the temperature characteristic of the thermal voltage VT of the bipolar transistor. Consequently, a reference voltage lower than the output voltage of the reference voltage circuit shown in FIG. 7 is obtained as now explained.

In FIG. 8 , the output voltage VREF of the reference voltage circuit is given by:

VREF=VBE 1 +VOS   (54).

The transistor Q 1 is driven with a constant current having a temperature characteristic of approximately 5000 ppm° C.

Therefore, if it is assumed that the temperature characteristic for the VBE of the bipolar transistor is slightly less stringent than −1.9 mV/° C. as explained with reference to FIG. 7 , and is slightly smaller than −1.9 mV/° C., for example, in the vicinity of −1.85 mV/° C., the temperature characteristic of the output voltage VREF of the reference voltage circuit is given by:

1 R 1 ⁢ β 0 ⁢ ( 1 - 1 K 1 ) ⁢ K 3 K 3 + 1 ⁢ ( 1 - 1 K 2 ⁢ K 3 ) = 0.37 ⁢ ⁢ V ( 55 )

in case the temperature characteristic of VBE 1 of −1.85 mV/° C. and that of VOS of 500 ppm/° C. cancel each other.

If, in this case, VBE 1 =0.7 V, the output voltage VREF of the reference voltage circuit shown in FIG. 8 is given by:

VREF =1.07 V   (56).

Since the circuit of the present embodiment takes the configuration of a voltage follower type operational amplifier, it is possible to subtract the offset voltage. In this case, the connection of various circuit components may be kept unchanged as shown in FIG. 8 and only the gate W/L ratio of the transistors MM 1 and MM 2 and the gate W/L ratio of the transistors MM 3 and MM 4 are changed to K 2 :1 and to 1:K 3 , respectively. The output voltage VREF of the reference voltage circuit in this case is given by:

VREF=VBE 1 −VOS   (57).

Thus, if the offset voltage shown by the equation (57) is subtracted, the output voltage VREF of the reference voltage circuit for VBE 1 =0.7 V is given by:

VREF=0.33V  (58)

it being noted that the output voltage VREF of the reference voltage circuit exhibits a negative temperature characteristic of −3.7 mV° C.

FIG. 9 shows a modification of the embodiment shown in FIG. 8 . The drain and the gate of the transistor MM 2 of the differential pair are connected together and the output VREF is taken out from the drain. In FIG. 9 , the output voltage VREF of the reference voltage circuit is given by:

VREF=VBE+V os ,

as in equation (54), where V os is given by the equation (53).

That is, a reference voltage not dependent upon temperature is output, as mentioned above. Although this modification lacks in capability of feeding a current from the reference voltage output terminal, it is effective as a voltage source for supplying the reference voltage.

In the above-described embodiments, the diode-connected bipolar transistors Q 1 and Q 2 may well be replaced by diodes. A Bi-CMOS circuit in which the bipolar transistor and the MOS transistors are constructed on one and the same substrate may also construct it. Although the present invention has been explained based on the above-described embodiments, the present invention is not limited to the particular structure shown therein and may, of course, be modified or corrected by those skilled in the art within the scope of the invention as defined by the claims.

The meritorious effects of the present invention are summarized as follows.

As described above, the present invention gives the following effects:

The first effect of the present invention is that a reference voltage circuit having an output voltage of 1.2 V and not exhibiting a temperature characteristic may readily be implemented by the CMOS process.

The reason is that, in the reference voltage circuit of the present invention, the circuitry is constructed merely using active devices, without employing resistors as in the conventional circuitry shown in FIG. 10 .

The second effect of the present invention is that the reference voltage circuit not exhibiting a temperature dependent characteristic and having an output voltage lowers than 1.2 V may be implemented by the CMOS process.

The reason is that, in the reference voltage circuit of the present invention, the positive temperature characteristic of the bipolar transistor is canceled out by the negative temperature characteristic of the bipolar transistor of −1.9 mV° C. by exploiting a temperature characteristic of 5000 ppm° C. derived from the term of 1/β.

It should be noted that other objects, features and aspects of the present invention will become apparent in the entire disclosure and that modifications may be done without departing the gist and scope of the present invention as disclosed herein and claimed as appended herewith.

Also it should be noted that any combination of the disclosed and/or claimed elements, matters and/or items might fall under the modifications aforementioned.