Level conversion for use in semiconductor device

This nonprovisional application is a continuation application of and claims the benefit of International Application No. PCT/JP2003/02178, filed Feb. 27, 2003. The disclosure of the prior application is hereby incorporated herein in its entirety by reference.

1. Field of the Invention

The present invention relates to a semiconductor device having an interface for converting the level of a signal to a voltage level higher than the voltage of its own power supply. More particularly, the present invention relates to a semiconductor device capable of converting the level of a signal to a high voltage level without continuous current consumption.

2. Description of Related Art

Japanese unexamined patent publication No. H10(1998)-22810 discloses an output buffer circuit capable of outputting a signal having a voltage level higher than the voltage of its own power supply. In accordance with the above publication '810, as shown in FIG. 15 , the voltage level of an output signal OUT is sequentially amplified from a low voltage level VDD to higher voltage levels (VL 1 , VH 1 ), (VL 2 , VH 2 ), (VL 3 , VH 3 ) and (VL 3 , VDD 2 ) by using four intermediate inverters operating at power-supply voltages at sequentially increasing voltage levels in order to raise the voltage level of the output signal OUT to a high voltage level VDD 2 .

The voltage levels VL 1 to VL 3 and VH 1 to VH 3 of the power-supply voltages of the intermediate inverters are obtained as a result of applying a voltage division potentiometer comprising resistors 105 to 111 to the high-level voltage VDD 2 .

In a state where the output buffer circuit disclosed in the publication '810 is capable of outputting the output signal OUT, the voltage levels VL 1 to VL 3 and VH 1 to VH 3 of the power-supply voltages to be supplied to the intermediate inverters are obtained as a result of dividing a power-supply voltage VDD 2 through the use of a voltage division potentiometer comprising the resistors 105 to 111 . Thus, after a transition of a logic level of an input signal IN has been propagated through the intermediate inverters, the logic states of the input/output signals of the intermediate inverters are fixed and, in spite of the fact that no current is consumed in the intermediate inverters, steady current consumption occurs from the power-supply voltage VDD 2 through the resistors 105 to 111 .

In applications to a technical field of mainly portable devices required to operate at a low current consumption, such steady current consumption raises a problem.

It is thus an object or the present invention, which addresses the problem, to provide a semiconductor device capable of converting the level of a signal to a high voltage level without causing steady current consumption in interfacing a signal between a first circuit group operating at a first power-supply voltage and a second circuit group operating at a second power-supply voltage, which is higher than the first power-supply voltage.

In order to achieve the object described above, a semiconductor device according to a first aspect of the invention is characterized in that the semiconductor device comprises: a first circuit group operating by being driven by a power supply at a voltage level between a reference voltage and a first power-supply voltage, a second circuit group, which operates by being driven by a power supply at a voltage level between the reference voltage and a second power-supply voltage, which is higher than the first power-supply voltage, a high-side voltage-controlled device having a first type of electrical conduction at an input stage of the second circuit group for controlling an output of the second power-supply voltage; and a level conversion circuit, which is provided as an interface from the first circuit group to the second circuit group, operates by being driven by a power supply at a voltage level between the first power-supply voltage and the second power-supply voltage to control electrical conduction of the high-side voltage-controlled device and has: a first voltage-controlled device, which has the first type of electrical conduction and is provided between the high-side voltage-controlled device and a line of the first power-supply voltage for supplying the first power-supply voltage with the high-side voltage-controlled device put in an electrically conductive state; and a second voltage-controlled device, which has the first type of electrical conduction and is provided between the high-side voltage-controlled device and a line of the second power-supply voltage for supplying the second power-supply voltage with the high-side voltage-controlled device put in an electrically non-conductive state.

As an interface between the first and second circuit groups, the semiconductor device according to the first aspect of the invention may have a level conversion circuit, which operates between the first power-supply voltage and the second power-supply voltage. In the level conversion circuit, the first voltage-controlled device controlled by a voltage supplies the first power-supply voltage whereas the second voltage-controlled device controlled by a voltage supplies the second power-supply voltage to put the high-side device, which is employed in the second circuit group controlled by a voltage and provided with a characteristic of the first type of electrical conduction, in an electrically conductive state or an electrically non-conductive state.

Thus, since the level conversion circuit has a configuration of supplying the second power-supply voltage relative to the first power-supply voltage instead of being relative to the reference voltage, a difference in supplied voltage is a difference in voltage level between the first power-supply voltage and the second power-supply voltage. Accordingly, a configuration element incapable of withstanding the second power-supply voltage can be employed in the interface. In addition, in order to assure a withstand-voltage characteristic, it is not necessary to generate an intermediate third power-supply voltage by proportional division of the first power-supply voltage and the second power-supply voltage. Thus, there is no current consumption accompanying the proportional division.

Within the range of the withstand voltage of the device and without steady current consumption, the first power-supply voltage or the second power-supply voltage is supplied to the high-side voltage-controlled device to put the high-side voltage-controlled device in an electrically conductive state or an electrically non-conductive state in accordance with the supplied voltage with the second power-supply voltage taken as a reference. In this way, electrical conduction of the high-side voltage-controlled device can be controlled.

Since the first and second voltage-controlled devices employed in the level conversion circuit have the same type of electrical conduction as the high-side voltage-controlled device, the control of the first and second power-supply voltages each appearing in the level conversion circuit as a floated voltage relative to the reference voltage can be executed with ease.

Further, a semiconductor device according to a second aspect of the invention is characterized by comprising: a first circuit group operating by being driven by a power supply at a voltage level between a reference voltage and a first power-supply voltage, a second circuit group, which operates by being driven by a power supply at a voltage level between the reference voltage and a second power-supply voltage, which is higher than the first power-supply voltage, an output PMOS transistor at an input stage of the second circuit group with a gate driven by the first power-supply voltage to deliver an output of the second power-supply voltage; and a level conversion circuit, which is provided as an interface from the first circuit group to the second circuit group, operates by being driven by a power supply at a voltage level between the first power-supply voltage and the second power-supply voltage to control electrical conduction of the output PMOS transistor and has: a first PMOS transistor provided on an electrical path from a line of the first power-supply voltage to a gate of the output PMOS transistor and controlled to enter an electrically conductive state by a first signal supplied by the first circuit group to a gate of the first PMOS transistor; a second PMOS transistor provided on an electrical path from a line of the second power-supply voltage to the gate of the output PMOS transistor and controlled to enter an electrically conductive state by the first power-supply voltage supplied to a gate of the second PMOS transistor; a third PMOS transistor provided on an electrical path from the line of the first power-supply voltage to a gate of the second PMOS transistor and controlled to enter an electrically conductive state by a second signal supplied by the first circuit group to a gate of the third PMOS transistor; and a fourth PMOS transistor provided on an electrical path from the line of the second power-supply voltage to the gate of the second PMOS transistor and controlled to enter an electrically conductive state or an electrically non-conductive state by the first or second power-supply voltage to a gate of the fourth PMOS transistor by way of the first or second PMOS transistor respectively, wherein either the first PMOS transistor or the third PMOS transistor is controlled to enter an electrically conductive state.

In the semiconductor device according to the second aspect of the invention, a first PMOS transistor is put in an electrically conductive state to supply the first power-supply voltage to the gates of an output PMOS transistor and a fourth PMOS transistor, putting the output PMOS transistor and the fourth PMOS transistor in an electrically conductive state. When the fourth PMOS transistor is put in an electrically conductive state, the second power-supply voltage is supplied to the gate of a second PMOS transistor, putting the second PMOS transistor in an electrically non-conductive state. At that time, a third PMOS transistor is put in an electrically non-conductive state. Conversely, when the first PMOS transistor is put in an electrically non-conductive state but the third PMOS transistor is put in an electrically conductive state, the second PMOS transistor is put in an electrically conductive state and the output PMOS transistor and the fourth PMOS transistor are put in an electrically non-conductive state

In the above configuration, terminals of the transistors can be connected to each other directly or through circuit components each having a voltage-dropping function as long as a voltage equal to or larger than the threshold voltage of each of the transistors is applied between the gate and source of the transistor when the first power-supply voltage is supplied to the gate of the transistor. Examples of the circuit components are resistors and/or diodes.

In addition, the high level of the first and second signals generated by the first circuit group can be the level of the first power-supply voltage, a voltage raised from the first power-supply voltage or even a voltage further raised from the first power-supply voltage. With the first or second signal set at the high level, the first or third PMOS transistor is put in an electrically non-conductive state.

Thus, since the level conversion circuit has a configuration of supplying the second power-supply voltage relative to the first power-supply voltage instead of being relative to the reference voltage, a difference in supplied voltage is equal to a difference in voltage level between the first power-supply voltage and the second power-supply voltage. Accordingly, the first to fourth PMOS transistors do not have to be transistors each capable of enduring the second power-supply voltage as a withstand voltage. That is, the first to fourth PMOS transistors can each be a circuit component having a lower withstand voltage. In addition, in the conversion of a signal level, it is not necessary to generate an intermediate third power-supply voltage by proportional division of the first power-supply voltage and the second power-supply voltage. Thus, there is no current consumption accompanying the proportional division.

By supplying a voltage equal to or larger than the threshold voltage of a PMOS transistor between the gate and source of the transistor, the transistor can be put in an electrically conductive state. Since the second power-supply voltage is applied to the sources of the output, first and fourth PMOS transistors, by supplying a voltage with voltage drop equal to or larger than the threshold voltage from second power-supply voltage to the gates of the output, first and fourth PMOS transistors, the output, first and fourth PMOS transistors can be controlled to enter an electrically conductive state or an electrically non-conductive state provided that the first power-supply voltage and the second power-supply voltage are set at such values that the difference between the first and second power-supply voltages is equal to or larger than the threshold voltage of the output, first and fourth PMOS transistors. In addition, a circuit for supplying the first power-supply voltage and the second power-supply voltage to the output, second and fourth PMOS transistors can be constructed with ease by employing PMOS transistors suitable for execution of electrical conduction on voltages on the high side. Since such a circuit is composed of PMOS transistors, the level conversion circuit can be built with ease between the first and second power-supply voltages, which are voltages floating with respect to the reference voltage.

The above and further objects and novel features of the invention will more fully appear from the following detailed description when the same is read in connection with the accompanying drawings. It is to be expressly understood, however, that the drawings are for the purpose of illustration only and are not intended as a definition of the limits of the invention.

FIG. 1 is a circuit diagram showing a preferred embodiment of the present invention;

FIG. 2 is a circuit diagram showing a first method for preventing PMOS transistors employed in a level conversion circuit from incorrectly entering an electrically conductive state;

FIG. 3 is a circuit diagram showing a second method for preventing the PMOS transistor employed in the level conversion circuit from incorrectly entering an electrically conductive state;

FIG. 4 is a circuit diagram showing a third method for preventing the PMOS transistor employed in the level conversion circuit from incorrectly entering an electrically conductive state;

FIG. 5 is a diagram showing a concrete typical embodiment of the third method shown in FIG. 4 ;

FIG. 6 is a circuit diagram showing a fourth method for preventing the PMOS transistor employed in the level conversion circuit from incorrectly entering an electrically conductive state;

FIG. 7 is a diagram showing a characteristic of a voltage appearing at the gate of a PMOS transistor PM 5 subjected to the fourth method;

FIG. 8 is a diagram showing a characteristic of a voltage appearing at the gate of a PMOS transistor PM 1 subjected to the fourth method;

FIG. 9 is a circuit diagram showing a first concrete typical embodiment of an N-well electric-potential control unit for the fourth method;

FIG. 10 is a circuit diagram showing a second concrete typical embodiment of the N-well electric-potential control unit for the fourth method;

FIG. 11 is a diagram showing a well electric potential varied by the first and second concrete typical embodiments of the N-well electric-potential control unit;

FIG. 12 is a circuit diagram showing a third concrete typical embodiment of the N-well electric-potential control unit for the fourth method;

FIG. 13 is a diagram showing a well electric potential varied by the third concrete typical embodiment of the N-well electric-potential control unit;

FIG. 14 is a circuit diagram showing a low-side level conversion circuit for driving an NMOS transistor NM 51 as one of level conversion circuits implemented by embodiments; and

FIG. 15 is a circuit diagram showing a level conversion circuit based on the conventional technology.

Embodiments implementing a semiconductor device provided by the present invention are explained by referring to FIGS. 1 to 14 as follows.

FIG. 1 is a circuit diagram showing a preferred embodiment implementing a semiconductor device provided by the present invention. The semiconductor device comprises a first circuit group 3 and a second circuit group 5 . The first circuit group 3 is a group of circuits operating by being driven by a first power-supply voltage VDD 1 relative to a reference voltage VSS. On the other hand, the second circuit group 5 is a group of circuits operating by being driven by a second power-supply voltage VDD 2 relative to the reference voltage VSS. The second power-supply voltage VDD 2 has a voltage level higher than the first power-supply voltage VDD 1 .

The first circuit group 3 is a circuit portion required to have a high processing speed. The first circuit group 3 is a circuit portion suitable for applications to control and processing, which are executed in a field of electronic devices each having an increasing number of functions and a rising processing speed. In general, the first circuit group 3 is implemented by adoption of a process technology in which miniaturization is making progress to increase the number of functions in the first circuit group 3 and raise the processing speed of the first circuit group 3 . Thus, an inverter gate I 31 serving as a typical device employed in the first circuit group 3 is required to operate at a low voltage. The first power-supply voltage VDD 1 is a power-supply voltage satisfying this required specification. At the first power-supply voltage VDD 1 , which is a low power-supply voltage, the withstand-voltage characteristic of a device employed in the first circuit group 3 can be assured. For the second power-supply voltage VDD 2 , which is a power-supply voltage higher than the first power-supply voltage VDD 1 , the withstand-voltage characteristic of a device may not be assured in some cases. In such a case, the second power-supply voltage VDD 2 cannot be applied to the device.

The second circuit group 5 is a circuit portion operating at the second power-supply voltage VDD 2 , which is a higher power-supply voltage. The second circuit group 5 is a control portion of typically an apparatus operating in an existing power-supply voltage system, or the second circuit group 5 is a circuit portion suitable for applications to operations to control and drive typically any one of another device and another apparatus, which operate at a predetermined voltage. These control portion and circuit portion require the second power-supply voltage VDD 2 having a voltage level different from the first power-supply voltage VDD 1 , which is needed to increase the number of functions and raise the processing speed. In addition, the second power-supply voltage VDD 2 may have a voltage level higher than the first power-supply voltage VDD 1 in some cases.

In the circuit shown in FIG. 1 , an input signal IN having an amplitude equal to the first power-supply voltage VDD 1 in the first circuit group 3 may in some cases be output as an output signal OUT having an amplitude equal to the second power-supply voltage VDD 2 in the second circuit group 5 . In this case, the input signal IN supplied to the first circuit group 3 is a signal obtained as a result of an operation such as a control operation or a processing operation. On the other hand, the output signal OUT generated by the second circuit group 5 is output to another device external to the semiconductor device as it is to be used as a signal to drive or control the other device. As an alternative, the output signal OUT is used as an input signal supplied to another second circuit group 5 .

The input portion of the second circuit group 5 comprises a switch on the high side and a switch on the low side. The switch on the high side is a PMOS transistor PM 51 having its source connected to the line of the second power-supply voltage VDD 2 . On the other hand, a switch on the low side is an NMOS transistor NM 51 having its source connected to the line of the reference voltage VSS. Signals generated by a level conversion circuit 1 to be described later are supplied to the gates of the PMOS transistor PM 51 and the NMOS transistor NM 51 to execute switching control exclusively from each other. The drain of the PMOS transistor PM 51 is connected to the source of a PMOS transistor PM 52 and the drain of the PMOS transistor PM 52 is connected to the drain of an NMOS transistor NM 52 . The drain of the NMOS transistor NM 51 is connected to the source of the NMOS transistor PM 52 and the drain of the NMOS transistor NM 52 is connected to the drain of the PMOS transistor PM 52 . The drains of the PMOS transistor PM 52 and the NMOS transistor NM 52 are connected to each other at a junction point used as an output terminal OUT. The gates of the PMOS transistor PM 52 and the NMOS transistor NM 52 are connected to the line of the first power-supply voltage VDD 1 .

The PMOS transistor PM 52 is electrically conductive when the PMOS transistor PM 51 is put in an electrically conductive state and the NMOS transistor NM 52 is electrically conductive when the NMOS transistor NM 51 is put in an electrically conductive state. When the PMOS transistor PM 51 and the PMOS transistor PM 52 are put in an electrically conductive state, the second power-supply voltage VDD 2 is applied to the drain of the NMOS transistor NM 52 , which thereby enters an electrically non-conductive state, establishing a bias state of a saturation characteristic. By the same token, when the NMOS transistor NM 51 and the NMOS transistor NM 52 are put in an electrically conductive state, the reference voltage VSS is applied to the drain of the PMOS transistor PM 52 , which thereby enters an electrically non-conductive state, establishing a bias state of a saturation characteristic. Thus, a voltage lower than the first power-supply voltage VDD 1 by a difference equal to the threshold voltage of the NMOS transistor NM 52 is applied to the drain of the NMOS transistor NM 51 , and a voltage higher than the first power-supply voltage VDD 1 by a difference equal to the threshold voltage of the PMOS transistor PM 52 is applied to the drain of the PMOS transistor PM 51 . As a result, also in the second circuit group 5 to which the second power-supply voltage VDD 2 relative to the reference voltage VSS is applied, only a difference in voltage level between the second power-supply voltage VDD 2 and the first power-supply voltage VDD 1 is applied to the PMOS transistor PM 51 and the PMOS transistor PM 52 whereas only a voltage equal to the first power-supply voltage VDD 1 is applied to the NMOS transistor NM 51 and the NMOS transistor NM 52 .

For the above reason, the second circuit group 5 to which the second power-supply voltage VDD 2 having a high voltage level is applied can be constructed from transistors each having a characteristic of a low withstand voltage.

It is to be noted that, while this embodiment comprises the PMOS transistor PM 52 and the NMOS transistor NM 52 by one stage as transistors each used for assuring a withstand-voltage characteristic, another embodiment can also be designed from two or more stages. In this case, it is desirable to provide a configuration for shifting an applied voltage stage by stage by properly adjusting a voltage applied to the gate of every MOS transistor. By providing a multi-stage configuration, a circuit configuration can be constructed from transistors each having a characteristic of low withstand voltage even for a case in which the second power-supply voltage VDD 2 having an even higher voltage level is supplied.

The level conversion circuit 1 mentioned above is a circuit provided between the first circuit group 3 and the second circuit group 5 as a circuit for converting the level of a signal from the first power-supply voltage VDD 1 to the second power-supply voltage VDD 2 .

The level conversion circuit 1 includes a high-side level conversion circuit 4 comprising PMOS transistors PM 1 to PM 4 . The high-side level conversion circuit 4 is a circuit for driving the gate of the PMOS transistor PM 51 serving as a switch on the high side as described above. The sources of the PMOS transistors PM 1 and PM 3 are connected to a line of the first power-supply voltage VDD 1 whereas the sources of the PMOS transistors PM 2 and PM 4 are connected to a line of the second power-supply voltage VDD 2 . The gate of the PMOS transistor PM 4 is connected to the drains of the PMOS transistors PM 1 and PM 2 as well as the gate of the PMOS transistor PM 51 at a node N 3 . On the other hand, the gate of the PMOS transistor PM 2 is connected to the drains of the PMOS transistors PM 3 and PM 4 at a node N 4 . The gate of the PMOS transistor PM 1 is connected to the output terminal of the inverter gate I 31 at a node N 1 . The gate of the PMOS transistor PM 3 is connected to a node N 2 to which the input signal IN is supplied.

It is to be noted that a signal for driving and controlling the gate of the NMOS transistor NM 51 on the low side is a signal having a voltage level converted from the voltage level of the input signal IN. This signal is generated from a low-side level conversion circuit 6 to be described later by referring to FIG. 14 .

When the input signal IN is a high-level signal having the voltage level of the first power-supply voltage VDD 1 , a signal output by the inverter gate I 31 as a signal appearing at the node N 1 is a low-level signal having the voltage level of the reference voltage VSS. In this case, since the input signal IN is supplied to the node N 2 connected to the gate of the PMOS transistor PM 3 , the first power-supply voltage VDD 1 is supplied to the gate of the PMOS transistor PM 3 . At that time, since the gate of the PMOS transistor PM 1 is wired to the node N 1 , the reference voltage VSS is supplied to the gate of the PMOS transistor PM 1 . Since the source of the PMOS transistor PM 1 is connected to the line of the first power-supply voltage VDD 1 , the PMOS transistor PM 1 is put in an electrically conductive state.

With the PMOS transistor PM 1 put in an electrically conductive state, the first power-supply voltage VDD 1 is supplied to the node N 3 , which is wired to the drain of the PMOS transistor PM 1 . Accordingly, the first power-supply voltage VDD 1 is supplied to the gates of the PMOS transistor PM 4 and the PMOS transistor PM 51 . Since the sources of the PMOS transistor PM 4 and the PMOS transistor PM 51 are connected to the line of the second power-supply voltage VDD 2 , a difference in voltage level between the first power-supply voltage VDD 1 and the second power-supply voltage VDD 2 is applied between the gate and source of the PMOS transistor PM 4 as well as the gate and source of the PMOS transistor PM 51 . Thus, the PMOS transistor PM 4 is put in an electrically conductive state provided that the difference in voltage level between the first power-supply voltage VDD 1 and the second power-supply voltage VDD 2 is at least equal to the threshold voltage of the PMOS transistor PM 4 . By the same token, the PMOS transistor PM 51 is put in an electrically conductive state provided that the difference in voltage level between the first power-supply voltage VDD 1 and the second power-supply voltage VDD 2 is at least equal to the threshold voltage of the PMOS transistor PM 51 .

With the PMOS transistor PM 4 put in an electrically conductive state, the second power-supply voltage VDD 2 is supplied to the node N 4 , which is wired to the drain of the PMOS transistor PM 4 . Accordingly, the PMOS transistor PM 2 is put in an electrically non-conductive state. Thus, the node N 3 receiving the first power-supply voltage VDD 1 through the PMOS transistor PM 1 is not connected to the line of the second power-supply voltage VDD 2 . Since the gate of the PMOS transistor PM 3 is wired to the node N 2 , the first power-supply voltage VDD 1 (the input signal IN) is supplied to the gate of the PMOS transistor PM 3 but, since the drain of the PMOS transistor PM 3 is wired to the node N 4 , on the other hand, the second power-supply voltage VDD 2 is supplied to the drain of the PMOS transistor PM 3 . Thus, a difference in voltage level between the first power-supply voltage VDD 1 and the second power-supply voltage VDD 2 is applied between the gate and drain of the PMOS transistor PM 3 . As a result, the PMOS transistor PM 3 is put in an electrically non-conductive state provided that the difference in voltage level between the first power-supply voltage VDD 1 and the second power-supply voltage VDD 2 is small in comparison with the threshold voltage of the PMOS transistor PM 3 . Thus, the node N 4 receiving the second power-supply voltage VDD 2 through the PMOS transistor PM 4 is not connected to the line of the first power-supply voltage VDD 1 .

When the input signal IN is a low-level signal having the voltage level of the reference voltage VSS, on the other hand, operating states opposite to what are described above prevail since the levels of the applied voltages are inverted.

That is, the reference voltage VSS is applied to the gate of the PMOS transistor PM 3 , causing the PMOS transistor PM 3 to enter an electrically conductive state. Thus, the first power-supply voltage VDD 1 is applied to the gate of the PMOS transistor PM 2 , causing the PMOS transistor PM 2 to enter an electrically conductive state. Assume that the difference in voltage level between the first power-supply voltage VDD 1 and the second power-supply voltage VDD 2 is at least equal to the threshold voltage of the PMOS transistor PM 2 . In this case, since the second power-supply voltage VDD 2 is supplied to the node N 3 , the PMOS transistor PM 4 and the PMOS transistor PM 51 are put in an electrically non-conductive state. Thus, the second power-supply voltage VDD 2 is supplied to neither the output terminal OUT nor the node N 4 , which is receiving the first power-supply voltage VDD 1 through the PMOS transistor PM 3 .

Even though the difference in voltage level between the first power-supply voltage VDD 1 and the second power-supply voltage VDD 2 is applied between the gate and drain of the PMOS transistor PM 1 , the PMOS transistor PM 1 is put in an electrically non-conductive state provided that the difference in voltage level between the first power-supply voltage VDD 1 and the second power-supply voltage VDD 2 is small in comparison with the threshold voltage of the PMOS transistor PM 1 . Thus, the first power-supply voltage VDD 1 is not supplied to the node N 3 , which is receiving the second power-supply voltage VDD 2 through the PMOS transistor PM 2 .

On the other hand, a signal generated by a low-side level conversion circuit 6 to be described later by referring to FIG. 14 is supplied to the gate of the NMOS transistor NM 51 as described above. Since the supplied signal has the same phase as the input signal IN, control of electrical conduction is executed exclusively from the PMOS transistor PM 51 .

When the PMOS transistor PM 51 is put in an electrically conductive state, the second power-supply voltage VDD 2 is supplied to the drain of the PMOS transistor PM 51 connected to the source of the PMOS transistor PM 52 . When the PMOS transistor PM 52 has the same threshold voltage as the PMOS transistor PM 51 , the PMOS transistor PM 52 is also put in an electrically conductive state, supplying the second power-supply voltage VDD 2 to the output terminal OUT. Since the NMOS transistor NM 52 is in an electrically non-conductive state, the output signal OUT appearing at the output terminal OUT is a signal having the voltage level of the second power-supply voltage VDD 2 .

When the PMOS transistor PM 51 is in an electrically non-conductive state, on the other hand, the NMOS transistor NM 51 is put in an electrically conductive state, connecting its drain to the reference voltage VSS. At that time, the NMOS transistor NM 52 is also put in an electrically conductive state, supplying the reference voltage VSS to the output terminal OUT. The output signal OUT appearing at the output terminal OUT is a signal having the voltage level of the reference voltage VSS.

In accordance with the high-side level conversion circuit 4 employed in the level conversion circuit 1 , since the difference in voltage level between the first power-supply voltage VDD 1 and the second power-supply voltage VDD 2 is at least equal to the threshold voltage of the PMOS transistor PM 2 , PM 4 , PM 51 and PM 52 , the PMOS transistor PM 2 , PM 4 , PM 51 and PM 52 can be put in an electrically conductive state or electrically non-conductive state by controlling the gates of the PMOS transistor PM 2 , PM 4 , PM 51 and PM 52 by using the first power-supply voltage VDD 1 and the second power-supply voltage VDD 2 . The high-side level conversion circuit 4 can be constructed from PMOS transistors with ease.

In converting the input signal IN with an amplitude varying between the reference voltage VSS and the first power-supply voltage VDD 1 into a signal with an amplitude varying between the first power-supply voltage VDD 1 and the second power-supply voltage VDD 2 for the purpose of controlling the electrical conduction of the PMOS transistor PM 51 , no steady current electrical path from the line of the second power-supply voltage VDD 2 to the line of the first power-supply voltage VDD 1 is created. In addition, a third power-supply voltage having a voltage level between the first power-supply voltage VDD 1 and the second power-supply voltage VDD 2 is also not required. Thus, steady current consumption due to voltage division of the first power-supply voltage VDD 1 and the second power-supply voltage VDD 2 does not occur either.

Moreover, since circuits is constructed between the first power-supply voltage VDD 1 and the second power-supply voltage VDD 2 in place of the reference voltage VSS, a difference in voltage level applied to the transistors is a difference in voltage level between the first power-supply voltage VDD 1 and the second power-supply voltage VDD 2 . The PMOS transistor PM 1 to the PMOS transistor PM 4 serving as first to fourth PMOS transistors respectively are not required to withstand the second power-supply voltage VDD 2 . Instead, the PMOS transistors PM 1 to PM 4 can each be a transistor having a low withstand voltage.

Furthermore, at the input stage of the second circuit group 5 , for the PMOS transistor PM 51 , the PMOS transistor PM 52 is used as a transistor for assuring a withstand-voltage characteristic and, for the NMOS transistor NM 51 , the NMOS transistor NM 52 is used as a transistor for assuring a withstand-voltage characteristic. Only a difference in voltage level between the second power-supply voltage VDD 2 and the first power-supply voltage VDD 1 is applied to the PMOS transistor PM 51 and the PMOS transistor PM 52 whereas only a voltage equal to the first power-supply voltage VDD 1 is applied to the NMOS transistor NM 51 and the NMOS transistor NM 52 . Thus, the second circuit group 5 can be constructed from transistors each having a low withstand voltage characteristic.

These MOS transistors each having a low withstand voltage each have a gate oxide film with a small thickness providing a high circuit operation speed.

With the PMOS transistor PM 2 put in an electrically conductive state allowing the second power-supply voltage VDD 2 to be supplied to the node N 3 , the electrical path from the node N 3 to the line of the first power-supply voltage VDD 1 must be cut off by the PMOS transistor PM 1 . By the same token, with the PMOS transistor PM 4 put in an electrically conductive state allowing the second power-supply voltage VDD 2 to be supplied to the node N 4 , the electrical path from the node N 4 to the line of the first power-supply voltage VDD 1 must be cut off by the PMOS transistor PM 3 . These electrical paths are cut off by taking any of the following four methods.

FIG. 2 is a diagram showing the first method. In accordance with this method, the PMOS transistors PM 1 and PM 3 are each designed into a configuration different from those of the PMOS transistors PM 2 , PM 4 , PM 51 and PM 52 . In general, the PMOS transistor PM 1 or PM 3 is controlled to an electrically non-conductive state by applying the first power-supply voltage VDD 1 by a signal generated by the first circuit group 3 to its gate. In order to cut off the second power-supply voltage VDD 2 applied to the drain of the PMOS transistors PM 1 and PM 3 , it is necessary to take a threshold voltage deeper than the difference between the first power-supply voltage VDD 1 and the second power-supply voltage VDD 2 as the threshold voltage of the PMOS transistor PM 1 or PM 3 . As substitutes for the PMOS transistors PM 2 , PM 4 , PM 51 and PM 52 , it is preferable to employ transistors each having a deeper threshold voltage.

FIG. 3 is a diagram showing the second method. In accordance with this method, the PMOS transistors PM 1 and PM 3 are each designed into a configuration identical with those of the PMOS transistors PM 2 , PM 4 , PM 51 and PM 52 . A voltage-level conversion circuit LS for converting a voltage level is connected to the nodes N 1 and N 2 , which are wired to the gates of the PMOS transistors PM 1 and PM 3 respectively. That is, a signal generated by the first circuit group 3 is supplied to the gate of the PMOS transistor PM 1 or PM 3 by way of the voltage-level conversion circuit LS. The PMOS transistor PM 1 or PM 3 is controlled to an electrically non-conductive state by supplying a signal having a voltage level VH higher than the first power-supply voltage VDD 1 . When the voltage-level conversion circuit LS is so set that a difference in voltage level between the first power-supply voltage VDD 1 and the voltage level VH generated by the voltage-level conversion circuit LS is small in comparison with the threshold voltage of the PMOS transistor PM 1 or PM 3 , the PMOS transistor PM 1 or PM 3 can be sustain in an electrically non-conductive state when the second power-supply voltage VDD 2 is being supplied to the drain of the PMOS transistor PM 1 or PM 3 respectively.

FIG. 4 is a diagram showing the third method. In accordance with this third method, an NMOS transistor NM 1 is provided between the PMOS transistors PM 1 and PM 2 whereas an NMOS transistor NM 2 is provided between the PMOS transistors PM 3 and PM 4 . The drain of the PMOS transistor PM 1 is connected to the source of the NMOS transistor NM 1 at a node 3 A whereas the drain of the PMOS transistor PM 3 is connected to the source of the NMOS transistor NM 2 at a node 4 A. On the other hand, the drain of the PMOS transistor PM 2 is connected to the drain of the NMOS transistor NM 1 at the node 3 whereas the drain of the PMOS transistor PM 4 is connected to the drain of the NMOS transistor NM 2 at the node 4 . A predetermined common bias voltage VG is supplied to the gates of both the NMOS transistors NM 1 and NM 2 . Instead of supplying the gate bias voltage VB to the gates directly, a bias voltage VB can also be supplied to the gates by way of a voltage-drop unit 7 .

The voltage-drop unit 7 can have a configuration like one shown in FIG. 5 . As shown in the figure, a voltage-drop unit 71 is provided between the second power-supply voltage VDD 2 and the gates of the NMOS transistors NM 1 and NM 2 . The voltage-drop unit 71 comprises diode-connected NMOS transistors provided at a predetermined number of stages. The voltage-drop unit 71 causes a voltage drop VDN, by which the second power-supply voltage VDD 2 is reduced before being supplied to the gates as the gate bias voltage VG (=VDD−VDN). The voltage-drop unit 7 is not limited to the configuration employing the voltage-drop unit 71 . Instead, the voltage-drop unit 7 can comprise any elements such as junction diodes and resistors as long as the elements serve as a means for causing a voltage drop or voltage division.

Refer back to FIG. 4 . Concrete operations according to the third method are explained as follows. With the PMOS transistor PM 1 put in an electrically conductive state, the first power-supply voltage VDD 1 is supplied to the node 3 A. At that time, the difference between the first power-supply voltage VDD 1 and the gate voltage VG applied to the gate of the NMOS transistor NM 1 must be at least equal to the threshold voltage VthN 1 of the NMOS transistor NM 1 , that is, (VG−VDD 1 )≧VthN 1 in order to put the NMOS transistor NM 1 in an electrically conductive state. With the NMOS transistor NM 1 put in an electrically conductive state, the first power-supply voltage VDD 1 is supplied to the node N 3 , causing the PMOS transistors PM 4 and PM 51 to enter an electrically conductive state.

With the PMOS transistor PM 1 put in an electrically non-conductive state, on the other hand, the second power-supply voltage VDD 2 is supplied to the node 3 by way of the PMOS transistor PM 2 . At that time, the NMOS transistor NM 1 operates in a saturated region. A voltage obtained as a result of subtracting the threshold voltage VthN 1 from the bias voltage VG applied to the gate of the NMOS transistor NM 1 , that is, a voltage equal to (VG−VthN 1 ), is supplied to the node 3 A. In order to sustain the PMOS transistor PM 1 in the electrically non-conductive state, the difference in voltage level between the gate voltage (VG−VthN 1 ) supplied to the node 3 A and the first power-supply voltage VDD 1 supplied to the node N 1 wired to the gate of the PMOS transistor PM 1 must be equal to or smaller than the threshold voltage VthP 1 of the PMOS transistor PM 1 . That is, in order to sustain the PMOS transistor PM 1 in the electrically non-conductive state, the following relation must be satisfied:

( VG−VthN 1)− VDD 1< VthP 1

The PMOS transistor PM 3 and the NMOS transistor NM 2 operate in similar ways.

In accordance with the third method shown in FIG. 4 ,

VthN 1≦ VG−VDD 1< VthP 1+ VthN 1  (1)

When a condition expressed by relations (VthN 2 ≦VG−VDD 1 <VthP 3 +VthN 2 ) is satisfied, the electrical conduction and non-conduction of the PMOS transistors PM 1 and PM 3 can be controlled. Equation (1) given above is set for the second power-supply voltage VDD 2 used as the bias voltage VB. When the second power-supply voltage VDD 2 is supplied directly to the gates of the NMOS transistors NM 1 and NM 2 as the gate voltage VG, that is, for VG=VDD 2 , Equation (1) is rewritten into the following relation:

VthN 1≦ VDD 2− VDD 1< VthP 1+ VthN 1

When the second power-supply voltage VDD 2 is reduced by the voltage drop VDN through the voltage-drop unit 71 before being supplied to the gates as the gate bias voltage VG (=VDD 2 −VDN), Equation (1) is rewritten into the following relation:

VthN 1+ VDN≦VDD 2− VDD 1< VthP 1+ VthN 1+ VDN

In addition, when a voltage generator other than the generators of the first power-supply voltage VDD 1 and the second power-supply voltage VDD 2 is available, the use of the other voltage generator for generating the gate voltage VG is conceivable.

In this case, when the gate voltage VG can be set at a lower level by using the voltage-drop unit 71 or the other voltage generator, NMOS transistors each having a lower threshold voltage VthN 1 can be employed. Thus, the number of types of transistors usable as the NMOS transistors NM 1 and NM 2 can be increased.

With the PMOS transistor PM 1 or PM 3 put in an electrically conductive state, a voltage lower than the first power-supply voltage VDD 1 is supplied to the PMOS transistor PM 1 or PM 3 respectively. Thus, even in the case of a configuration comprising the PMOS transistors PM 1 and PM 3 each having the same threshold voltage as those of the PMOS transistors PM 2 , PM 4 and PM 51 , the PMOS transistor PM 1 or PM 3 can be controlled to enter an electrically non-conductive state.

In addition, in the case of any one of the first to third methods, the PMOS transistor PM 1 or PM 3 can be controlled to enter an electrically non-conductive state with ease provided that the PMOS transistors PM 1 and PM 3 are each configured to have a threshold voltage deeper than those of the PMOS transistors PM 2 , PM 4 and PM 51 . In the case of the method utilizing the NMOS transistors NM 1 and NM 2 , in particular, the range of the bias voltage VB can be broadened.

FIG. 6 is a diagram showing the fourth method. In a configuration for taking this fourth method, in accordance with the voltages supplied to the drains of the PMOS transistors PM 1 and PM 3 , the voltages supplied to the gates of the PMOS transistors PM 1 and PM 3 are controlled. In addition, N-well electric potential is also adjusted as well. The PMOS transistors PM 1 and PM 3 can have circuit configurations similar to each other. The operation of the PMOS transistor PM 1 is explained as an example as follows.

First of all, a gate voltage control unit 11 shown in FIG. 6 is described. A PMOS transistor PM 7 is connected between a node N 1 A wired to the gate of the PMOS transistor PM 1 and the node N 3 wired to the drain of the PMOS transistor PM 1 . The gate of the PMOS transistor PM 7 is connected to the line of the first power-supply voltage VDD 1 . When the second power-supply voltage VDD 2 is higher that the first power-supply voltage VDD 1 by a difference in voltage level at least equal to the threshold voltage of the PMOS transistor PM 1 , the PMOS transistor PM 1 can be sustained in an electrically non-conductive state by supplying the second power-supply voltage VDD 2 to the node N 1 A, which is wired to the gate of the PMOS transistor PM 1 .

The signal generated by the first circuit group is supplied to the node N 1 A wired to the gate of the PMOS transistor PM 1 by way of a PMOS transistor PM 5 or an NMOS transistor NM 3 . The gate of the NMOS transistor NM 3 is connected to the line of the first power-supply voltage VDD 1 . A node N 11 wired to the gate of the PMOS transistor PM 5 is connected to the node N 3 wired to the drain of the PMOS transistor PM 1 through a PMOS transistor PM 6 and an NMOS transistor NM 4 . The gate of the PMOS transistor PM 6 is connected to the line of the first power-supply voltage VDD 1 . A signal generated by the first circuit group or a signal having the same phase as the signal generated by the first circuit group is supplied to the gate of the NMOS transistor NM 4 .

In this configuration, as a signal generated by the first circuit group, a signal set at the high level of the first power-supply voltage VDD 1 is supplied to a node N 13 , which is wired to the gate of the NMOS transistor NM 4 . As another conceivable alternative, this signal is supplied to the node N 13 after its voltage is reduced by a voltage-drop circuit B 11 .

A node N 11 wired to the gate of the PMOS transistor PM 5 is connected to the line of the reference voltage VSS through the NMOS transistor NM 5 . The signal generated by the first circuit group is supplied to the gate of the NMOS transistor NM 5 after being inverted by an inverter gate I 11 .

With the signal from the first circuit group set at a low level, the signal needs to be supplied to the node N 1 A, which is wired to the gate of the PMOS transistor PM 1 , by way of the PMOS transistor PM 5 and the NMOS transistor NM 3 . Since the gate of the NMOS transistor NM 3 is connected to the line of the first power-supply voltage VDD 1 , the NMOS transistor NM 3 will be put in an electrically conductive state when voltage level of the signal is lower than the first power-supply voltage VDD 1 by at least the threshold voltage of the NMOS transistor NM 3 .

On the other hand, the gate of the PMOS transistor PM 5 is connected to the node N 3 through the PMOS transistor PM 6 and the NMOS transistor NM 4 . Since a signal set at a low level is supplied to the gate of the NMOS transistor NM 4 , the NMOS transistor NM 4 is put in an electrically non-conductive state. The PMOS transistor PM 6 is also put in an electrically non-conductive state as well. This is because the gate of the PMOS transistor PM 6 is connected to the line of the first power-supply voltage VDD 1 and the node N 3 is brought to the first power-supply voltage VDD 1 due to electrical conduction of the PMOS transistor PM 1 . Thus, an electrical path leading to the node N 3 is cut off. Since an inverted high-level signal is supplied to the gate of the NMOS transistor NM 5 , on the other hand, the NMOS transistor NM 5 is put in an electrically conductive state. Thus, the PMOS transistor PM 5 is also put in an electrically conductive state as well. As a result, a signal set at a low level is supplied to the node N 1 A so that the PMOS transistor PM 1 is put in an electrically conductive state.

When the signal generated by the first circuit group is set at a high level, the level of the voltage appearing at the node N 3 rises to the second power-supply voltage VDD 2 due to electrical conduction of the PMOS transistor PM 2 .

FIG. 7 is a diagram showing a relation between the level of the second power-supply voltage VDD 2 supplied to the node N 3 and the level of a voltage appearing at the node N 11 . On the other hand, FIG. 8 is a diagram showing a relation between the level of the second power-supply voltage VDD 2 supplied to the node N 3 and the level of a voltage appearing at the node N 1 A. In this case, the NMOS transistor NM 5 is put in an electrically non-conductive state since a voltage set at a low level is supplied to the gate of the NMOS transistor NM 5 . The PMOS transistors PM 1 , PM 6 and PM 7 are assumed to have equal threshold voltages VthP. In addition, the relations are explained on the assumption that a voltage set at the voltage level of the first power-supply voltage VDD 1 is supplied to the node N 13 .

When the voltage V (N 3 ) appearing at the node N 3 is lower than the sum of the first power-supply voltage VDD 1 and the threshold voltage VthP of the PMOS transistor PM 6 , that is, for V (N 3 )<(VDD 1 +VthP), the PMOS transistor PM 6 is put in an electrically non-conductive state while the NMOS transistor NM 4 is electrically conductive in a saturated region. Thus, a voltage V (N 11 ) obtained as a result of subtracting the threshold voltage VthN of the NMOS transistor NM 4 from the first power-supply voltage VDD 1 is supplied to the node N 11 . That is, V (N 11 ) (=VDD 1 −VthN) is supplied to the node N 11 as indicated by a line (I) shown in FIG. 7 . When the threshold voltage VthN of the NMOS transistor NM 4 is deep in comparison with the threshold voltage of the PMOS transistor PM 5 , the PMOS transistor PM 5 is put in an electrically conductive state.

The above description is based on the assumption that a voltage V (N 13 ) set at the voltage level of the first power-supply voltage VDD 1 is supplied to the node N 13 . However, the voltage V (N 13 ) can also be a voltage supplied to the node N 13 after being reduced by the voltage-drop circuit B 11 . In this case, a voltage equal to (V (N 13 )−VthN) is supplied to the node N 11 as indicated by a line (II) shown in FIG. 7 where V (N 13 ) is a voltage dropped by the voltage-drop circuit B 11 . In this case the voltage level applied to the node N 11 is (V(N 13 )−VthN). Thus, the PMOS transistor PM 5 can be put in an electrically conductive state even if the threshold voltage VthN of the NMOS transistor NM 4 is equivalent to or even shallower than the threshold voltage VthP of the PMOS transistor PM 5 .

In addition, since the PMOS transistor PM 7 is also put in an electrically non-conductive state, the second power-supply voltage VDD 2 supplied to the node N 3 is not supplied to the node N 1 A.

Thus, a signal generated by the first circuit group at a high level is supplied to the node N 1 A wired to the gate of the PMOS transistor PM 1 by way of the PMOS transistor PM 5 . Normally, this signal has the voltage level of the first power-supply voltage VDD 1 as shown in FIG. 8 . Since a voltage applied between the gate and drain of the PMOS transistor PM 1 is small in comparison with the threshold voltage of the PMOS transistor PM 1 , the PMOS transistor PM 1 is sustained in an electrically non-conductive state. Thus, an electrical path from the node N 3 to the line of the first power-supply voltage VDD 1 is not formed.

When the voltage V (N 3 ) appearing at the node N 3 is equal to or larger than the sum of the first power-supply voltage VDD 1 and the threshold voltage VthP of the PMOS transistor PM 6 , that is, for V (N 3 )≧(VDD 1 +VthP), a voltage at least equal to the threshold voltage VthP of the PMOS transistor PM 6 is applied to the gate of the PMOS transistor PM 6 , putting the PMOS transistor PM 6 in an electrically conductive state. With the PMOS transistor PM 6 put in an electrically conductive state, the node N 11 is linked to the node N 3 , that is, V (N 11 )=V (N 3 ) as shown in FIG. 7 . Thus, the voltage V (N 11 ) becomes equal to the second power-supply voltage VDD 2 and the PMOS transistor PM 5 is put in an electrically non-conductive state. On the other hand, the PMOS transistor PM 7 having the same threshold VthP is put in an electrically conductive state, linking the node N 1 A to the node N 3 , that is, V (N 1 A)=V (N 3 ) as shown in FIG. 8 . Thus, the voltage V (N 1 A) becomes equal to the second power-supply voltage VDD 2 . At the PMOS transistor PM 1 , the electric potential appearing at the gate becomes equal to the electric potential appearing at the drain so that the PMOS transistor PM 1 is sustained in the electrically non-conductive state. Thus, an electrical path from the node N 3 to the line of the first power-supply voltage VDD 1 is not formed.

As described above, the use of the gate voltage control unit 11 shown in FIG. 6 in the fourth method allows a voltage applied to the node N 1 A (or N 2 ) wired to the gate of the PMOS transistor PM 1 (or PM 3 ) to be switched in accordance with the second power-supply voltage VDD 2 relative to the first power-supply voltage VDD 1 even if the second power-supply voltage VDD 2 is applied directly to the node N 3 (or N 4 ) wired to the drain of the PMOS transistor PM 1 (or PM 3 ) when the PMOS transistor PM 1 (or PM 3 ) is put in an electrically non-conductive state so that the PMOS transistor PM 1 (or PM 3 ) can be sustained in an electrically non-conductive state. Since an unnecessary current electrical path from the node N 3 (or N 4 ) wired to the drain of the PMOS transistor PM 1 (or PM 3 ) to the line of the first power-supply voltage VDD 1 is not created, wasteful current consumption can be avoided. When the threshold voltage VthP of the PMOS transistor PM 1 (or PM 3 ) is set at the same value as those of the PMOS transistors PM 6 and PM 7 , the voltage applied to the node N 1 A (or N 2 ) wired to the gate of the PMOS transistor PM 1 (or PM 3 ) can be switched with a voltage at which the PMOS transistor PM 1 (or PM 3 ) starts to enter an electrically conductive state from the drain side to the side of the first power-supply voltage VDD 1 due to the voltage appearing at the node N 3 (or N 4 ) connected to the drain of the PMOS transistor PM 1 (or PM 3 ).

In addition, the PMOS transistor PM 1 (or PM 3 ) can be sustained in an electrically non-conductive state in a stable manner independently of whether the threshold voltage of the PMOS transistor PM 1 (or PM 3 ) is equal to or different from the threshold voltage of the PMOS transistors PM 2 , PM 4 and PM 51 .

Propagation of a signal from the first circuit group to the node 1 A can be controlled by controlling the electrical conduction of the PMOS transistor PM 5 . By putting the PMOS transistor PM 5 in an electrically non-conductive state, the second power-supply voltage VDD 2 supplied to the node N 1 A is not applied to the first circuit group. In addition, by operating the NMOS transistor NM 3 in a saturated region, a voltage applied to the first circuit group is limited to a voltage obtained as a result of subtracting the threshold voltage from the first power-supply voltage VDD 1 and, hence, no over-voltage is applied to the first circuit group.

Next, an N-well electric-potential control unit 9 shown in FIG. 6 is explained. In the high-side level conversion circuit 4 employed in the level conversion circuit 1 and the gate voltage control unit 11 shown in FIG. 6 , the first power-supply voltage VDD 1 is used as the power-supply voltage and, in general, an N-well electric potential also biases the first power-supply voltage VDD 1 . For the PMOS transistors PM 1 (or PM 3 ) and PM 5 to PM 7 , however, when the second power-supply voltage VDD 2 is supplied to the nodes N 3 and N 1 A, due to a difference in level between the first power-supply voltage VDD 1 and the second power-supply voltage VDD 2 , a forward-direction current may flow in some cases by way of a junction biased in the forward direction from the P-type drain to an N well NW. In order to avoid this phenomenon, the electric potential of the N well NW needs to be controlled.

FIG. 9 is a diagram showing an N-well electric-potential control unit 9 A as a first concrete typical embodiment. The N-well electric-potential control unit 9 A includes a PMOS transistor PM 8 A and a PMOS transistor PM 9 A. The source of the PMOS transistor PM 8 A is connected to the line of the first power-supply voltage VDD 1 whereas the drain and back gate of the PMOS transistor PM 8 A are connected to the N well NW. The source of the PMOS transistor PM 9 A is connected to the node N 3 whereas the drain and back gate of the PMOS transistor PM 9 A are connected to the N well NW. The gate of the PMOS transistor PM 9 A is connected to the line of the first power-supply voltage VDD 1 .

The gate of the PMOS transistor PM 8 A is wired to a node P 1 , which is connected to a PMOS-transistor control unit for controlling the electrical conduction/non-conduction of the PMOS transistor PM 8 A.

The PMOS-transistor control unit comprises an NMOS transistor NM 6 A, a PMOS transistor PM 10 A and, if necessary, a first voltage-drop unit 91 . The drain of the NMOS transistor NM 6 A is connected to the node N 3 and the source of the NMOS transistor NM 6 A is connected to the gate of the PMOS transistor PM 8 A at the node P 1 through the first voltage-drop unit 91 . The gate of the NMOS transistor NM 6 A is connected to the line of the first power-supply voltage VDD 1 . The source of the PMOS transistor PM 10 A is connected to the node N 3 whereas the drain of the PMOS transistor PM 10 A is connected to the gate of the PMOS transistor PM 8 A. The back gate and gate of the PMOS transistor PM 10 A are connected to the N well MW and the line of the first power-supply voltage VDD 1 respectively.

The first voltage-drop unit 91 causes a voltage drop from a voltage appearing at the source of the NMOS transistor NM 6 A and supplies the reduced voltage to the node P 1 , which is wired to the gate of the PMOS transistor PM 8 A.

In FIG. 9 , typical embodiment A or B of the first voltage-drop unit 91 are also shown. Typical embodiment A has a predetermined number of diodes connected to each other in series to cause the voltage drop. By properly setting the number of diodes, a voltage not equal to or larger than a voltage obtained as a result of subtracting the threshold voltage from the first power-supply voltage VDD 1 is supplied from the first voltage-drop unit 91 to the node P 1 , which is wired to the gate of the PMOS transistor PM 8 A, to put the PMOS transistor PM 8 A in an electrically conductive state. On the other hand, typical embodiment B divides the voltage appearing at the source of the NMOS transistor NM 6 A by using resistors. By properly setting the voltage-division ratio, a voltage not equal to or larger than a voltage obtained as a result of subtracting the threshold voltage from the first power-supply voltage VDD 1 is supplied from the first voltage-drop unit 91 to the node P 1 , which is wired to the gate of the PMOS transistor PM 8 A.

The N-well electric-potential control unit 9 B as a second concrete typical embodiment shown in FIG. 10 includes a second voltage-drop unit 92 in a PMOS-transistor control unit in place of the first voltage-drop unit 91 employed in the first embodiment 9A of the N-well electric-potential control unit 9 shown in FIG. 9 .

In the PMOS-transistor control unit, the source of the NMOS transistor NM 6 B is connected directly to the gate of the PMOS transistor PM 8 B at the node P 1 and the gate of the NMOS transistor NM 6 B is connected to the line of the first power-supply voltage VDD 1 through the second voltage-drop unit 92 .

The second voltage-drop unit 92 causes a voltage drop from the first power-supply voltage VDD 1 , outputting a bias voltage to the gate of the NMOS transistor NM 6 B. Thus, a properly reduced voltage is output at the source of the NMOS transistor NM 6 B, being supplied to the node P 1 .

Concrete typical embodiments of the second voltage-drop unit 92 shown in FIG. 10 are similar to the typical concrete embodiments of the first voltage-drop unit 91 . To put it concretely, typical concrete embodiment A of the second voltage-drop unit 92 has a predetermined number of diodes connected to each other in series to cause the voltage drop from the first power-supply voltage VDD 1 . On the other hand, typical concrete embodiment B of the second voltage-drop unit 92 divides the first power-supply voltage VDD 1 by using resistors.

FIG. 11 is a diagram showing a relation between a voltage V (N 3 ) appearing at the node N 3 and an electric potential V (NW) of the N well NW as well as a relation between a voltage V (N 3 ) and a voltage V (P 1 ) appearing at the gate of the PMOS transistor PM 8 A for the N-well electric-potential control unit 9 A shown in FIG. 9 and the N-well electric-potential control unit shown in FIG. 10 . The relations shown in FIG. 11 are relations obtained for a case in which the threshold voltage of the NMOS transistors is about equal to the threshold voltage of the PMOS transistors, that is, for VthN≈VthP.

When the voltage V (N 3 ) becomes equal to or larger than the sum of the first power-supply voltage VDD 1 and the threshold voltage VthP, that is, for V (N 3 )≧(VDD 1 +VthP), the PMOS transistor PM 10 A (or PM 10 B) is put in an electrically conductive state. Thus, the voltage V (N 3 ) is biased by the voltage V (P 1 ) is supplied to the second power-supply voltage VDD 2 , putting the PMOS transistor PM 8 A (or PM 8 B) in an electrically non-conductive state. Since the PMOS transistor PM 9 A (or PM 9 B) is in an electrically conductive state, on the other hand, the electric potential V (NW) of the N well becomes equal to the voltage V (N 3 ), that is, the electric potential V (NW) of the N well becomes equal to the second power-supply voltage VDD 2 .

When the voltage V (N 3 ) becomes smaller than the sum of the first power-supply voltage VDD 1 and the threshold voltage VthP, that is, for V (N 3 )<(VDD 1 +VthP), the PMOS transistors PM 9 A and PM 10 A (or PM 9 B and PM 10 B) are put in an electrically non-conductive state. On the other hand, the NMOS transistor NM 6 A (or NM 6 B) is put in an electrically conductive state.

The NMOS transistor NM 6 A (or NM 6 B) operates in a saturated region till the voltage V (N 3 ) decreases to a voltage at a level obtained as a result of subtracting the threshold voltage VthN of the NMOS transistor NM 6 A (or NM 6 B) from the voltage appearing at the gate of the NMOS transistor NM 6 A (or NM 6 B). Thus, the voltage appearing at the source of the NMOS transistor NM 6 A (or NM 6 B) is approximately fixed at the level obtained as a result of subtracting the threshold voltage VthN of the NMOS transistor NM 6 A (or NM 6 B) from the voltage appearing at the gate of the NMOS transistor NM 6 A (or NM 6 B). As the voltage V (N 3 ) decreases further to an even lower level, the NMOS transistor NM 6 A (or NM 6 B) operates linearly in the electrically conductive state, outputting the voltage V (N 3 ) to the source of the NMOS transistor NM 6 A (or NM 6 B) as it is.

The voltage supplied to the gate of the NMOS transistor NM 6 A is the first power-supply voltage VDD 1 as shown in FIG. 9 . On the other hand, the voltage supplied to the gate of the NMOS transistor NM 6 B is a voltage obtained as a result of subtracting the voltage from the first power-supply voltage VDD 1 as shown in FIG. 10 . The voltage supplied to the gate of the NMOS transistor NM 6 A shown in FIG. 9 is supplied to the node P 1 , which is wired to the gate of the PMOS transistor PM 8 A. The voltage supplied to the gate of the NMOS transistor NM 6 B shown in FIG. 10 is applied to the node P 1 , which is wired to the gate of the PMOS transistor PM 8 B. When the first voltage-drop unit 91 and the second voltage-drop unit 92 is not used, the voltage V (P 1 ) is set at a value in a range having an upper limit equal to a voltage obtained as a result of subtracting the threshold voltage VthN of the NMOS transistor NM 6 A (or NM 6 B) from the first power-supply voltage VDD 1 .

When the threshold voltage of the NMOS transistor NM 6 A (or NM 6 B) is about equal to the threshold voltage of the NMOS transistor NM 8 A (or NM 8 B), an electric-potential difference equal to or larger than the threshold voltage VthP is applied between the gate and source of the PMOS transistor PM 8 A (or PM 8 B), causing the PMOS transistor PM 8 A (or PM 8 B) to enter an electrically conductive state, which supplies the first power-supply voltage VDD 1 to the N well.

Even if the threshold voltage of the NMOS transistor NM 6 A (or NM 6 B) is different from the threshold voltage of the PMOS transistor PM 8 A (or PM 8 B), by employing at least either one of the first voltage-drop unit 91 and the second voltage-drop unit 92 , the voltage V (P 1 ) appearing at the node P 1 can be sufficiently lowered to put the PMOS transistor PM 8 A (or PM 8 B) in an electrically conductive state.

FIG. 12 is a diagram showing the N-well electric-potential control unit 9 C as a third concrete typical embodiment. In the first embodiment 9A shown in FIG. 9 or the second embodiment 9B shown in FIG. 10 , the PMOS-transistor control unit controls the PMOS transistor PM 8 A (or PM 8 B). The gate of the PMOS transistor PM 9 A (or PM 9 B) is connected to the first power-supply voltage VDD 1 . In the third embodiment 9C, on the other hand, a connecting relation is inverted. That is to say, an NMOS transistor NM 6 C and a PMOS transistor PM 10 C are placed between the gate of the PMOS transistor PM 9 C and the line of the first power-supply voltage VDD 1 . The gate of the NMOS transistor NM 6 C is connected to the node N 3 . The gates of the PMOS transistors PM 8 C and 10 C are also connected to the node N 3 . In the third embodiment 9C, the first voltage-drop unit 91 and the second voltage-drop unit 92 can be inserted in the same ways as the second concrete typical embodiment 9A, 9B. To put it concretely, the first voltage-drop unit 91 can be inserted between the NMOS transistor NM 6 C and the node P 2 . On the other hand, the second voltage-drop unit 92 can be inserted between the gate of the NMOS transistor NM 6 C and the node N 3 .

FIG. 13 is a diagram showing a relation between the voltage V (N 3 ) and the electric potential V (NW) of the N well as well as a relation between the voltage V (N 3 ) and the voltage V (P 2 ) appearing at the node P 2 for the third embodiment 9C. When the first voltage-drop unit 91 and the second voltage-drop unit 92 are not used, at a voltage V (N 3 ) not equal to or larger than the sum of the first power-supply voltage VDD 1 and the threshold voltage VthN, the NMOS transistor NM 6 C operates in a saturated region. In this state, the voltage V (P 2 ) applied to the node P 2 wired to the gate of the PMOS transistor PM 9 C is supplied to a voltage obtained as a result of subtracting the threshold voltage VthN from the voltage V (N 3 ). Under the condition that the threshold voltage of the NMOS transistor is about equal to the threshold voltage of the PMOS transistor, that is, for VthN≈VthP, the PMOS transistor PM 9 C is put in an electrically conductive state, outputting the voltage V (N 3 ) as the electric potential V (NW) of the N well. In this state, the voltage V (N 3 ) is equal to the second power-supply voltage VDD 2 . Thus, the electric potential V (NW) of the N well is also equal to the second power-supply voltage VDD 2 .

As the voltage V (N 3 ) exceeds the sum of the first power-supply voltage VDD 1 and the threshold voltage VthN, the NMOS transistor NM 6 C operates linearly. In this state, the first power-supply voltage VDD 1 is supplied to the node P 2 wired to the gate of the PMOS transistor PM 9 C, causing the PMOS transistor PM 9 C to enter an electrically conductive state, which outputs the voltage V (N 3 ) as the electric potential V (NW) of the N well. In this state, the voltage V (N 3 ) is equal to the second power-supply voltage VDD 2 . Thus, the electric potential V (NW) of the N well is also equal to the second power-supply voltage VDD 2 .

It is to be noted that since the effects of the first voltage-drop unit 91 and the second voltage-drop unit 92 are the same as those for the first embodiment 9A and the second embodiment 9B, their descriptions are not repeated. A voltage drop caused by the first voltage-drop unit 91 exhibits an effect that, for a voltage V (N 3 ) equal to or larger than the sum of the first power-supply voltage VDD 1 and the threshold voltage VthN, the voltage V (P 2 ) is set at a voltage level obtained as a result of subtracting the voltage from the first power-supply voltage VDD 1 as indicated by lines (II) shown in FIG. 13 , whereas a voltage drop caused by the second voltage-drop unit 92 exhibits an effect that the voltage V (P 2 ) is set at a voltage level, which is obtained as a result of subtracting the voltage from the first power-supply voltage VDD 1 to result in a difference and further subtracting the threshold voltage VthN from the resulting difference as indicated by lines (I) shown in FIG. 13 .

As described above, in accordance with the first embodiment 9A shown in FIG. 9 , the second embodiment 9B shown in FIG. 10 or the third embodiment 9C shown in FIG. 12 , by employing the first voltage-drop unit 91 , a voltage drop from a voltage appearing at the source of the NMOS transistor NM 6 A, NM 6 B or NM 6 C can be generated.

By employing the second voltage-drop unit 92 , the predetermined voltage applied to the gate the NMOS transistor NM 6 A, NM 6 B or NM 6 C can be dropped from the first power-supply voltage VDD 1 so that the level of the voltage appearing at the source of the NMOS transistor NM 6 A, NM 6 B or NM 6 C operating in a saturated region can be reduced.

By employing the first voltage-drop unit 91 and the second voltage-drop unit 92 , the voltages supplied to the nodes P 1 and P 2 can be reduced to a level obtained as a result of subtracting the threshold voltage VthN and the voltage drops from the first power-supply voltage VDD 1 . In addition, since the first voltage-drop unit 91 results in a fixed voltage drop, also in a region where the NMOS transistor NM 6 A, NM 6 B or NM 6 C operates linearly, a predetermined voltage drop can be resulted in.

By employing both the first voltage-drop unit 91 and the second voltage-drop unit 92 , the voltage drops are added to each other to effectively lower the voltages V (P 1 ) and V (P 2 ), which appear at the nodes P 1 and P 2 wired to the gates of the PMOS transistor PM 8 A (or PM 8 B) and the PMOS transistor PM 9 C respectively with the PMOS transistor PM 8 A, PM 8 B or PM 9 C put in an electrically conductive state. The first voltage-drop unit 91 is capable of exhibiting the same effect without regard to whether the first voltage-drop unit 91 is employed alone or used in conjunction with the second voltage-drop unit 92 . By the same token, the second voltage-drop unit 92 is capable of exhibiting the same effect without regard to whether the second voltage-drop unit 92 is employed alone or used in conjunction with the first voltage-drop unit 91 .

The electric potential V (NW) of the N well NW for each of the PMOS transistor PM 1 (or PM 3 ) and the PMOS transistors PM 5 to PM 7 is controlled in accordance with the voltage V (N 3 ) (or V (N 4 )) applied to the node N 3 (or N 4 ) over a seamless range of the voltage V (N 3 ) (or V (N 4 )) resulting in no floating state. To be more specific, for V (N 3 ) (or V (N 4 ))<(VDD 1 +VthP), the electric potential V (NW) is biased to the first power-supply voltage VDD 1 and, for V (N 3 ) (or V (N 4 ))≧(VDD 1 +VthP), the electric potential V (NW) is biased to the voltage V (N 3 ) (or V (N 4 )). Thus, the N well NW never enters a floating state. In addition, a forward bias is also never applied between junctions with drains. As a result, the electric potential V (NW) of the N well NW is set with a high certainly in level conversion from the level of the first circuit group 3 to that of the second circuit group 5 , and no unnecessary forward bias current flows. Accordingly, a stable circuit operation can be implemented with low current consumption.

FIG. 14 is a diagram showing a concrete typical embodiment implementing the low-side level conversion circuit 6 employed in the level conversion circuit 1 implemented by the embodiment described above. The low-side level conversion circuit 6 converts the level of the input signal IN having an amplitude equal to the first power-supply voltage VDD 1 into a signal having an amplitude equal to the bias voltage VB.

The input signal IN is supplied to an inverter gate comprising a PMOS transistor PM 62 and an NMOS transistor NM 62 and also supplied to the gate of an NMOS transistor NM 61 . The output terminal of the inverter gate is connected to the gate of an NMOS transistor NM 63 . The sources of the NMOS transistors NM 61 and NM 63 are connected to the line of the reference voltage VSS whereas the drains of the NMOS transistors NM 61 and NM 63 are connected to the drains of PMOS transistors PM 61 and PM 63 respectively. The gate of the PMOS transistor PM 61 is connected to the drain of the PMOS transistor PM 63 while the gate of the PMOS transistor PM 63 is connected to the drain of the PMOS transistor PM 61 . The sources of the PMOS transistors PM 61 and PM 63 are connected to the bias voltage VB through a voltage-drop unit 71 if necessary. A signal obtained as a result of the level conversion is output from a connection point between the PMOS transistor PM 63 and the NMOS transistor NM 63 .

An input signal IN set at a high level is received, putting the NMOS transistor NM 61 in an electrically conductive state. The voltage appearing at the gate of the PMOS transistor PM 63 is brought to the level of the reference voltage VSS, causing the PMOS transistor PM 63 to enter an electrically conductive state. In addition, a low-level signal obtained as a result of inversion by the inverter gate is supplied to the gate of the NMOS transistor NM 63 , putting the NMOS transistor NM 63 in an electrically non-conductive state. Thus, the bias voltage VB or a voltage lower than the bias voltage VB is output to the connection point by way of the PMOS transistor PM 63 as an output signal. The output signal is also supplied to the gate of the PMOS transistor PM 61 , causing the PMOS transistor PM 61 to enter an electrically non-conductive state.

Now, assume that the received input signal IN is set at a low level of the reference voltage VSS. In this case, the NMOS transistor NM 61 is put in an electrically non-conductive state, cutting off an electrical path from the gate of the PMOS transistor PM 63 to the line of the reference voltage VSS. On the other hand, a high-level signal obtained as a result of inversion by the inverter gate is supplied to the gate of the NMOS transistor NM 63 , putting the NMOS transistor NM 63 in an electrically conductive state. Thus, the reference voltage VSS is output to the connection point mentioned above by way of the NMOS transistor NM 63 as an output signal. The output signal is also supplied to the gate of the PMOS transistor PM 61 , causing the PMOS transistor PM 61 to enter an electrically conductive state and sustaining the PMOS transistor PM 63 in an electrically non-conductive state.

As described above, the high level of the output signal is the level of the bias voltage VB or a voltage lower than the bias voltage VB by the voltage drop. By setting this level at a level higher than the first power-supply voltage VDD 1 , the gate of the NMOS transistor NM 51 is deeply biased, leading to an expectation of an increased driving power and a raised operation speed.

In accordance with the present invention, when a signal is subjected to interfacing between a first circuit group operating at a first power-supply voltage and a second circuit group operating at a second power-supply voltage higher than the first power-supply voltage, by providing a level conversion circuit operating by being driven by a power supply having a voltage level between the first power-supply voltage and the second power-supply voltage, a semiconductor device capable of converting a voltage level without continuous current consumption can be provided.