PLL loop filter capacitor test circuit and method for on chip testing of analog leakage of a circuit

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1. Field of the Invention

This invention relates to analog circuit tests, and particularly to circuits within a tested circuit for testing the tested analog circuit using a digital tester.

2. Description of Background

Before our invention external analog testers were used by IBM to test existing PLL designs which are sensitive to the characteristics of the loop filters. Most are sensitive to the leakage in the capacitors of that filter.

Prior solutions require using a dedicated analog test I/O, perhaps with an analog multiplexer to select which analog function is to be tested through a shared pin. As technology has progressed, it has become increasingly difficult to design such a solution. The additional leakage introduced by an analog multiplexer can disrupt the circuit activities. Adding a dedicated analog test I/O can introduce noise into the circuit. In addition, most manufacturing test instrumentation is not equipped to measure small analog values.

The shortcomings of the prior art are overcome and additional advantages are provided through the provision of a test circuit within an existing design to enable the test circuit to test directly within the circuit. The solution enables an analog test of a chip using a digital tester. This invention provides a way to test and measure the leakage of the PLL loop filter capacitor leakage during test with a simple digital tester using existing pins.

Our invention performs the analog test directly within the circuit, sending a digital signal to a standard digital test process. In this manner, tests can be performed during manufacturing test with only standard testing.

While this is described as a solution for PLL loop filter capacitor leakage measurements, it can be used to measure capacitor leakage generally.

Additional features and advantages are realized through the techniques of the present invention. The embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with advantages and features, refer to the description and to the drawings.

The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:

FIG. 1 illustrates one example of a simplified schematic diagram of the invention

FIG. 2 illustrates one example of a detailed schematic of our implementation of the preferred embodiment having an added test circuit.

FIG. 3 illustrates one example of a schematic for the differential amplifier.

FIG. 4 illustrates results of a circuit simulation.

The detailed description explains the preferred embodiments of the invention, together with advantages and features, by way of example with reference to the drawings.

As shown in FIG. 1 , there are two capacitors to be tested. These capacitors are labeled Cfilt and Cfiltn and coupled to ground. Other connections to the capacitors are assumed and assumed to be disabled during testing and so are not shown.

To start a test, bring the enab_signal low. This causes the weak PFETs (three are shown as P 1 , P 2 , P 3 , with P 1 , P 2 as examples of a plurality of possible PFETs, while P 3 is provided with a coupling to reference resistor Rref) connected to their coupled capacitor to try to charge up the capacitor.

Thus if weak PFET P 1 will charge Capacitor Cfilt and PFET P 2 will charge Capacitor Cfiltn. If the capacitor is ideal, it will charge up to the supply voltage. The more leakage the capacitor has, the lower the voltage that will be generated. At the same time, PFET P 3 will apply a voltage to the reference resistor R ref. This resistor models the equivalent leakage resistance that is acceptable. The transistor P 3 driving the resistor Rref is 40× larger than the ones (P 1 , P 2 ) driving the capacitors. This allows the reference resistor R ref to be 40× smaller in value. This is necessary as the acceptable leakage resistances are very large, in excess of 1 MegOhm. Without this multiplication, the reference resistor R ref would be impracticably large.

These voltages are compared using a differential amplifier circuit. The voltage from PFET P 1 is compared to the voltage on reference resistor R ref by respective inputs to the differential amplifier 105 , while the voltage from PFET P 2 is compared to the voltage on reference resistor R ref by respective inputs to the differential amplifier 106 . This output can then be used to drive standard digital output pins, leak-filt and leak-filtn respectively, for testing input to enable a way to test and measure the leakage of the PLL loop filter capacitor leakage during test with a simple digital tester using existing pins coupled to output pins leak-filt and leak-filtn.

A detailed schematic of our implementation is shown in FIG. 2 .

The capacitors are not shown in this schematic as this schematic is for the additions to the existing circuit. The plurality of capacitors, one for each transistor as shown in FIG. 1 , are connected to the ports labeled filt and filtn on this schematic. Instead of a single transistor, multiple transistors are used and coupled in series as schematically illustrated in FIG. 2 in accordance with the preferred embodiment. The multiple transistors are illustrated as P 1 a , P 1 b , P 1 c and P 1 d for the first differential amplifier 105 set, while P 2 a , P 2 b , P 2 c and P 2 d are coupled to the second differential amplifier 106 of the differential amplifier circuit. This ensures that the manufacturing tolerances are small enough on these weak devices. Additional transistors are added, but are shorted out, to allow for an easy circuit tuning with a Release Interface Tape B Mask (RIT-B) circuit tuning tool.

A similar structure is used for the reference resistor R ref. The resistor R ref 104 is broken into several series resistors due to its size. Additional transistors and resistors are supplied, with their terminals shorted out, to allow for RIT-B circuit tuning.

The schematic for each of the differential amplifiers 105 , 106 is shown in FIG. 3 . FIG. 3 represents a CMOS differential amplifier generally conventionally coupled; however, the top transistor is connected to the enable line enab_to allow it to be turned off as well. The transistor N 0 108 ensures a suitable output is present, even when the amplifier is disabled. The amplifier in FIG. 3 has two inverters in series on the output. In FIG. 4 , the dot dash dot line 401 (which could be yellow line with a colored drawing) is the input to the first inverter. The large dot line 402 (which is a colored drawing could be a red line) is the output from the first inverter and the input to the second. The small dotted line 403 (which in a colored drawing could be a tan line) is the output of the second inverter.

To test the structure of the invention, we simulated the circuit under varying conditions of assumed capacitor oxide thickness. It is well known that the leakage of a capacitor has an exponential dependence on the oxide thickness. The results of this simulation are shown in FIG. 4 below.

Here, in FIG. 4 , the X axis represents oxide thickness in the capacitor, and the Y axis represents voltages at various points. The voltage on one of the capacitors is shown as a solid line 404 (which with a colored drawing could be green), the long dashed line 405 (which with a colored drawing could be purple) represents the reference voltage generated. The short dashed 406 (which with a colored drawing could be blue line) and dot dashed dot 401 (which with a colored drawing could beyellow) lines represent the voltage within the differential amplifier, while the large dotted line 402 (which with a colored drawing could be red) is the output of the first inverter, and the small dotted line 403 is the final output of the second inverter.

In the test case, the reference voltage is set to indicate acceptable leakage at 21 A of oxide. This is adjustable and could be adjusted by changing the reference resistor value.

While the preferred embodiment to the invention has been described above and particularly in the claims themselves, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.