Operational transconductance amplifier with DC offset elimination and low mismatch

This application claims the priority of Korean Patent Application No. 2003-97756, filed on Dec. 26, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

1. Field of the Invention

The present invention relates to a transconductor, and more particularly, to a transconductor, of which direct current (CD) offset component is cancelled and a mismatch characteristic is improved.

2. Description of the Related Art

An operational transconductance amplifier (OTA) is a current amplifier that amplifies an applied input voltage and outputs the input voltage as an output voltage in proportion to a transconductance (Gm). In a case where the OTA is applied in a communication system of direct conversion type, a signal of high frequency is converted into baseband signal based on a direct current (DC), and a DC offset largely affects the performances of the system. The DC offset degrades a restoration function of the signal, and causes a wrong operation of the system since it makes an operational point of next stage be a saturation status. Generally, the DC offset may be generated by frequency conversion that is caused by a local oscillator (LO) signal leakage or an interferer leakage such as a time-variant DC-offset, or generated by a non-linear mixer or an asymmetric circuit such as a time-invariant DC-offset.

A low pass filter that is located at a rear end of a receive system in the entire system is largely affected by the DC-offset. Therefore, in order to satisfy a desired bit error ratio (BER), the DC-offset should be eliminated and a clean signal should be transmitted to a final analog/digital converter (ADC). Especially, in a case where the low pass filter is formed of active circuits of the OTA and a capacitor, each of OTA cells should have a performance of eliminating the DC offset so that a DC value of respective node does not become the saturation status, but maintains at a predetermined voltage value even when the DC offset is generated at the previous node.

In a differential circuit structure, a mismatch characteristic may make a signal non-linear, and generate an internal DC offset. Thus, the DC value of output signal can be differentiated, and accordingly, the mismatch of the signal at the next node becomes worse. Therefore, the BER of the entire system may be degraded.

In a superheterodyne system that is conventionally used, the DC offset is small, thus there is no need to use a filter eliminating the DC offset. However, in the direct conversion system for realizing a system on chip (SOC) of lower power consumption, a circuit design for solving the DC offset problem is required.

FIG. 1 is a circuit diagram showing a conventional triode-typed transconductor. In addition, FIG. 2 is a circuit diagram showing a common mode control circuit of FIG. 1 in detail.

Referring to FIG. 1 , the conventional transconductor includes triode-typed transconductors M 1 a , M 1 b , M 1 c , and M 1 d having a dual-pair input vpi 1 , vmi 1 , vpi 2 , and vmi 2 structure, and a gain boosting amplifier. The gain boosting amplifier includes transistors M 2 a and M 2 b , and an amplifier A 1 . Transistors M 3 a , M 3 b , M 4 a , and M 4 b are loads to supply predetermined electric currents, and an amplifier A 2 increases output resistance in connection with the transistors M 3 a and M 3 b . In addition, an amplifier Am that is a common mode control circuit compares a constant output voltage and a sub-output voltage to a common mode voltage Vcm to control the electric currents of the transconductors M 1 a , M 1 b , M 1 c , and M 1 d through the transistors M 4 a and M 4 b so that the two output voltages are corresponded to the common mode voltage Vcm.

Referring to FIG. 2 , the amplifier Acm, that is, the common mode control circuit includes transistors M 100 , M 101 , M 102 , M 103 , M 104 , M 105 , M 106 , M 107 , and M 108 . The transistors M 100 and M 101 generate electric current of a predetermined magnitude by mirroring a current source of a bias circuit. The transistors M 102 and M 103 and the transistors M 104 and M 105 form differential pair amplifiers, respectively. The transistors M 106 and M 108 perform as loads. The transistor M 107 includes a diode connection to transmit the current generated by the transistors M 100 and M 101 and supply the fixed current to a core of the transconductor. Two output voltages vo+ and vo− of the transconductor are compared to the common mode voltage Vcm through two differential pair amplifiers M 102 and M 103 , and M 104 and M 105 , respectively. The differences of compared voltages is amplified and added to form a gate voltage VMFB of the transistor M 107 . The gate voltage CMFB is a DC component value without an alternating current (AC) component, and the DC component value is inverted and amplified through the transistors M 4 a and M 4 b shown in FIG. 1 so that the output DC value can be corresponded to the common mode voltage Vcm.

However, in the above case, although the output voltage can be maintained constantly, the DC offset generated in the input voltages vpi 1 , vmi 1 , vpi 2 , and vmi 2 cannot be eliminated. In addition, in a case where a mismatch in the output voltage is generated due to a change of device size after performing processes, the mismatch cannot be eliminated. Since the filter generally has a structure, in which a plurality of transconductors are connected in parallel and serial to each other, if the output DC voltage of first transconductor, that is, the input DC value of the next transconductor, is not coincided with the output DC voltage of the next transconductor, the filter performs a wrong operation and makes the next circuit saturated.

The present invention provides an operational transconductance amplifier (OTA) capable of eliminating an input DC offset and compensating a mismatch of a signal so that an output DC value can be fixed with maintaining a linear range and a large output resistance value of a conventional transconductor.

According to an aspect of the present invention, there is provided a transconductor including a common mode control DC offset elimination circuit receiving input/output voltages to stabilize current supplying and output DC value constantly, and a first differential amplifier and a second differential amplifier reducing a mismatch in a transconductor circuit and increasing an output resistance in order to prevent a DC voltage applied to input/output nodes from being saturated or a circuit from wrongly operating due to a DC offset or a mismatch of the circuit.

The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:

FIG. 1 is a circuit diagram showing a conventional triode-typed transconductor;

FIG. 2 is a circuit diagram showing a common mode control circuit shown in FIG. 1 in detail;

FIG. 3 is a view showing a transconductor according to the present invention;

FIG. 4 is a circuit diagram showing the transconductor of FIG. 3 in more detail;

FIG. 5 is a circuit diagram showing internal circuit of a DC offset elimination circuit and internal circuits of an inversion amplifier of the transconductor circuit in the transconductor of FIG. 3 ;

FIG. 6 is a circuit diagram showing the DC offset elimination circuit shown in FIG. 5 in detail;

FIG. 7 is a circuit diagram showing a first inversion amplifier shown in FIG. 5 in detail;

FIG. 8 is a circuit diagrams showing a second inversion amplifier shown in FIG. 5 in detail; and

FIG. 9 is a graph showing a change of output voltages according to the DC offset in the transconductor according to the present invention.

FIG. 3 is a circuit diagram showing a transconductor according to the present invention.

Referring to FIG. 3 , the transconductor of the present invention includes a transconductor circuit 300 and a direct current (DC) offset elimination circuit 400 . The transconductor circuit 300 converts input voltages vpi 1 , vmi 1 , vpi 2 , and vmi 2 so that the input voltages are in proportion to a transconductance gm, and outputs output voltages vo+ and vo−. The DC offset elimination circuit 400 receives the dual-pair inputs vpi 1 , vmi 1 , vpi 2 , and vmi 2 , the constant output vo+, and the sub-output vo− to generate DC offset elimination voltage. The DC offset elimination voltage is input into the transconductor circuit 300 so that the affects of the DC offset in the transconductor circuit 300 can be eliminated.

FIG. 4 is a circuit diagram showing the transconductor of FIG. 3 in more detail.

Referring to FIG. 4 , the transconductor circuit 300 of FIG. 3 includes input transistors M 1 a , M 1 b , M 1 c , and M 1 d having dual-pair vpi 1 , vmi 1 , vpi 2 , and vmi 2 input structures. The input transistors M 1 a , M 1 b , M 1 c , and M 1 d are n-channel type MOS transistors. The transistors M 2 a and M 2 b and a first inversion amplifier A 11 receive core node voltages V×a and V×b of the input transistors M 1 a , M 1 b , M 1 c , and M 1 d and control drain-source voltages of the input transistors M 1 a , M 1 b , M 1 c , and M 1 d so as to be changed as a function of a predetermined transconductance changing voltage Vc, so that the input transistors M 1 a , M 1 b , M 1 c , and M 1 d can operate in the triode region. Transistors M 2 a and M 2 b are n-channel MOS transistors. Transistors M 3 a and M 3 b , and a second inversion amplifier A 22 increase an output resistance. Transistors M 4 a and M 4 b supplies the electric current input from the DC offset elimination circuit 400 by mirroring the current. The transistors M 3 a , M 3 b , M 4 a , and M 4 b are p-channel MOS transistors.

FIG. 5 is a circuit diagram showing an internal circuit of the DC offset elimination circuit and internal circuits of the inversion amplifiers of the transconductor circuit. In addition, FIGS. 6 through 8 are circuit diagrams showing the DC offset elimination circuit 400 , the first inversion amplifier A 11 , and the second inversion amplifier A 22 of FIG. 5 , respectively.

Referring to FIG. 6 , the DC offset elimination circuit 400 includes a current generation circuit 410 having transistors M 10 , M 11 , M 12 , M 13 , M 14 , and M 15 and the amplifier A 11 , a common mode feedback circuit 420 having two differential amplifiers M 16 and M 17 , and M 18 and M 19 , and a load circuit 430 including transistors M 20 , M 21 , and M 22 . Especially, the transistor M 21 performs a function of current mirror.

The current generation circuit 410 generates the current If flowing on the transconductor circuit 300 . The transistors M 10 , M 11 , M 12 , and M 13 operate in the triode region, and receive the dual-pair input voltages vpi 1 , vmi 1 , vpi 2 , and vmi 2 with the transconductor circuit 300 and generate common current If corresponding to the input voltages vpi 1 , vmi 1 , vpi 2 , and vmi 2 . That is, the common current If is a function of the input voltages vpi 1 , vmi 1 , vpi 2 , and vmi 2 . In order for the transistors M 10 , M 11 , M 12 , and M 13 to operate in the triode region, the transistors M 14 and M 15 and the amplifier A 11 maintain the drain-source voltage Vds of the transistors M 10 , M 11 , M 12 , and M 13 to be smaller than a difference between the gate-source voltage and a threshold voltage (V GS −Vth) like the transistors M 2 a and M 2 b (refer to FIG. 4 ) and the amplifier A 11 (refer to FIG. 4 ). The differential amplifiers M 16 and M 17 , and M 18 and M 19 of the common mode feedback circuit 420 receive two output voltages and common mode voltage (vo− and Vcm), and (vo+ and Vcm) respectively to stabilize the output voltages vo+ and vo−.

The transistors M 4 a and M 4 b generate the current flowing on the transconductor circuit 300 by mirroring the current If flowing on the transistor M 21 . Here, the current flowing on the CD offset elimination circuit should be lowered in a current ratio of 10 times lower than the current If so that the transistors M 3 a and M 3 b are not exceed from a saturated region. Therefore, a ratio between areas of the transistors M 3 a and M 3 b and the transistor M 21 is the same as the current ratio. In the conventional art, the current flowing on the common mode control circuit Acm shown in FIG. 2 is a constant current controlled by a bias circuit, however, the current generated by the DC offset elimination circuit 400 is changed according to the input voltages. Accordingly, the DC offset elimination circuit 400 controls the output voltages vo+ and vo− of the transconductor circuit ( 300 in FIG. 4 ) so as to be coincided with the common mode voltage Vcm by comparing the output voltages to the common mode voltage Vcm like in the conventional art, however, the DC offset elimination circuit 400 of the present invention makes the current that is changed according to the input voltages flow on the transconductor circuit, thus the DC values of the output voltages vo+ and vo− can be coincided with the common mode voltage Vcm even if the DC offset is generated.

Referring to FIG. 7 , the first inversion amplifier A 11 receive drain voltages of the input transistors M 1 a , M 1 b , M 1 c , and M 1 d to make the input transistors M 1 a , M 1 b , M 1 c , and M 1 d operate in the triode region. The first inversion amplifier A 11 includes transistors M 30 and M 31 performing as resistances and current paths, a transistor M 32 as a current source, transistors M 33 , M 34 , M 35 , and M 36 forming the inversion amplifier, and load transistors M 37 , M 38 , M 39 , M 40 , M 41 , M 42 , M 43 , and M 44 .

The transistors M 30 , M 31 , M 32 , M 33 , M 34 , M 35 , and M 36 are n-channel type MOS transistors, and the transistors M 37 , M 38 , M 39 , M 40 , M 41 , M 42 , M 43 , and M 44 are p-channel type MOS transistors. The transistors M 30 and M 31 operate in the triode region, and the transistors M 33 and M 34 receive node voltages sharing the node with the drains of the transistors M 30 and M 31 . The transistors M 35 and M 36 receive the signal that is input into the sources of the transistors M 33 and M 34 and amplified at the common gate through the gate thereof. In addition, the signal that is inversely amplified by the transistors M 35 and M 36 is applied to the gate of the transistors M 2 a and M 2 b (refer to FIG. 4 ).

The transistors M 33 , M 34 , M 35 , and M 36 output the output voltages V 1 a and V 1 b that are made by amplifying the input voltages V×a and V×b thereto. The first inversion amplifier A 11 controls the drain-source voltages of the transistors into the function of the transconductance changing voltage Vc in combination with the transistors M 2 a and M 2 b of FIG. 4 or the transistors M 14 and M 15 of FIG. 6 so that the input transistors M 1 a , M 1 b , M 1 c , and M 1 d of FIG. 4 or the transistors M 10 , M 11 , M 12 , and M 13 of FIG. 6 can operate in the triode region. Here, the transconductance changing voltage Vc is the DC voltage that increases/reduces the transconductance value gm of the transconductor proportionally, and is supplied from an external tuning circuit. As described above, when the amplifier A 11 is used, the circuit operation is not affected by the low values of the input voltages V×a and V×b, and the mismatch between the input voltages V×a and V×b caused by the change of areas after the processes can be compensated by differentially amplifying the input voltages V×a and V×b of both nodes in the transconductor circuit 300 .

Referring to FIG. 8 , the second inversion amplifier A 22 increases the output resistance in combination with the transistors M 3 a and M 3 b of the transconductor circuit 300 . The second inversion amplifier A 22 includes transistors M 50 , M 51 , and M 52 as current sources, transistors M 53 , M 54 , M 55 , and M 56 forming the differential amplifiers, and load transistors M 57 and M 58 . The transistor pairs M 55 and M 53 , and M 56 and M 54 are formed of source follower circuits, and accordingly, the transistors M 55 and M 56 buffer the drain voltages of the transistors M 4 a and M 4 b in the transconductor circuit 300 from the gate to the source, and the transistors M 53 and M 54 differentially amplify the buffered voltages and transmit the amplified voltages to the gates of the transistors M 3 a and M 3 b in the transconductor circuit 300 . Since the second inversion amplifier A 22 also has the differential structure receiving the input voltages V×a and V×b at the both nodes of the transconductor circuit 300 like the first inversion amplifier A 11 , the mismatch can be compensated. In addition, the transistors M 50 , M 51 , M 52 , M 53 , M 54 , M 55 , and M 56 are the n-channel type MOS transistors, and the transistors M 57 and M 58 are p-channel type MOS transistors.

FIG. 9 is a graph showing a change of output voltage according to the DC offset in the transconductor according to the present invention.

As shown in FIG. 9 , according to the conventional transconductor without the DC offset elimination circuit (the line denoted by reference numeral 910 in FIG. 9 ), the output voltage is rapidly changed due to the DC offset, however, according to the transconductor of the present invention (the line denoted by reference numeral 920 in FIG. 9 ), the constant output voltage can be maintained even when the DC offset is generated, and accordingly, it can be recognized that the DC offset is eliminated by the DC offset circuit.

As described above, in the transconductor according to the present invention, the mismatch output voltage and the DC offset voltage/current can be eliminated at low voltage environment while maintaining the linear range and larger output resistance value using a simple circuit configuration, thus the voltages of respective nodes can be stabilized in a case where a plurality of transconductors are connected in parallel/serial such as a filter, and accordingly, the stability of the entire communication system.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims.