Two light level ballast

The present invention relates to the general subject of circuits for powering discharge lamps. More particularly, the present invention relates to an electronic ballast that provides two light levels.

Two light level lighting systems have been utilized in overhead lighting for many years. Typically, two light level systems are implemented by using two power switches and two ballasts in each lighting fixture, wherein each of the power switches controls only one of the ballasts in the fixture. Turning on both of the switches at the same time powers both ballasts, thus producing full light output from the fixture. Turning on only one of the switches applies power to only one of the ballasts in the lighting fixture and results in a reduced light level and a corresponding reduction in power consumed.

Because it is more economical to have a single ballast in the fixture instead of two, a system for producing the same result using only a single ballast is desirable. For compatibility purposes, the ballast would be required to operate from the same two power switches used in the two ballast system. When both switches are closed, the ballast would operate in a full light mode. Conversely, when only one of the two power switches is closed, the ballast would operate in a reduced light mode.

Two light level systems that require only a single ballast are known in the art. For example, U.S. Pat. No. 5,831,395 (issued to Mortimer) discloses one such system, which is described in FIG. 1 . As shown in FIG. 1 , the Mortimer system includes a detector circuit 270 that provides a control signal that is dependent on the states of two on-off switches S 1 and S 2 . Theoretically, when only one of the switches S 1 ,S 2 is on, the control signal will be at a first level, causing the ballast to drive the lamp at a reduced light level; when both of the switches S 1 ,S 2 are on, the control signal will be at a second level, causing the ballast to drive the lamp at a higher light level.

Unfortunately, the Mortimer system has a major limitation in that detector circuit 270 may not function properly in the presence of X capacitances that are typically present between the hot and neutral wires that connect the ballast to the switches S 1 ,S 2 and the AC source. These X capacitances (denoted by dashed line/phantom capacitor symbols in FIG. 1 ) are present due to EMI circuitry in the ballast and/or the nature and length of the wiring between the AC source, switches S 1 ,S 2 , and the ballast. Essentially, these X capacitances compromise the ability of detector circuit 270 to distinguish between a condition where only one switch is closed versus a condition where both switches are closed, and thus defeat the intended functionality of a two light level approach. This problem is particularly pronounced when multiple ballasts are connected to the same branch circuit, in which case the X capacitances due to the EMI circuitry in each ballast, and/or the wiring between the AC source, switches S 1 ,S 2 , and each ballast, are additive.

What is needed, therefore, is a ballast that provides two light levels but that is substantially insensitive to the capacitances that are typically present in actual lighting installations. Such a ballast would represent a significant advance over the prior art.

FIG. 1 is a schematic diagram of a two light level ballast, in accordance with the prior art.

FIG. 2 is a schematic diagram of a two light level ballast, in accordance with a preferred embodiment of the present invention.

FIG. 2 describes a preferred structure for a ballast 100 for powering at least one gas discharge lamp 30 from an alternating current (AC) voltage source 20 . Ballast 100 comprises a plurality of input connections 102 , 104 , 106 , a full-wave rectifier circuit 120 , electromagnetic interference (EMI) inductors L 1 ,L 2 ,L 3 , a detector circuit 200 , power factor correction (PFC) and inverter circuits 300 , and output connections 108 , 110 for coupling to at least one discharge lamp 30 .

The plurality of input connections includes a first hot input connection 102 , a second hot input connection 104 , and a neutral input connection 106 . First hot input connection 102 is adapted for coupling to a hot wire 22 of AC source 20 via a first on-off switch S 1 , while second hot input connection 104 is adapted for coupling to the hot wire 22 of AC source 20 via a second on-off switch S 2 . Switches S 1 and S 2 are typically implemented by conventional wall switches having an on state and an off state. Neutral input connection 106 is adapted for coupling to a neutral wire 24 of AC source 20 .

Full-wave rectifier circuit 120 is coupled to first hot input connection 102 via first EMI inductor L 1 , to second input connection 104 via second EMI inductor L 2 , and to neutral input connection 106 via third EMI inductor.

Detector circuit 200 is coupled to first and second hot input connections 102 , 104 via first and second EMI inductors L 1 ,L 2 . During operation, detector circuit 200 provides an output voltage, V OUT , having a magnitude that is dependent on the states of switches S 1 ,S 2 , but that is substantially unaffected by typical X capacitances being present between the hot input connections 102 , 104 and the neutral input connection 106 .

Detector circuit 200 operates as follows. When both switches S 1 and S 2 are in the on state, the magnitude of V OUT is at a first level (e.g., 0 volts), causing the ballast (via PFC and inverter circuits 300 ) to operate lamp 30 at a first light level (e.g., 100% of full light output). When only one of the switches S 1 and S 2 is in the on state, the magnitude of V OUT is at a second level (e.g., 8 volts), causing the ballast to operate lamp 30 at a second light level (e.g., 50% of full light output).

PFC and inverter circuits 300 may be realized by any of a number of arrangements that are well known to those skilled in the art, and thus will not be described in any further detail herein. For example, PFC and inverter circuit 300 may be implemented using a boost converter followed by a driven series resonant half-bridge inverter. For purposes of the present invention, it is required only that PFC and inverter circuit 300 are capable of responding to the output, V OUT , of detector circuit 200 in the manner previously described. More specifically, PFC and inverter circuits 300 should power lamp 30 at the first light level (e.g., 100% of full light output) when V OUT is at the first level (e.g., zero volts), and at the second light level (e.g., 50% of full light output) when V OUT is at the second level (e.g., 8 volts).

Preferably, as shown in FIG. 2 , full-wave rectifier circuit 120 is implemented by an arrangement comprising six diodes D 1 ,D 2 ,D 3 ,D 4 ,D 5 ,D 6 . First diode D 1 has an anode coupled to a first node 122 and a cathode coupled to a second node 124 ; first node 122 is coupled to first hot input connection 102 via first EMI inductor L 1 . Second diode D 2 has an anode coupled to a third node 126 and a cathode coupled to first node 122 ; third node is coupled to circuit ground 60 . Third diode D 3 has an anode coupled to a fourth node 128 and a cathode coupled to second node 124 ; fourth node 128 is coupled to second hot input connection 104 via second EMI inductor L 2 . Fourth diode D 4 has an anode coupled to third node 126 and a cathode coupled to fourth node 128 . Fifth diode D 5 has an anode coupled to a fifth node 130 and a cathode coupled to second node 124 ; fifth node 130 is coupled to neutral input connection 106 via third EMI inductor L 3 . Sixth diode D 6 has an anode coupled to third node 126 and a cathode coupled to fifth node 130 . During operation, rectifier circuit 120 receives the sinusoidal AC voltage provided by AC source 20 and provides a full-wave rectified voltage to the PFC and inverter circuits 300 . Capacitor 140 serves as a high frequency bypass capacitor.

As described in FIG. 2 , first EMI inductor L 1 is coupled between first hot input connection 102 and first node 122 . Second EMI inductor L 2 is coupled between second hot input connection 104 and fourth node 128 . Third EMI inductor L 3 is coupled between neutral input connection 106 and fifth node 130 .

Preferably, as described in FIG. 2 , detector circuit 200 comprises a first input terminal 202 , a second input terminal 204 , first and second output terminals 206 , 208 , a first transistor Q 1 , a second transistor Q 2 , a third transistor Q 3 , a first resistor R 1 , a second resistor R 2 , a third resistor R 3 , a fourth resistor R 4 , a fifth resistor R 5 , a sixth resistor R 6 , a seventh resistor R 7 , a first capacitor C 1 , a second capacitor C 2 , and a third capacitor C 3 . First input terminal 202 is coupled to first node 122 and first hot input connection 102 . Second input terminal 204 is coupled to fourth node 128 and second hot input connection 104 . First and second output terminals 206 , 208 are coupled to PFC and inverter circuits 300 ; second output terminal 208 is coupled to circuit ground 60 . First transistor Q 1 is preferably implemented as a NPN type bipolar junction transistor having a base 202 , a collector 204 , and an emitter 206 . Second transistor Q 2 is preferably implemented as a NPN type bipolar junction transistor having a base 208 , a collector 210 , and an emitter 212 . Third transistor Q 3 is preferably implemented as a PNP type bipolar junction transistor having a base 214 , a collector 216 , and an emitter 218 . The collector 204 of first transistor Q 1 is coupled to the collector 210 of second transistor Q 2 . The emitter 206 of first transistor Q 1 is coupled to the base 208 of second transistor Q 2 . The emitter 212 of second transistor Q 2 is coupled to the base 202 of first transistor Q 1 . First resistor R 1 is coupled between first input terminal 202 and the base 208 of second transistor Q 2 . Second resistor R 2 is coupled between the base 208 of second transistor Q 2 and circuit ground 60 . First capacitor C 1 , which is present to provide noise suppression, is likewise coupled between the base 208 of second transistor Q 2 and circuit ground 60 . Third resistor R 3 is coupled between second input terminal 204 and the base 202 of first transistor Q 1 . Fourth resistor R 4 is coupled between the base 202 of first transistor Q 1 and circuit ground 60 . Second capacitor C 2 , which is present to provide noise suppression, is likewise coupled between the base 202 of first transistor Q 1 and circuit ground 60 . Third transistor Q 3 is preferably implemented as a PNP type bipolar junction transistor having a base 214 , a collector 216 , and an emitter 218 . The base 214 of transistor Q 3 is coupled to the collectors 204 , 210 of first and second transistors Q 1 ,Q 2 . The emitter 218 of third transistor Q 3 is coupled to a DC supply voltage (e.g., +18 volts). Fifth resistor R 5 is coupled between the base 214 and emitter 218 of third transistor Q 3 . Sixth resistor R 6 is coupled between the collector 216 of third transistor Q 3 and first output terminal 206 . Seventh resistor R 7 and third capacitor C 3 are each coupled between first and second output terminals 206 , 208 .

The detailed operation of ballast 100 and detector circuit 200 is now described with reference to FIG. 2 as follows. The four operating conditions of interest are: (i) S 1 and S 2 off; (b) S 1 and S 2 on; (c) S 1 on and S 2 off; and (d) S 1 off and S 2 on. In the following description, an X capacitance is assumed to be present between each of the hot input connections 102 , 104 and the neutral input connection 106 . The frequency of AC source 20 is assumed to be 60 hertz. Additionally, unless stated otherwise, all voltages should be understood to be referenced to circuit ground 60 .

(a) When both switches S 1 and S 2 are off, no power is applied to ballast 100 and lamp 30 is not illuminated.

(b) When both switches S 1 and S 2 are on, V OUT will be at the first level (e.g., zero volts) and lamp 30 will be illuminated at a full light level. This occurs as follows. During the positive half cycles of V AC , equal positive pulsating voltages (i.e., having the same magnitude and phase and being approximately equal to a positive half cycle of V AC ) will be present at both input terminals 202 , 204 of detector circuit 200 . Consequently, the base voltages at each transistor Q 1 ,Q 2 will be equal (due to the fact that R 1 ,R 3 have the same resistance, and R 2 ,R 4 have the same resistance). Because the base of each transistor Q 1 ,Q 2 is coupled to the emitter of the other transistors Q 2 ,Q 1 , the base-to-emitter voltage for each transistor Q 1 ,Q 2 will be zero, causing both transistors Q 1 ,Q 2 to be off. With both transistors Q 1 ,Q 2 off, Q 3 will likewise be off. As a result, V OUT will be zero. During the negative half cycles of V AC , the voltages at both input terminals 202 , 204 of detector circuit 200 will be zero. Consequently, the base voltages and base-to-emitter voltages for each transistor Q 1 ,Q 2 will be zero, causing both transistor Q 1 ,Q 2 to be off. With both transistors Q 1 ,Q 2 off, Q 3 will likewise be off, and V OUT will remain at zero. Thus, when both switches S 1 and S 2 are on, V OUT will be zero.

(c) When switch S 1 is on and switch S 2 is off, V OUT will be at the second level (e.g., 8 volts) and lamp 30 will be illuminated at a reduced light level. This occurs as follows. During the positive half cycles of V AC , a pulsating positive voltage (i.e., approximately equal to a positive half cycle of V AC ) will be present at first input terminal 202 and zero voltage will be present at second input terminal 204 . Consequently, the base-to-emitter voltage of Q 2 will be positive and the base-to-emitter voltage of Q 1 will be near zero. As a result, Q 2 will be on (once the voltage at input terminal 202 reaches a level sufficient to cause at least 0.6 volts to appear at the base-to-emitter junction of Q 2 ) and Q 1 will be off. With Q 2 on, the base 214 of Q 3 will be pulled low, causing Q 3 to turn on, resulting in the development of a positive voltage across output terminals 206 , 208 . Q 2 and Q 3 will remain on until the voltage at input terminal 202 falls below the aforementioned sufficient level, at which point Q 2 and Q 3 will turn off. Conversely, during the negative half cycles of V AC , a positive voltage will be present at second input terminal 204 and zero voltage will be present at first input terminal 202 . It should be appreciated that the positive voltage at second input terminal 204 during the negative half cycles of V AC occurs only because of the presence of an X capacitance (i.e., X 2 ) between second hot input connection 104 and neutral input connection 106 ; in the absence of the X capacitance, the voltage at second input terminal 204 would be zero during the negative half cycles of V AC . Consequently, the base-to-emitter voltage of Q 1 will be positive and the base-to-emitter voltage of Q 2 will be near zero. As a result, Q 1 will be on (once the voltage at input terminal 204 reaches a level sufficient to cause at least 0.6 volts to appear at the base-to-emitter junction of Q 1 ) and Q 2 will be off. With Q 1 on, the base 214 of Q 3 will be pulled low, causing Q 3 to turn on, resulting in the development of a positive voltage across output terminals 206 , 208 . Thus, over the positive and negative half cycles of V AC , Q 1 and Q 2 will alternately turn on and off over a portion of each half cycle, with the result that Q 3 will turn on and off at a 120 hertz rate and with a duty cycle of approximately 40% (i.e., Q 3 will be on 40% of the time, and off the remaining 60% of the time). Due to the filtering action of capacitor C 3 , V OUT will be at the second level (e.g., 8 volts), causing lamp 30 to be illuminated at a reduced light level (e.g., 50% of full light output).

(d) When switch S 1 is off and switch S 2 is on, V OUT will be the same as when S 1 is on and S 2 is off (i.e., VOUT will be at the second level and lamp 30 will be illuminated at a reduced light level). During the positive half cycles of V AC , a pulsating positive voltage (i.e., approximately equal to a positive half cycle of V AC ) will be present at second input terminal 204 and zero voltage will be present at first input terminal 202 . Consequently, the base-to-emitter voltage of Q 1 will be positive and the base-to-emitter voltage of Q 2 will be zero. As a result, Q 1 will be on (once the voltage at input terminal 204 reaches a level sufficient to cause at least 0.6 volts to appear at the base-to-emitter junction of Q 1 ) and Q 2 will be off. With Q 1 on, the base 214 of Q 3 will be pulled low, causing Q 3 to turn on, resulting in the development of a positive voltage across output terminals 206 , 208 . Conversely, during the negative half cycles of V AC , a positive voltage will be present at first input terminal 202 and zero voltage will be present at second input terminal 204 . It should be appreciated that the positive voltage at first input terminal 202 during the negative half cycles of V AC occurs only because of the presence of an X capacitance (i.e., X 1 ) between first hot input connection 102 and neutral input connection 106 ; in the absence of the X capacitance, the voltage at first input terminal 202 would be zero during the negative half cycles of V AC . Consequently, the base-to-emitter voltage of Q 2 will be positive and the base-to-emitter voltage of Q 1 will be near zero. As a result, Q 2 will be on (once the voltage at input terminal 202 reaches a level sufficient to cause at least 0.6 volts to appear at the base-to-emitter junction of Q 2 ) and Q 1 will be off. With Q 2 on, the base 214 of Q 3 will be pulled low, causing Q 3 to turn on, resulting in the development of a positive voltage across output terminals 206 , 208 . Thus, over the positive and negative half cycles of V AC , Q 1 and Q 2 will alternately turn on and off over a portion of each half cycle, with the result that Q 3 will turn on and off at a 120 hertz rate and with a duty cycle of approximately 40% (i.e., Q 3 will be on 40% of the time, and off the remaining 60% of the time). Due to the filtering action of C 3 , V OUT will be at the second level (e.g., 8 volts), causing lamp 30 to be illuminated at a reduced light level (e.g., 50% of full light output).

A prototype ballast configured substantially as described in FIG. 2 was built and tested. Detector circuit 200 was observed to operate reliably in the presence of X capacitances (connected between each of the hot input connections 102 , 104 and neutral input connection 106 ) up to at least 15 microfarads, which is at least several orders or magnitude greater than the typical X capacitances that will be encountered in an actual ballast installation involving a large number of ballasts connected to the same branch circuit. Thus, the operation of detector circuit 200 is considered to be immune to any negative effects due to typical X capacitances.

Preferred values for the components of detector circuit 200 are given as follows:

Q 1 ,Q 2 : 2N3904

Q 3 : 2N3906

R 1 ,R 4 : 1 M′Ω

R 2 ,R 3 : 15 k′Ω

R 5 : 10 k′Ω

R 6 : 5 k′Ω

R 7 : 10 k′Ω

C 1 ,C 2 : 0.15 microfarad

C 3 : 10 microfarad

Preferably, ballast 100 further includes a pair of X capacitors X 1 ,X 2 that are believed to render detector circuit 200 substantially immune to capacitances that, due to wiring lengths and other factors, may be present between the first and second hot input connections 102 , 104 . As shown in FIG., 2 , first X capacitor X 1 is coupled between first hot input connection 102 and neutral input connection 106 . Second X capacitor X 2 is coupled between second hot input connection 104 and neutral input connection 106 . In a prototype ballast, capacitors X 1 and X 2 were chosen to each have a capacitance on the order of about 0.15 microfarads.

Preferably, EMI inductors L 1 ,L 2 ,L 3 are implemented using a single magnetic assembly (i.e., the windings for all three inductors are wound on the same bobbin). Further, for purposes of minimizing EMI, it is preferred that the bobbin for the magnetic assembly include separate sectors, and that the winding for each inductor L 1 ,L 2 ,L 3 be situated in its own sector(s), thus providing relatively loose coupling between the three inductors. This is in contrast with the more conventional approach of situating windings L 1 and L 2 in the same sector, with one winding wound on the top of the other (which provides tight coupling between L 1 and L 2 ), and placing the winding for L 3 in a different sector (which provides loose coupling between L 3 and the other two windings L 1 ,L 2 ). In a prototype ballast configured substantially as described in FIG. 2 , inductors L 1 ,L 2 ,L 3 were implemented by a single magnetic assembly with the following pertinent specifications:

Bobbin: EF25, 4 sectors

(from left to right: sector 1, sector 2, sector 3, sector 4)

Cores: EF25/13/7, ungapped

L 1 winding: 100 turns #29H AWG wire, wound in sector 3

L 2 winding: 100 turns #29H AWG wire, wound in sector 4

L 3 winding: 100 turns #27H AWG wire, wound in sectors 1 and 2

Inductance of L 1 ,L 2 ,L 3 : 29 millihenries (nominal)

Polarities of L 1 ,L 2 ,L 3 : As indicated by the dots shown in FIG. 2

Although the present invention has been described with reference to certain preferred embodiments, numerous modifications and variations can be made by those skilled in the art without departing from the novel spirit and scope of this invention.