DC-DC converter for converting an input voltage to a first output voltage

This application claims the benefit of Taiwan Application Patent Serial No. 093109232, filed Apr. 2, 2004, the subject matter of which is incorporated herein by reference.

1. Field of the Invention

The invention relates in general to DC—DC converters, and more particularly to DC—DC converters that are capable of outputting three times amplified, and two times amplified and inverted voltages.

2. Description of the Related Art

DC—DC converter is a circuit device that receives an input DC voltage and produces a DC output voltage. DC—DC converters have been used to amplify DC voltages, or to invert input DC voltages and output them as negative voltages. Due to their ability to receive low input voltages and consume low power, DC—DC converters have been widely used in all types of electronic products.

Low temperature poly-Si LCDs (liquid crystal display) are equipped with the technology to integrate circuits onto the glass substrate. Thus, integrating the DC—DC converter onto the LCD panel can result in many advantages including the reduction of the surrounding area, the ability to have low voltage supply and a single DC voltage source input, the reduction in production costs, and the ability to apply in mobile electronic products.

FIG. 1A is a circuit diagram of the traditional DC—DC converter. DC—DC converter 100 , applying the theory of charge pump, uses clock signals {overscore (φ 1 )}, φ 2 , φ 1 and φ 2 to control transistors SW 1 , SW 2 , SW 3 and SW 4 , and converts input voltage VDD to output voltage Vo 1 of 2VDD. Then DC—DC converter uses clock signals φ 2 , {overscore (φ 2 )}, {overscore (φ 2 )} and {overscore (φ 2 )} to control transistors SW 5 , SW 6 , SW 7 and SW 8 , and converts the value of output voltage Vo 1 to an output voltage Vo 2 of 3VDD, and also uses clock signals φ 2 , φ 2 , {overscore (φ 1 )}, and φ 1 to control transistors SW 9 , SW 10 , SW 11 and SW 12 , and converts output voltage Vo 1 to output voltage Vo 3 of −2VDD.

As shown in FIG. 1B , at time T 1 , the voltage level of clock signal φ 1 is at VDD, the voltage level of clock signal φ 2 is at 3VDD, and the voltage level of clock signal {overscore (φ 1 )} is at −2VDD. At this time, transistor SW 1 and SW 4 turn on, but transistor SW 2 and SW 3 remain off, making the voltage across capacitor C 1 to equal VDD. At time T 2 , clock signal φ 1 is at −2VDD, clock signal φ 2 is at 0V, clock signal {overscore (φ 1 )} is at VDD, and clock signal {overscore (φ 2 )} is at 3VDD. At this time, transistors SW 1 and SW 4 are turned off, and transistor SW 2 and SW 3 are turned on, causing output voltage Vo 1 to become 2VDD. In addition, at time T 2 , transistors SW 5 and SW 7 are turned on, and SW 6 and SW 8 are turned off, causing the voltage across C 2 to be VDD. And transistors SW 10 and SW 11 are turned on, and transistors SW 9 and SW 12 remain off, causing the voltage across C 3 to be 2VDD.

At time T 3 , clock signal φ 1 is at signal level VDD, clock signal φ 2 is at 3VDD, clock signal {overscore (φ 1 )} is at −2VDD, and clock signal {overscore (φ 2 )} is at 0V. At this time, transistors SW 5 and SW 7 are turned off, and transistors SW 6 and SW 8 are turned on, causing output voltage Vo 2 to become 3VDD. And transistors SW 10 and SW 11 are turned off, and transistors SW 9 and SW 12 are turned on, causing output voltage Vo 3 become −2VDD.

However, the described DC—DC converter 100 must use additional shift register 110 and 120 to convert clock signal CLK individually into the described clock signals φ 1 , {overscore (φ 1 )}, φ 2 and {overscore (φ 2 )}, as shown on FIG. 1C . Only then the DC—DC converter 100 can output the expected two times amplified, three times amplified, and two times amplified and inverted output voltages. However, the positive bias VDD and negative bias −2VDD of level shifter 110 , and the positive bias 3VDD of level shifter 120 are provided by the DC—DC converter 100 , thus, this structure will not only increase the loading of DC—DC converter 100 , but also aggravate the time required for DC—DC converter 100 to output stabilized voltage.

FIG. 2 is a circuit diagram of the DC—DC converter disclosed by U.S. Pat. No. 6,509,894. DC—DC converter 210 or 220 uses the clock signal HCK of the shift register (not shown on the figure) on the panel of low temperature poly-Si LCD as the clock signal, and uses inverter 211 and 212 or inverter 221 and 222 to output clock signals φ 11 and φ 12 or clock signals φ 21 and φ 22 . The clock signals are used to charge and discharge the capacitors C 11 and C 12 or C 21 and C 22 to control transistors T 11 , T 12 and T 13 or transistors T 21 , T 22 , and T 23 , and cause DC—DC converter 210 or 220 to be able to amplify the DC input voltage to produce twice amplified and inverted output voltages.

However, the high voltage levels of clock signal HCK of the shift register (not shown on the figure), located on the panel of the low temperature poly-Si LCD, are mostly at 3.3V. In order to produce a positive output voltage 2VDD of 9˜10V, and a negative output voltage −VDD of −6.5V˜−5V, the DC input voltage VDD and the positive bias voltage VDD of inverter 211 , 212 , 221 and 222 must be equal to 5V. Thus, the DC—DC converter of the LCD as disclosed by U.S. Pat. No. 6,509,894 must use an additional 5V DC voltage source and thereby increases the production cost of the system and the power consumption.

It is therefore an object of the invention to provide a DC—DC converter that utilizes existing DC voltage source, and clock signals from the shift register, both located on the LCD panel, to output three times amplified, and two times amplified and inverted output voltages, without the need of any additional clock signals, or any additional DC voltage source signals. The present invention has the advantages of being able to quickly provide three times amplified, and two times amplified and inverted output voltages, and reduces production costs and power consumption.

The invention achieves the above-identified object by providing a DC—DC converter to convert an input voltage to a first output voltage, and the DC—DC converter includes a first voltage output unit, a first energy-storing unit, and a first selecting switch. First voltage output unit includes a first selecting switch, and a first capacitor. First selecting switch includes a first input terminal and a first output terminal. Input voltage is input to first input terminal, and first selecting switch is controlled by a first signal. First capacitor has an a 1 end and a b 1 end, where b 1 end is coupled to first output terminal of first selecting switch, and outputs a first control voltage, and a 1 end receives first signal. First energy-storing unit includes a second selecting switch, and a second capacitor. Second selecting switch includes a second input terminal and a second output terminal, where input voltage is input to second input terminal, and second selecting switch is controlled by first control voltage. Second capacitor has an a 2 end and a b 2 end, where b 2 end is coupled to second output terminal of second selecting switch, and outputs a first energy-storing voltage, and a 2 end receive a second signal. First selecting switch receives first energy-storing voltage, and uses signal level of first control voltage as a reference to alternatively output a first energy-storing voltage as first output voltage, wherein first signal is alternatively at a first and a second signal level, and second signal is alternatively at a second and a first signal level. First and second signal come to a second signal level at a different time point. The value of first control voltage and first energy-storing voltage change according to first and second signal.

Other objects, features, and advantages of the invention will become apparent from the following detailed description of the preferred but non-limiting embodiments. The following description is made with reference to the accompanying drawings.

FIG. 1A (Prior Art) is circuit diagram showing a conventional DC—DC converter.

FIG. 1B (Prior Art) is signal timing diagram showing clock signals CLK, φ 1 , φ 2 {overscore (φ 1 )}, and, {overscore (φ 2 )} of DC—DC converter in FIG. 1A .

FIG. 1C (Prior Art) is partial block diagram of level shifters which are used by the DC—DC converter in FIG. 1A .

FIG. 2 (Prior Art) shows a circuit diagram illustrating a DC—DC converter as disclosed by U.S. Pat. No. 6,509,894

FIG. 3A is circuit diagram showing DC—DC converter outputting three times amplified output voltages according to first embodiment of the invention.

FIG. 3B is detailed circuit diagram showing DC—DC converter of FIG. 3A .

FIG. 3C is timing diagram showing clock signals CLK, CLK 1 and CLK 2 of FIG. 3B .

FIG. 4A is circuit diagram showing DC—DC converter outputting two times amplified and inverted output voltages according to second embodiment of the invention.

FIG. 4B is detailed circuit diagram of FIG. 4A , and

FIG. 4C is timing diagram of clock signals CLK, CLK 3 , CLK 4 and CLK 5 of FIG. 4B .

The invention utilizes existing DC voltage source, and clock signals from the shift register, both located on the LCD panel, to output three times amplified, and two times amplified and inverted output voltages, and to accomplish the goals in achieving low voltage input, reducing panel area, and decreasing power consumption without the need of any additional level shifters to increase signal levels of clock signals, or any additional DC voltage source signals. The following illustration includes two separate embodiments to demonstrate how DC—DC converter under this invention outputs three times amplified, and two times amplified and inverted output voltages. In the following two embodiments, clock signal CLK is high when signal level is at VDD, and CLK is low when signal level is at 0V.

FIG. 3A shows a circuit diagram of a DC—DC converter outputting three times amplified voltages in accordance with the first embodiment of the present invention. DC—DC converter 300 includes first voltage output unit 310 , second voltage output unit 320 , first energy-storing unit 330 , second energy-storing unit 340 , first selecting switch 350 , and second selecting switch 360 . DC—DC converter 300 utilizes clock signal CLK of shift register (not shown in figure) and input voltage VDD, both located on display panel, (not shown in figure), to generate output voltage Vo 1 .

First voltage output unit 310 receives clock signal CLK and outputs control voltage Vc 1 . First energy-storing unit receives clock signal CLK 1 , and outputs energy-storing voltage Vs 1 . While controlled by control voltage Vc 1 , first selecting switch 350 outputs energy storing voltage Vs 1 as output voltage Vi. Clock signal CLK 1 is generated after clock signal CLK goes through inverter 370 , where inverter 370 has a positive and a negative bias of VDD and 0V, respectively.

Second voltage output unit 320 receives clock signal CLK and outputs control voltage Vc 2 . The second energy-storing unit 340 receives clock signal CLK 2 and outputs energy-storing voltage Vs 2 . The second selecting switch 360 outputs control voltage Vc 2 as output voltage Vo 1 according to energy-storing voltage Vs 2 . Clock signal CLK 2 is generated after clock signal CLK 2 goes through inverter 380 , where positive and negative bias of inverter 380 are VDD and 0V, respectively.

FIG. 3B shows a detailed circuit diagram of DC—DC converter 300 of FIG. 3A . First voltage output unit 310 includes capacitor C 1 and PMOS (P-type Metal Oxide Semiconductor) transistor T 1 . Input voltage VDD is input to source S 1 of transistor T 1 , clock signal CLK is input to gate G 1 of transistor T 1 and a 1 end of capacitor C 1 . The b 1 end of capacitor C 1 is coupled to drain D 1 of transistor T 1 and outputs control voltage Vc 1 .

First energy-storing unit 330 includes capacitor C 2 and NMOS (N-type Metal Oxide Semiconductor) transistor T 2 . Control voltage Vc 1 is input to gate G 2 of transistor T 2 , and input voltage VDD is input to source S 2 of transistor T 2 . Clock signal CLK 1 is input to a 2 end of capacitor C 2 . The b 2 end of capacitor C 2 is coupled to drain of transistor T 2 and outputs energy-storing voltage Vs 1 .

In addition, first selecting switch 350 includes a PMOS transistor T 5 having a source S 5 , drain D 5 and gate G 5 . Energy-storing voltage Vs 1 is input to source S 5 , control voltage Vc 1 is input to gate G 5 , and drain D 5 outputs output voltage Vi.

Second voltage output unit 320 includes capacitor C 3 , and PMOS transistor T 3 having source S 3 , drain D 3 , and gate G 3 . Output voltage Vi is input to source S 3 , clock signal CLK is input to gate G 3 , and b 3 end of capacitor C 3 is connected to drain D 3 . The b 3 end of capacitor C 3 outputs control voltage Vc 2 , and a 3 end of capacitor C 3 is controlled by clock signal CLK.

Second energy-storing unit 340 includes capacitor C 4 , and NMOS transistor T 4 having source S 4 , gate G 4 , and drain D 4 . Control voltage Vc 2 is input to gate G 4 , output voltage Vi is output to source S 4 . The a 4 end of capacitor C 4 receives clock signal CLK 2 , and b 4 end of capacitor C 4 , connected to drain D 4 , outputs energy-storing voltage Vs 2 .

Second selecting switch includes PMOS transistor T 6 having source S 6 , drain D 6 and, gate G 6 . Energy-storing voltage Vs 2 is input to gate G 6 , control voltage Vc 2 is input to source S 6 , and drain D 6 outputs voltage Vo 1 .

Referring to FIGS. 3B and 3C , at time t 1 , clock signal CLK is at 0V, and clock signals CLK 1 and CLK 2 are at VDD. At this time, the voltage of gate G 1 of transistor T 1 is 0V, which is lower than voltage VDD of source S 1 , thus causing transistor T 1 to turn on. At this time, signal level of control voltage Vc 1 is substantially the same as input voltage VDD, thus causing the voltage across capacitor C 1 (which equals the voltage on b 1 end minus the voltage on a 1 end) to be VDD. At the same time, since gate G 2 of transistor T 2 has the voltage equal to control voltage Vc 1 (=VDD), and the source S 2 has voltage VDD, transistor T 2 does not turn on.

Then, at time t 2 , clock signal CLK is at VDD, and clock signals CLK 1 and CLK 2 are at 0V. At this time, the voltage at a 1 end of capacitor C 1 becomes VDD, but since properties of capacitor govern that the voltage across capacitor C 1 must remain at VDD in this condition, the voltage on b 1 end rises from control voltage Vc 1 to 2VDD.

In addition, since control voltage Vc 1 is input to gate G 2 of transistor T 2 , causing G 2 voltage to become 2VDD, which is higher than voltage VDD of source S 2 . Thus, transistor T 2 turns on, and causes the energy-storing voltage Vs 1 to be substantially the same as input voltage VDD. And at this time, the voltage across capacitor C 2 is VDD (equals to voltage on b 2 end minus voltage on a 2 end).

At time t 3 , clock signal CLK turns is at 0V, and clock signals CLK 1 and CLK 2 are at VDD. At this time, as described above, transistor T 1 is turned on, and control voltage Vc 1 is substantially the same as input voltage VDD, while transistor T 2 is turned off. Since voltage across capacitor C 2 must remain at VDD, the energy-storing voltage Vs 1 raises to 2VDD. Since the voltage of gate G 5 (=Vc 1 =VDD) is at a lower signal voltage than the voltage of source S 5 (=Vs 1 =2VDD), transistor T 5 is turned on, and thus the output voltage Vi is substantially the same as energy-storing voltage Vs 1 =(2VDD).

Also, at this time, transistor T 3 turns on, and causes the voltage across C 3 to be 2VDD (equals to voltage on b 3 end minus voltage on a 3 end), causes the signal level of control voltage Vc 2 to be at 2VDD. Gate G 4 of transistor T 4 is also at control voltage Vc 2 (=2VDD), and source S 4 is at output voltage Vi (=2VDD), hence, transistor T 4 does not turn on.

Next, at time t 4 , clock signal CLK is at VDD, and clock signals CLK 1 and CLK 2 are at 0V. At this time, gate G 3 of transistor T 3 has voltage VDD, which is at a lower bias of output voltage Vi (=2VDD)) than source S 3 , thus, T 3 transistor turns on. However, since the voltage across capacitor C 3 must remain at 2VDD, control voltage Vc 2 becomes 3VDD. And output voltage Vi also increases to 2VDD. At the same time, voltage of gate G 4 (which equals control voltage Vc 2 (=3VDD)) of transistor T 4 is higher than source voltage S 4 (which equals output voltage Vi (˜2VDD)), thus, transistor T 4 turns on, following the rise of output voltage Vi to 2VDD, energy-storing voltage Vs 2 also gradually increases accordingly. Although voltage of gate G 6 (equals to energy-storing voltage Vs 2 ) gradually increases, voltage of source S 6 (equals to control voltage Vc 2 (=3VDD)) is still at a higher voltage. Hence, transistor T 6 will turn on, causing drain D 6 of transistor T 6 to output an output voltage Vo 1 (=Vc 2 =3VDD).

Next, DC—DC converter 300 will repeat the conditions as described in time T 3 and T 4 , causing transistor T 6 to turn on and output an output voltage Vo 1 equals to 3VDD. Drain D 6 of transistor T 6 can also be electrically connected to a voltage-stabilizing capacitor Cx in order to maintain the voltage of drain D 6 of transistor T 6 at 3VDD.

In addition, in the first embodiment, a 1 end and a 2 end capacitor C 1 and capacitor C 2 receive clock signals CLK and CLK 1 , respectively. However, providing that clock signals CLK and CLK 1 transform to high signal level at a different time, such as two clock signals are not overlapping, then such modification is still within the scope of the appended claim. Similarly, providing that clocks signals CLK and CLK 2 input to a 3 and a 4 end of capacitor C 3 and C 4 transform to high signal level at a different time, such as two clock signals are not overlapping, then such modification is still within the scope of the appended claim.

FIG. 4A shows a circuit diagram of a DC—DC converter outputting inverted and two times amplified output voltages in accordance with second embodiment of the present invention. DC—DC converter 400 includes third voltage output unit 410 , fourth voltage output unit 420 , third energy-storing unit 430 , fourth energy-storing unit 440 , third selecting switch 450 and fourth selecting switch 460 . DC—DC converter 400 utilizes clock signal CLK of shift register (not shown in figure) and input voltage VDD, both located on display panel, (not shown in figure), to generate output voltage Vo 2 .

Third voltage output unit 410 receives clock signal CLK and outputs control voltage Vc 3 . Third energy-storing unit 430 receives clock signal CLK 3 , and outputs energy-storing voltage Vs 3 . Under control of control voltage Vc 3 , third selecting switch 450 outputs energy-storing voltage Vs 3 as output voltage Vj, where clock signal CLK 3 is generated after clock signal CLK goes through inverter 470 , and positive and negative bias of inverter 470 are VDD and 0V, respectively. Besides, fourth voltage output unit 420 receives clock signal CLK 4 , and outputs control voltage Vc 4 , where control voltage Vc 4 is generated after clock signal CLK goes through buffer 480 .

Fourth energy-storing unit 440 receives clock signal CLK 5 and output voltage Vj, and outputs energy-storing voltage Vs 4 . Fourth selecting switch 460 , controlled by control voltage Vc 4 , selectively outputs energy-storing voltage Vs 4 as output voltage Vo 2 , where clock signal CLK 5 is generated after CLK goes through inverter 490 , and both positive and negative bias of buffer 480 and inverter 490 are respectively Vj and 0V.

FIG. 4B shows a detailed circuit diagram of DC—DC converter 400 of FIG. 4A . Third voltage output unit 410 includes capacitor C 5 and PMOS transistor T 7 . Third energy-storing unit 430 includes capacitor C 7 and NMOS transistor T 9 . Third selecting switch unit 450 includes PMOS transistor T 11 having gate G 11 , source S 11 , and drain D 11 , where gate G 11 is controlled by control voltage Vc 3 , source S 11 receives energy-storing voltage Vs 3 , and drain D 11 outputs output voltage Vj.

Fourth voltage output unit 420 includes capacitor C 6 , and NMOS transistor T 8 having source S 8 , drain D 8 , and gate G 8 . Ground is connected to source S 8 , clock signal CLK 4 is input to gate G 8 , and b 6 end of capacitor C 6 is connected to drain D 8 . The b 6 end of capacitor also outputs control voltage Vc 4 , and a 6 end of capacitor C 6 receives clock signal CLK 4 .

Fourth energy-storing unit 440 includes capacitor C 8 , C 9 and PMOS transistor T 10 . Control voltage Vc 4 is input to gate G 10 of transistor T 10 , source of transistor S 10 is connected to ground. The a 8 end of capacitor C 8 receives clock signal CLK 5 , and b 8 end of capacitor C 8 couples to drain D 10 of transistor T 10 , and drain D 10 of transistor T 10 outputs energy-storing voltage Vs 4 . The a 9 end of capacitor C 9 is grounded, and b 9 end of capacitor C 9 is coupled to drain D 11 of transistor D 11 .

Fourth selecting switch 460 includes NMOS select transistor T 12 , having drain D 12 , source S 12 and gate G 12 . Energy-storing voltage Vs 4 is input to source S 12 , control voltage Vc 4 is input to gate G 12 , and drain D 12 outputs output voltage Vo 2 .

Referring to FIGS. 4B and 4C , at time T 1 , clock signal CLK is at 0V, and clock signal CLK 3 is at VDD. At this time, transistor T 7 turns on, causing control voltage Vc 3 to be VDD, and voltage across capacitor C 5 to be VDD.

Next, at time T 2 , clock signal CLK is at VDD, and clock signal CLK 3 is at 0V. At this time, transistor T 7 does not turn on, and control voltage Vc 3 becomes 2VDD. Also, transistor T 9 turns on, causing energy-storing voltage to be VDD, and voltage across capacitor C 7 to be VDD.

At time T 3 , clock signal is at 0V, and clock signal CLK 3 is at VDD. At this time, as described above, transistor T 7 turns on, causing control voltage Vc 3 to be VDD, but transistor T 9 does not turn on. Since voltage across C 7 must remain at VDD, energy-storing voltage Vs 3 raises to 2VDD. And since transistor T 11 is turned on, output voltage Vj becomes 2VDD, and the voltage across C 9 becomes and remains at 2VDD.

Next, at time T 4 , clock signal CLK becomes VDD. Capacitor C 9 causes output voltage Vj to remain at 2VDD. Clock signal CLK 4 becomes 2VDD, and clock signal CLK 5 becomes 0V. At this time, gate G 8 of transistor T 8 is at 2VDD, which is greater than 0V of source S 8 of transistor T 8 . Hence, transistor T 8 turns on, and causes control voltage Vc 4 to be 0V, and voltage across C 6 to be −2VDD (equals voltage on b 6 end minus voltage on a 6 end). In addition, voltage of gate G 10 of transistor T 10 is Vc 4 (0V), and the voltage of drain D 10 is 0V, thus, transistor T 10 does not turn on.

At time T 5 , clock signal CLK and CLK 4 become 0V, and clock signal CLK 5 becomes 2VDD. At this time, transistor T 8 does not turn on. Voltage across capacitor C 6 is −2VDD, as a result, voltage on b 6 end of capacitor C 6 becomes −2VDD. Since gate voltage of transistor T 10 is at control voltage Vc 4 (=−2VDD), which is lower than source voltage of 0V, transistor T 10 turns on, and energy-storing voltage Vs 4 becomes 0V. At the same time, clock signal being at 2VDD causes the voltage across capacitor C 8 to be −2VDD (equals voltage on b 8 end minus voltage on a 8 end). However, since gate voltage of transistor T 12 is at control voltage Vc 4 (=−2VDD), which is lower than 0V (energy-storing voltage Vs 4 ) of source voltage, the transistor still does not turn on.

At time T 6 , clock signal CLK becomes VDD, clock signal CLK 4 becomes 2VDD, and clock signal CLK 5 becomes 0V. At this time, transistor T 8 turns on, control voltage Vc 4 becomes 0V, transistor T 10 does not turn on Since clock signal CLK 5 is at 0V, and capacitor has a voltage of −2VDD across, energy-storing voltage Vs 4 becomes −2VDD. Meanwhile, gate G 12 of transistor T 12 is at control voltage Vc 4 (=0V), which is greater than the voltage of source S 12 (equals energy-storing voltage Vs 4 =−2VDD). Thus, transistor T 12 turns on, and causes output voltage Vo 2 to become Vs 4 (−2VDD). Next, DC—DC converter 400 will repeat conditions described during time T 5 and T 6 , causing transistor T 12 to output DC voltage of −2VDD when turned on. During time when transistor T 12 is not turned on, voltage-stabilizing capacitor Cy, coupled to drain D 12 of transistor T 12 , is used to maintain output voltage Vo 2 at −2VDD.

The clock signals CLK 3 and CLK 5 as described above are generated after clock signal CLK goes through inverter 470 and 490 , and clock signal CLK 4 is generated after CLK signal goes through buffer 480 . However, the invention can also use other clock signals, providing that clock signals CLK 3 and CLK, and clock signals CLK 4 and CLK 5 , are not the same clock signal, such as two non-overlapping clock signals and low signal level of signal CLK 4 and CLK 5 are the same as low signal level of CLK (such as 0V), and high signal level of signal CLK 4 and CLK 5 are twice the high signal level of CLK, an inverted and two times amplified output voltage Vo 2 can be produced.

Even though DC—DC converter 300 and 400 under present invention are used to respectively output three times amplified, and two times amplified and inverted DC voltages, yet if only the combination of first voltage output unit 310 , first energy-storing unit 330 , and first selecting switch 350 or of third voltage output unit 410 , third energy-storing unit 430 and third selecting switch 450 , are used, input voltage VDD can still be converted to output voltage Vi or Vj, having twice the voltage of VDD.

Although the two embodiments described above use MOS transistors T 1 ˜T 12 as exemplary illustration, providing that any form of selecting switch, such as TFT (Thin Film Transistor) or transmission gate, can be controlled by clock signals or control voltages as described in the two embodiments, then such variation is still within the scope of the appended claim.

Furthermore, clock signals CLK and CLK 1 of DC—DC converter 300 or 400 of present invention are not limited to signal levels 0V and VDD, but can also be at other signal levels. When clock signals CLK and CLK 1 are alternatively at a first signal level and a second signal level, voltage Vi and Vj are substantially the same as input voltage VDD, plus the difference in voltage between second and first signal level, wherein first signal level is lower than second signal level. And output voltage Vo 2 is substantially the same as output voltage VDD, plus the negative difference in voltage between second and first signal level. When signal levels CLK 2 and CLK 3 are alternatively at a third signal level and a fourth signal level, output voltage Vo 1 is substantially the same as the sum of output voltage VDD, difference in voltage between second and first signal level, and the difference in voltage between fourth and third signal level.

By utilizing drain D 6 of transistor T 6 and drain D 12 of transistor T 12 to respectively couple with voltage-stabilizing capacitor Cx and Cy, the DC—DC converter 300 and 400 of present invention, regardless of clock signal CLK being high or low, allows transistor T 6 and T 12 to output stable output voltage Vo 1 and Vo 2 . However, DC—DC converter can utilize design of dual-direction structure, by means of using two DC—DC converters 300 or 400 , electrically connecting output nodes of two DC—DC converters, and having clock signals CLK received by two DC—DC converters be the invert of each other, to allow two DC—DC converters to alternatively output all desired voltages.

According to the two embodiments described above, DC—DC converters under present invention have many advantages. Present invention utilizes existing input voltage VDD and clock signal CLK of shift register, not requiring additional level shifter to increase signal level of clock, and not requiring additional input voltage of different signal level, to output three times amplified, and two times amplified and inverted DC voltages, and results in the intended reduction in panel area, the ability to have low voltage input, and the decrease in power consumption.

While the invention has been described by way of example and in terms of a preferred embodiment, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.