Input/output block with programmable hysteresis

The present application claims priority of Indian Patent Application No. 1430/Del/2003 filed Nov. 18, 2003.

This invention relates to Input/Output Blocks (IOBs) in integrated circuits. More particularly, the invention relates to IOBs with programmable hysteresis to support multiple IO standards for providing optimum noise margins.

Hysteresis is an effective technique for enhancing the noise immunity of a logic circuit. High-speed switching circuits, where the switching speed is very high and input swing is very low are especially sensitive to noise. In such applications a precisely defined hysteresis voltage plays an important role in minimizing the effect of glitch signals. Different technologies supports different voltages i.e. the operating voltages and definition of the lower limit of threshold high (VIHmin) and upper limit of low (VILmax) level voltage varies with the technology used.

FIG. 1 shows the value of VIHmin and VILmax for GTL, GTL+, HSTL, SSTL, LVPECL, LVDS or AGP technologies. As is apparent from the figure these technologies support different hysteresis voltage levels (VIHmin−VILmax) e.g., for HSTL, VIHmin is 0.85V while VILmax is 0.65V for a reference voltage of 0.75V yielding a maximum hysteresis voltage of 200 mV around the reference voltage. On the other hand, GTL technology has VIHmin=0.85V and VILmax=0.75V for a reference voltage of 0.8V and can thus accommodate a hysteresis voltage of only 100 mV around 0.8 V. Similarly, other standards require different hysteresis values.

It is desired that an integrated circuit should support all available technologies specially when the circuit is expected to have a varying interface. For such cases the IOBs of the integrated circuit need to provide a control mechanism for adjusting the hysteresis according to requirements.

FIG. 2 is the simplified circuit diagram of an IOB in accordance with U.S. Pat. No. 5,958,026. This IOB can support the HSTL, GTL, GTL+IO standards which have a reference voltage VREF below 0.7V. The circuit operates as comparator whose trip voltage is set at VREF and whenever the signal crosses VREF the output changes. These type of IOBs do not provide any hysteresis option and hence a small amount of noise in the inputs can result in a false output.

FIG. 3 shows a similar IOB using inverted logic. The operation of this IOB is similar to that of FIG. 2 . This IOB can support SSTL2, SSTL3 and LVPECL IO standards without hysteresis.

FIG. 4 shows an input receiver used for GTL according to U.S. Pat. No. 5,666,068. This circuit is basically a PMOS differential amplifier having two reference voltages Vin 1 and Vin 2 . Transistors P 3 and P 4 are the input transistors while transistors P 8 and P 9 coupled in parallel with P 3 and P 4 , respectively, are used to provide hysteresis. This circuit provides a hysteresis value that is capable of satisfying the GTL standard only. Further, though the hysteresis voltage can be changed by varying the reference voltages Vin 1 and Vin 2 , this is not practically feasible since the sizes of the transistors are fixed in a circuit Therefore this circuit does not provide the flexibility to support different technologies.

What is desired, therefore, is a need to develop a system and method that provides a programmable hysteresis voltage to support different technology standards.

A method and system according to an embodiment of the present invention provides a programmable hysteresis voltage for supporting different technology standards. According to an embodiment of the present invention, an improved Input Output Block (IOB) providing programmable hysteresis includes:

a differential amplifier having one input coupled to an input signal and its second input coupled to a complementary input signal in the case of differential signaling, or to a reference voltage for the case of single-ended signaling, a pair of series coupled digital inverters coupled to one output of said differential amplifier, one or more transistors coupled in parallel with each input transistor of the differential amplifier, each transistor of each parallel coupled set being of a predetermined size relative to the corresponding input transistor, the control terminal of each parallel coupled transistor in each set being coupled to the output of one of said series coupled inverters such that positive feedback is provided directly or indirectly through a selection switch, and hysteresis control bits that symmetrically enable or disable each said selection switch to provide a programmable level of hysteresis that is determined by the combination of selection switches that are enabled and the relative sizes of the corresponding parallel coupled transistors.

The number and relative sizes of the parallel coupled transistors in the two sets are selected to provide the programmable hysteresis levels corresponding to a desired range of logic families.

The present invention also provides a method for providing programmable hysteresis in an Input Output Block (IOB), including:

providing a differential amplifier having one input coupled to an input signal and its second input coupled to a complementary input signal in the case of differential signaling, or to a reference voltage for the case of single-ended signaling, coupling a pair of series coupled digital inverters to one output of said differential amplifier, coupling one or more transistors in parallel with each input transistor of the differential amplifier, each transistor of each parallel coupled set being of a predetermined size relative to the corresponding input transistor, coupling the control terminal of each parallel coupled transistor in each set being to the output of one of said series coupled inverters such that positive feedback is provided directly or indirectly through a selection switch, and providing hysteresis control bits that symmetrically enable or disable each said selection switch to provide a programmable level of hysteresis determined by the combination of selection switches that are enabled and the relative sizes of the corresponding parallel coupled transistors.

The number and relative sizes of the parallel coupled transistors in the two sets are selected to provide the programmable hysteresis levels corresponding to a desired range of logic families.

The aforementioned and other features and objects of the present invention and the manner of attaining them will become more apparent and the invention itself will be best understood by reference to the following description of a preferred embodiment taken in conjunction with the accompanying drawings, wherein:

FIG. 1 shows different technology standard and voltage definitions;

FIG. 2 shows a prior art differential IOB in accordance with U.S. Pat. No. 5,958,026;

FIG. 3 shows another prior art differential IOB in accordance with U.S. Pat. No. 5,958,026;

FIG. 4 shows a prior art IOB in accordance with U.S. Pat. No. 5,666,068;

FIG. 5 shows an IOB in accordance with an embodiment of the present invention;

FIG. 6 shows another embodiment of the IOB in accordance with an embodiment of the present invention;

FIG. 7 shows another embodiment of the IOB in accordance with an embodiment of the present invention;

FIGS. 8A , 8 B, and 8 C show computer simulation results for the IOB of FIG. 7 ;

FIG. 9 shows another embodiment of the IOB in accordance with an embodiment of the present invention; and

FIGS. 10A , 10 B, and 10 C show computer simulation results for the IOB of FIG. 9 .

FIG. 5 shows a basic IOB in accordance with an embodiment of the present invention. The IOB has an NMOS differential input receiver comprising block 57 that is a load, and block 58 which is a current sink circuit. The load 57 is coupled to the current sink 58 through input transistors N 51 and N 52 . Transistor N 51 is controlled by input IN 1 while transistor N 52 is controlled by input IN 2 . For differential standards, IN 1 and IN 2 are differential inputs while for single ended standards IN 2 is a reference voltage. Each input transistor N 51 , N 52 has multiple transistors (only N 53 , N 54 , N 55 and N 56 are shown here) coupled in parallel with it as shown in the figure. Each transistor is of a predefined size to control the resistance offered by both the branches of input transistors. The transistors N 53 and N 54 are controlled by S 1 and S 3 while N 54 and N 56 are controlled by S 2 and S 4 respectively. The control signals S 1 , S 2 , S 3 and S 4 are generated by configuration bits and some feedback means. The parallel transistors are selectively enabled to provide a desired hysteresis voltage. This IOB can support standards whose input swings are towards VDD where VDD is the supply voltage. For example, this receiver can be used to support SSTL2, SSTL3, LVPECL etc. standards.

If the transistors N 53 and N 54 have width w 1 and the transistors N 55 and N 56 are of the width w 2 then variable hysteresis for different standards can be achieved by selecting the proper combinations of parallel transistors pairs (N 53 , N 54 and N 55 , N 56 . For IO standards which require small value of hysteresis, only one combination of parallel transistor pair, say N 53 and N 54 , are sufficient. In such a case, configuration bits enable N 53 and N 54 while N 55 and N 56 are disabled. Similarly, for standards which required a higher value of hysteresis both pairs of parallel transistor can be enabled by the configuration bits. Here only two pair of parallel transistors are shown, but the number can be varied depending upon the value of hysteresis required for different standards.

FIG. 6 shows an IOB in accordance with an embodiment of the present invention for inverted logic. It can be used to support HSTL, GTL, GTL+ etc. IO standards.

As shown in FIG. 5 and FIG. 6 , transistors are coupled in parallel with the input transistors to provide hysteresis. These parallel transistors can be programmatically switched ON and OFF by the configuration bits to provide different value of hysteresis for different standards. In this manner, various IO standards can be supported with optimum hysteresis or noise margin.

FIG. 7 shows one of the possible embodiments in accordance with the present invention. The circuit has a load realized by transistors P 71 and P 72 and transistor N 79 is the current sink. The sources of P 71 and P 72 are coupled to VDD while their gates are coupled together with the drain of P 71 . The gate of N 79 is coupled to some bias voltage at which the circuit can sink the desired amount of current. The drain of N 79 is coupled with the sources of input voltage transistors N 71 and N 72 while its source is coupled to ground. Transistors N 71 and N 72 are the input transistors and transistors N 73 , N 74 , N 75 , N 76 , N 77 and N 78 are the transistors coupled in parallel to the input transistors as shown in FIG. 7 . At least one transistor of the parallel-coupled transistor has its control terminal coupled to the output of the circuit and also at least one transistor has its control terminal coupled to the inverted output of the circuit as shown in FIG. 7 . The rest of the control terminals of the said parallel-coupled transistors are coupled to signals S 1 , S 2 etc., which are used to control the states of the parallel transistors. The drain of N 71 is coupled to the drain of P 71 while its source is coupled to the drain of N 79 . The source of N 72 is coupled to the drain of N 79 while its drain is coupled to the drain of P 72 which is the OUT 1 terminal. Two inverters 170 and 171 , are coupled back to back with OUT 1 as input and OUT as output terminal. The gate of N 73 is coupled to the receiver output OUT while the gate of N 74 is coupled to the inverted form of receiver output X. The gates of N 75 and N 77 are coupled to S 1 and S 3 respectively while the gates of N 76 and N 78 are coupled to S 2 and S 4 respectively. The control signals S 1 , S 2 , S 3 and S 4 are generated by the switch SW 70 and configuration bits CB 1 and CB 2 .

FIG. 7 also shows switch SW 70 consisting of transmission gate TG 70 and NMOS N 70 . The switch is controlled by configuration bit CB. When configuration bit CB is high, TG 70 couples Y to A; for this case N 70 is OFF. When CB is low, TG 70 is OFF and N 70 is ON; this makes output Y low. Blocks 71 , 72 , 73 and 74 are used to generate S 1 , S 2 , S 3 and S 4 that control the states of the parallel transistors.

When CB 1 and CB 2 are both LOW i.e. CB 1 =0, CB 2 =0, SW 70 couples S 1 , S 2 , S 3 and S 4 to ground. This makes N 75 , N 76 , N 77 and N 78 OFF. In this case N 73 and N 74 are conducting since they are directly coupled to OUT and X. These two transistors provide a hysteresis value which is sufficient to support standards which required minimum hysteresis. For example, LVPECL is supported, which can have a maximum hysteresis of 310 mV. To support SSTL2, which requires a higher value of hysteresis, another branch comprising parallel transistors N 75 and N 76 can be turned ON by making configuration bit CB=1. In this manner, standards which require more hysteresis can be supported by turning ON all the branch of parallel transistors by making CB 1 =1 and CB 2 =1. The sizing of the parallel transistors can be chosen such that the various standards can be supported by selecting the appropriate combination of parallel transistors.

FIGS. 8A , 8 B, 8 C shows the hysteresis characteristics of various standards obtained by computer simulation of the circuit shown in FIG. 6 . FIG. 8A shows the hysteresis characteristics for the LVPECL standard. The desired hysteresis for LVPECL can be achieved by configuring CB 1 =0 and CB 2 =0. In this case N 75 , N 76 , N 77 and N 78 are all OFF. FIG. 8B shows the hysteresis characteristics of FIG. 6 for the SSTL2 standard. In this case CB 1 =1 and CB 2 =0. FIG. 8C shows the hysteresis characteristics of FIG. 6 for the SSTL3 standard and in this case CB 1 =1 and CB 2 =1. As apparent from FIGS. 8A , 8 B and 8 C the hysteresis characteristic is symmetrical and evenly spread about the reference voltage VREF for all the standards. The hysteresis characteristic has two threshold voltages. One threshold voltage is used for the low to high output transition, VTH and the other threshold voltage is used for the high to low output transition, VTL. This means that the output will only be high when the input is VTH or higher. Similarly, the output will be low when the input is VTL or lower. By this way a noise of width VTH−VTL can be eliminated.

FIG. 9 shows another embodiment of the invention for inverted logic. A person skilled in art will appreciate that the circuit operation of the FIG. 9 remains the same as that of the circuit shown in FIG. 7 except for the polarity of the supply. FIG. 10 are the simulation results corresponding to the embodiment shown in FIG. 9 .

In FIG. 7 and FIG. 9 , by varying the number of parallel pair transistors, various standards can be supported with optimum hysteresis. While FIG. 7 and FIG. 9 show an implementation as an NMOS differential amplifier and PMOS differential amplifier respectively, a person in the art will appreciate that the same concept can also be realized in a combination of both NMOS and PMOS differential amplifiers. The present discussion is only an illustrative description of the invention and the scope of the invention is not limited to the circuits described.

It will be apparent to those with ordinary skill in the art that the foregoing is merely illustrative intended to be exhaustive or limiting, having been presented by way of example only and that various modifications can be made within the scope of the above invention.

Accordingly, this invention is not to be considered limited to the specific examples chosen for purposes of disclosure, but rather to cover all changes and modifications, which do not constitute departures from the permissible scope of the present invention. The invention is therefore not limited by the description contained herein or by the drawings, but only by the claims.