Semiconductor apparatus and method of charging desired number of capacitors

This application claims priority under 35 USC §119 to Japanese Patent Application No. 2003-378339 filed on Nov. 7, 2003, the entire contents of which are herein incorporated by reference.

A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever.

1. Field of the Invention

The present invention relates to capacitor charging semiconductor apparatuses, in particular, to capacitor charging semiconductor apparatuses each integrally formed from a plurality of parallel monitor circuits to equally charge a plurality of electric double layer type capacitors, which are serially connected to each other.

2. Discussion of the Background Art

An electric double layer type capacitor can be charged faster than a secondary battery because the secondary battery generally takes a certain time period to be charged. Since a rated voltage of the electric double layer type capacitor is generally low, for example, approximately three volts, a necessary voltage is typically obtained by serially connecting a plurality of such capacitors. When charging such capacitors, a problem that arises is unevenness of charge caused by a difference in a capacitor capacitance, its own charging and discharging, and so on. One approach is to employ an equally charging circuit called a parallel monitor circuit as illustrated in FIG. 6 . Specifically, since an output of a comparator CMP 1 becomes high, and accordingly a transistor Tr 1 is turned on when a voltage V 1 of a capacitor C 1 exceeds a reference voltage Vr 1 in the parallel monitor circuit, charge current is bypassed by the transistor Tr 1 to avoid excessive charging to the capacitor C 1 as discussed in Japanese Patent Application Laid Open No. 2000-50495, for example.

However, due to non-integration of a semiconductor apparatus, i.e., assembly of discrete parts, size and cost of the background parallel monitor circuit increase. Then, the integration is conventionally demanded. However, if a semiconductor apparatus is manufactured while changing a number of parallel monitor circuits to be integrated, a small number of various products are generally produced because the number of serially connected capacitors varies depending upon usage. As a result, advantages of mass-production of the semiconductor apparatus are suppressed. Thus, the semiconductor apparatus is expensive and cannot practically be used. Further, if a semiconductor apparatus is manufactured with it being integrated with only one parallel monitor circuit, the parallel monitor circuit cannot be effectively downsized resulting in loss of the advantages of the integration.

Then, as shown in FIG. 1 , when approximately five to ten parallel monitor circuits (e.g. five in FIG. 1 ) are integrated on one semiconductor apparatus IC 1 , and a number of capacitors to be charged is more than that of the integrated parallel monitor circuits, the same semiconductor apparatuses can be longitudinally connected as needed. Thus, a semiconductor apparatus can be mass-produced, while downsizing and reducing cost of the entire monitor circuit.

However, a total number of chargeable capacitors are unavoidably integral multiples of that of capacitors charged by one semiconductor apparatus. As a result, the other number of capacitors cannot be charged.

Accordingly, an object of the present invention is to address and resolve the above-noted and other problems and provide a new a capacitor charging semiconductor apparatus and method. The above and other object are achieved according to the present invention by providing a novel capacitor charging semiconductor apparatus which includes a plurality of capacitors serially connected to each other, a direct current power source that supplies charge current to the plurality of capacitors, and a plurality of bypass use transistors each bypasses charge current when a voltage of a capacitor exceeds a prescribed reference level. A plurality of parallel monitor circuits is provided to control the bypass use transistor to equally charge the plurality of capacitors. A plurality of capacitor connection terminals is included in the semiconductor apparatus and is connected to both ends and a plurality of intersections formed between the plurality of capacitors. A plurality of transistor connection terminals is included in the semiconductor apparatus to be connected to control terminals of bypass use transistors. A prescribed number of the capacitors are optionally charged by shorting prescribed number of capacitor connection terminals starting from those connected to a highest voltage side and a lower voltage side.

In another embodiment, a prescribed number of capacitors are charged by shorting neighboring capacitor connection terminals in a capacitor charging semiconductor apparatus.

In yet another embodiment, a capacitor charging semiconductor apparatus has a plurality of control terminals to control charge current and a semiconductor apparatus. A number of chargeable capacitors are increased by longitudinally connecting a plurality of capacitor charging semiconductor apparatuses to each other via some of the control terminals.

In yet another embodiment, the parallel monitor circuit includes a signal generation function that generates a charge completion signal when a capacitor voltage reaches a prescribed reference voltage. The charge completion signal is controlled not to be outputted from a parallel monitor circuit where a corresponding capacitor connection terminal is shorted.

A more complete appreciation of the present invention and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:

FIG. 1 illustrates an exemplary fundamental capacitor charging semiconductor apparatus according to a first embodiment of the present invention;

FIG. 2 illustrates an exemplary capacitor charging semiconductor apparatus according to a second embodiment of the present invention;

FIG. 3 illustrates an exemplary capacitor charging semiconductor apparatus according to a third embodiment of the present invention;

FIG. 4 illustrates exemplary capacitor charging semiconductor apparatuses longitudinally connected to each other according to a fourth embodiment of the present invention;

FIG. 5 illustrates an exemplary semiconductor apparatus according to a fourth embodiment of the present invention;

FIG. 6 illustrates an exemplary parallel monitor circuit and an exemplary connection terminal provided in a semiconductor apparatus according to one embodiment of the present invention;

FIG. 7 illustrates an exemplary manner of connecting control terminals according to one embodiment of the present invention; and

FIGS. 8A and 8B specifically illustrate the exemplary connecting manner according to one embodiment of the present invention.

Referring now to the drawings, wherein like reference numerals and marks designate identical or corresponding parts throughout several figures, particularly to FIG. 1 , a fundamental configuration of a capacitor charging semiconductor apparatus is described. As shown, a number of parallel monitor circuits provided in a semiconductor apparatus are the same as that of the capacitors. Specifically, the semiconductor apparatus IC 1 includes five groups of parallel monitor circuits to charge five capacitors C 11 to C 15 , a plurality of capacitor connection terminals Vdd, Cell 1 to Cell 5 (i.e., Vss) connected to both ends and intersections between respective five serially connected capacitors C 11 to C 15 , and a plurality of transistor connection terminals OUT 1 to OUT 5 connected to respective bases of bypass use transistors. When the five capacitors are to be charged, a terminal Vdd of the semiconductor apparatus is connected to the positive side terminal of the capacitor C 11 , while a terminal Cell 1 is connected to the negative terminal of the capacitor C 11 and the positive side terminal of the serially connected capacitor C 12 . Similarly, terminals Cell 2 to Cell 5 are connected to respective terminals of the capacitors as shown in FIG. 1 . The respective bypass use transistors TR 11 to TR 15 are assigned to the capacitors C 11 to C 15 , respectively. The bases are connected to the transistor connection terminals OUT 1 to OUT 5 , respectively.

Referring now to FIG. 6 , an arrangement of connection terminals provided between a semiconductor apparatus and capacitors or bypass use transistors will be described in detail. As shown, only the capacitors 1 and 2 are illustrated. However, the capacitor 3 and subsequent capacitors have substantially the same configuration. The parallel monitor circuit includes a pair of comparators CMP 1 and CMP 2 , non-inversion inputs of a power supply terminal Vdd and a voltage V 2 , and inversion inputs of voltages Vr 1 and Vr 2 . When described linking with FIG. 1 , the terminal Vdd of FIG. 1 corresponds to the power supply terminal Vdd of FIG. 6 . The Out 1 of FIG. 1 is connected to an output of the comparator CMP 1 and a base of the bypass use transistor Tr 1 in FIG. 6 . The Cell 1 terminal of FIG. 1 serves as a negative side terminal of the capacitor 1 in FIG. 6 . The Out 2 terminal of FIG. 1 is connected to an output of the comparator CMP 2 and a base of the bypass use transistor Tr 2 in FIG. 6 . The Cell 2 terminal of FIG. 1 serves as a negative side terminal of the capacitor 2 in FIG. 6 . Similarly, respective terminals of the Out 3 to Out 5 and Cell 3 to Cell 5 of FIG. 1 are connected to those of the corresponding capacitors 3 , 4 , and 5 and bypass use transistors Tr 3 , Tr 4 , and Tr 5 , respectively, in FIG. 6 .

A capacitor charging semiconductor apparatus according to a first embodiment of the present invention will now be described with reference to FIG. 2 . As shown, four capacitors are charged. A difference from the semiconductor apparatus of FIG. 1 is that the terminals Vdd and Cell 1 are shorted, and a positive side terminal of a capacitor C 12 disposed at the highest voltage side among the four capacitors is connected to a capacitor connection terminal Cell 1 of a semiconductor apparatus. Thus, when a smaller number of capacitors is to be charged, a prescribed number of capacitor connection terminals neighboring the high voltage side capacitor connection terminal Vdd are preferably shorted as a number of capacitors decrease. For example, when three capacitors are to be charged, three terminals Vdd, Cell 1 , and Cell 2 are preferably shorted, and a positive side terminal of a capacitor of the highest voltage is preferably connected to the terminal Cell 2 . Thus, one to five capacitors are optionally charged.

A capacitor charging semiconductor apparatus according to a second embodiment of the present invention will now be described with reference to FIG. 3 . As shown, four capacitances are charged as in the first embodiment. The only difference from the semiconductor apparatus of FIG. 2 is that capacitor connection terminals Cell 1 and Cell 2 are shorted. Although there is a restriction in the first embodiment of FIG. 2 that a capacitor connection terminal should be shorted in order from the highest voltage side capacitor connection terminal Vdd, such a restriction is not needed, and even a restriction of wiring and so on is decreased in the second embodiment of FIG. 3 because capacitor connection terminals are optionally shorted. For example, when three capacitors are to be charged, any two of the capacitor connection terminals are optionally shorted. Thus, one to five capacitors can be optionally charged.

A capacitor charging semiconductor apparatus according to a third embodiment of the present invention will now be described with reference to FIG. 4 . As shown, two units of semiconductor apparatuses are longitudinally connected. If the semiconductor apparatus of FIG. 2 is employed, and a number of capacitor connection terminals are increasingly shorted from the highest voltage side capacitor connection terminal Vdd as shown in FIG. 4 , six to ten capacitors can be charged. Further, if the semiconductor apparatus of FIG. 3 is employed (not shown) and a number of optional capacitor connection terminals in the semiconductor apparatuses IC 1 and IC 2 of FIG. 4 are increasingly shorted, one to ten capacitors can be charged. A control circuit is connected to the semiconductor apparatus IC 2 is formed from a CPU or the like to control a charge current supplied to the capacitors C 11 to C 15 and C 22 to C 25 as well as the semiconductor apparatuses IC 1 and IC 2 .

A parallel monitor circuit according to a fourth embodiment of the present invention will be described with reference to FIG. 5 . A parallel monitor circuit 1 controls charging to the highest voltage side capacitor in a semiconductor apparatus. Five circuits of substantially the same configuration are included in the semiconductor apparatus in this embodiment. Specifically, parallel monitor circuits 1 to 5 are arranged in order from the highest voltage side. Since these parallel monitor circuits 1 to 5 have substantially the same configuration, only the parallel monitor circuit 1 is typically described. The parallel monitor circuit 1 includes a pair of resistances R 12 and R 13 which detect a voltage of a capacitor C 1 , a reference voltage Vr 1 , a comparator CMP 1 , an inverter INV 1 , and three MOSFETS M 11 , M 12 , and M 13 . A power supply for the comparator CMP 1 has the same voltage as that of the semiconductor apparatus. A voltage obtained by dividing the voltage of the capacitor C 1 is connected to an inversion input terminal (−) of the comparator CMP 1 , while a reference voltage Vr 1 is connected to a non-inversion input terminal (+). An output of the comparator CMP 1 is connected to an input of an inverter INV 1 .

Since the same voltage as that applied to the capacitor C 1 is applied to an inverter INV 1 as a power supply, an output voltage of the inverter INV 1 ranges within the voltage of the capacitor C 1 . Thus, a signal is outputted limiting the output voltage of the comparator CMP 1 . The output of the inverter INV 1 is connected to a transistor connection terminal OUT 1 and a base of a bypass use transistor Tr 1 . When a voltage of the capacitor C 1 is low and that of the inversion input terminal (−) of the comparator CMP 1 is lower than a reference voltage Vr 1 , an output of the comparator CMP 1 is high (i.e., Vdd). The signal is inverted by the inverter INV 1 with voltage limitation within the voltage range of the capacitor C 1 . A low level signal outputted from the inverter INV 1 is a negative side potential of the capacitor C 1 . Since this voltage is outputted from the transistor connection terminal OUT 1 , a voltage between the base and emitter of the bypass use transistor TR 1 is zero volts. Thus, the bypass use transistor TR 1 is turned off and does not bypass charge current.

When the voltage of the capacitor increases and that of the inversion input terminal (−) of the comparator CMP 1 exceeds the reference voltage Vr 1 , an output of the comparator CMP 1 becomes low (i.e., Vss). The inverter INV 1 inverts this signal, and the voltage is limited within that of the capacitor C 1 . A high level signal outputted from the inverter INV 1 is a potential of the positive side of the capacitor C 1 . Since this voltage is outputted from the transistor connection terminal OUT 1 , a base current is supplied to the bypass use transistor TR 1 . Thus, the bypass use transistor TR 1 is turned on, and bypasses charge current.

The MOSFETs M 1 and M 11 to M 13 collectively form a circuit for generating a charge completion signal that externally informs completion of charging to the capacitor C 1 . The source of the NchMOSFET M 13 is connected to a negative side potential of the capacitor C 1 , while the gate is connected to a positive side potential of the capacitor C 1 . Further, the drain is connected to a power supply Vdd of the semiconductor apparatus via a current source 11 serving as a load and the gate of the PchMOSFET M 11 .

The source of the PchMOSFET M 11 is connected to the power supply Vdd of the semiconductor apparatus, while its drain is connected to the source of the PchMOSFET M 12 . The gate of the PchMOSFET M 12 is connected to an output of the comparator CMP 1 . Further, the drain of the PchMOSFET M 12 is connected to a drain of a depletion type NchMOSFET M 1 arranged in a control circuit. Since the source and gate of the depletion type NchMOSFET M 1 are shorted to each other, the depletion type NchMOSFET M 1 constitutes a constant current source and operates as a load for the PchMOSFETs M 11 and M 12 .

Since an output voltage of the comparator CMP 1 becomes low (i.e., Vss) when the voltage of the capacitor C 1 increases and that of the inversion input terminal (−) of the comparator CMP 1 exceeds the reference voltage Vr 1 , the gate voltage of the PchMOSFET M 12 decreases and turns on the PchMOSFET M 12 . Simultaneously, since the gate voltage of the NchMOSFET M 13 is the same as that of the capacitor C 1 , and thus the NchMOSFET M 13 is turned on, the gate voltage of the PchMOSFET M 11 decreases and turns on the PchMOSFET M 11 .

Specifically, since the PchMOSFETs M 11 and M 12 are turned on when charging to the capacitor C 1 is completed, the drain voltage of the PchMOSFET M 12 becomes equivalent to the power supply voltage Vdd. Such a voltage serves as a charge completion signal D 1 of the parallel monitor circuit 1 . The same circuits are provided in respective parallel monitor circuits 2 to 5 , and respective charge completion signals D 2 to D 5 outputted from the respective circuits are connected to the drain of the depletion type NchMOSFET M 1 .

When at least one of charge completion signals D 1 to D 5 is outputted, the terminal Dout becomes high (i.e., Vdd), the one of charge completion signals D 1 to D 5 becomes a charge completion signal that externally informs completion of charging to the one of the capacitors C 1 to C 5 . If the capacitor connection terminals Vdd and Cell 1 are shorted, the gate and source of the NchMOSFET M 13 are shorted to each other resulting in turning off the NchMOSFET M 13 .

Since the drain of the NchMOSFET M 13 (i.e., the gate of the PchMOSFET M 11 ) becomes high (i.e., Vdd) as a result, and thus the PchMOSFET M 11 is turned off, a charge completion signal D 1 is not outputted. Specifically, when the capacitor connection terminal is shorted, a charge completion signal is not erroneously generated from a parallel monitor circuit. Even though the above-mentioned preferred embodiment uses the five chargeable capacitors for one semiconductor apparatus, the present invention is not limited thereto and can optionally use a prescribed number of capacitors.

Four exemplary types of control terminals and a manner of connecting the control terminals will be now described with reference to FIGS. 7 and 8 . As shown in FIG. 7 , the control terminals CON 1 to CON 10 of FIGS. 1 to 4 are described. Specifically, an output terminal outputs a signal, which reports a condition of the semiconductor apparatus to a microcomputer, while an input terminal receives an input of a control signal, which controls a semiconductor apparatus, from a microcomputer. For example, output and input signals are transmitted as a pair to a semiconductor apparatus (IC). As shown, four types of control terminals are connected between semiconductor apparatuses ICn+1 and ICn. However, a number of control terminals per an IC is not limited thereto. Further, up and down signals are connected to terminals as shown in FIGS. 8A and 8B . However, a number of up and down signals is not limited thereto.

A microcomputer is connected to an IC, which is connected to the lowest voltage (i.e., zero volts) through its Vss terminal. An IC of the lowest voltage side is given a reference numeral IC 1 , an IC next to the IC 1 is given a reference numeral IC 2 , and the n-th number IC is given a reference numeral ICn. When the microcomputer is connected, a detection signal, such as a voltage detection alarm, a negative voltage detection alarm, etc., which appears in a serially connected capacitor system, is required to be outputted from an applicable IC to the microcomputer. Thus, the alarm signal is transmitted from the ICn to the microcomputer via the IC 1 . A control terminal is provided on the high voltage side of the ICn to be connected to the ICn+1, while a control terminal is provided on the low voltage side thereof to be connected to the ICn−1.

Since the alarm signal needed to be transmitted to the semiconductor apparatus ICn−1 is outputted from the low voltage side IC connection terminal of the semiconductor apparatus ICn, and inputted to the high voltage side IC connection terminal of the semiconductor apparatus ICn−1. A signal transmitted to a low voltage side IC is hereinafter referred to as a down signal, while a signal transmitted to a high voltage side IC is hereinafter referred to as an up signal. The down signal inputted to the ICn−1 undergoes signal conversion in an interior circuit, and outputted from the low voltage side IC connection terminal of the ICn−1. The down signal is then inputted to the high voltage side IC connection terminal of the ICn−2. By repeating signal transmissions in such a manner, the down signal is finally inputted to the high voltage side IC connection terminal of the IC 1 . The down signal inputted to the IC 1 undergoes signal conversion in the interior circuit, and is outputted from the low voltage side IC connection terminal to the microcomputer. The alarm signal is transmitted in such an order.

Further, a control signal transmitted from the microcomputer is the up signal, and is inputted to the low voltage side IC connection terminal of the IC 1 . The up signal in the IC 1 then receives signal conversion in the interior circuit and is outputted therefrom and inputted to the low voltage side IC connection terminal of the IC 2 . By repeating the above-mentioned operations, the control signal is finally transmitted to the highest voltage IC. In summary, a low voltage side IC connection terminal outputs a down signal therefrom and inputs it to a corresponding high voltage side IC connection terminal of another low voltage side IC lower by one. A high voltage side IC connection terminal outputs an up signal therefrom and inputs it to a corresponding low voltage side IC connection terminal of another high voltage side IC higher by one. As shown in FIG. 7 , four types of control terminals, i.e., high voltage side IC connection input and output terminals, and low voltage side IC connection input and output terminals, are employed.

As shown in FIGS. 8A and 8B , the high voltage side IC connection output terminal can be an N-channel open drain, for example. The high voltage side IC connection input terminal serves as an inverter input terminal in an opposite terminal side of a high resistance element connected to the voltage Vss of the IC. The low voltage side IC connection output terminal can be a P-channel open drain. The low voltage side IC connection input terminal serves as an inverter input terminal on an opposite terminal side of a high resistance element that is connected to the voltage Vdd of the IC. When the N-channel open drain of the high voltage side IC connection output terminal of the semiconductor apparatus ICn is turned on, the voltage of the high voltage side IC connection output terminal of the semiconductor apparatus ICn becomes equivalent to the voltage Vss of the semiconductor apparatus ICn. The low voltage side IC connection input terminal of the semiconductor apparatus ICn+1 receives a LOW signal as a corresponding recipient from the semiconductor apparatus ICn. Then, some current flows to the high resistance element connected to the Vdd of the semiconductor apparatus Icn+1, while a LOW signal is inputted to the inverter input. A signal is transmitted through the semiconductor apparatus ICn+1, and turns on the N-channel open drain of the high voltage side IC connection output terminal of the semiconductor apparatus ICn+1. Thus, the signal is transmitted to the semiconductor apparatus ICn+2.

When the N-channel open drain of the high voltage side IC connection output terminal of the semiconductor apparatus ICn is turned off, the high voltage side IC connection output terminal of the semiconductor apparatus ICn is in a floating state. However, since being drawn by the high resistance element connected to the Vdd, which is connected to the low voltage side IC connection input terminal of the semiconductor apparatus ICn+1, the voltage of the high voltage side IC connection output terminal serving as a corresponding recipient becomes equivalent to the voltage Vdd of the semiconductor apparatus ICn+1.Thus, a high level signal is inputted to the inverter input of the low voltage side IC connection input terminal of the semiconductor apparatus ICn+1. The high level signal is conveyed through the semiconductor apparatus ICn+1, and turns off the N-channel open drain of the high voltage side IC connection output terminal of the semiconductor apparatus ICn+1. Then, the signal is transmitted to the semiconductor apparatus ICn+2.

When the P-channel open drain of the low voltage side IC connection output terminal of the semiconductor apparatus ICn is turned on, the voltage of the low voltage side IC connection output terminal of the semiconductor apparatus ICn becomes equivalent to the voltage Vdd of the semiconductor apparatus ICn. The high voltage side IC connection input terminal of the semiconductor apparatus ICn−1 receives a high level signal of the semiconductor apparatus Icn as a corresponding recipient. Thus, some current flows through the high resistance element connected to the voltage Vss of the semiconductor apparatus ICn−1, while a high level signal is inputted to the inverter. The signal is conveyed through the semiconductor apparatus ICn−1, and then turns on the P-channel open drain of the low voltage side IC connection output terminal of the semiconductor apparatus ICn−1. Thus, the signal is transmitted to the semiconductor apparatus ICn−2.

When the P-channel open drain of the low voltage side IC connection output terminal of the semiconductor apparatus ICn is turned off, the low voltage side IC connection output terminal of the semiconductor apparatus ICn is in a floating state. However, since being drawn by the high resistance element connected to the Vss, which is connected to the high voltage side IC connection input terminal of the ICn−1 serving as a corresponding recipient, the voltage of the low voltage side IC connection input terminal becomes equivalent to the voltage Vss of the ICn−1. Thus, a low-level signal is inputted to the inverter input of the high voltage side IC connection input terminal of the semiconductor apparatus ICn−1. The low-level signal is conveyed through the semiconductor apparatus ICn−1, and then turns off the P-channel open drain of the low voltage side IC connection output terminal of the semiconductor apparatus ICn−1. Thus, the low level signal is transmitted to the semiconductor apparatus ICn−2. A system using the above-mentioned control terminal is not limited thereto, and the other system can be employed.

Further, a type of a terminal employable in the present invention can be either a pin insertion type or a surface package type. The surface package type can include ball grid, Gull-wing lead, and J-lead type terminals. Various packages, such as a DIP, a PGA, a SOP, a QFP, a BGA, a CSP, etc., having an opposing lead side can be employed.