Liquid crystal display device

This application claims the benefit of Korean Patent Application No. P2003-90301, filed Dec. 11, 2003, and P2004-29615 filed on Apr. 28, 2004, which are hereby incorporated by reference for all purposes as if fully set forth herein.

1. Field of the Invention

This invention relates to a liquid crystal display, and more particularly to a liquid crystal display device that is adaptive for improving working efficiency as well as reducing manufacturing costs.

2. Description of the Related Art

Generally, a liquid crystal display (LCD) controls a light transmittance of a liquid crystal using an electric field to thereby display a picture.

To achieve this, as illustrated in FIG. 1 , the LCD includes a matrix-type liquid crystal display panel 2 , in which liquid crystal cells are arranged in a matrix, a gate driver 6 for driving gate lines GL 1 to GLn of the liquid crystal display panel 2 , a data driver 4 for driving data lines DL 1 to DLm of the liquid crystal display panel 2 , and a timing controller 8 for controlling the gate driver 6 and the data driver 4 .

The liquid crystal display panel 2 includes a thin film transistor TFT provided at each intersection between the gate lines GL 1 to GLn and the data lines DL 1 to DLm, and a liquid crystal cell 7 connected to the thin film transistor TFT. The thin film transistor TFT is turned on when it is supplied with a scanning signal, that is, a gate high voltage VGH from the gate line GL, to thereby apply a pixel signal from the data line DL to the liquid crystal cell 7 . Further, the thin film transistor TFT is turned off when it is supplied with a gate low voltage VGL from the gate line GL, to thereby keep a pixel signal charged in the liquid crystal cell 7 .

The liquid crystal cell 7 can be equivalently expressed as a liquid crystal capacitor. The liquid crystal cell 7 includes a pixel electrode connected to a common electrode and a thin film transistor with a liquid crystal therebetween. Further, the liquid crystal cell 7 includes a storage capacitor for the purpose of maintaining the charge of the pixel signal until the next pixel signal is charged. This storage capacitor is provided between the pixel electrode and the pre-stage gate line. Such a liquid crystal cell 7 varies an alignment state of the liquid crystal, which has a dielectric anisotropy, in accordance with a pixel signal charged through the thin film transistor TFT to control a light transmittance, thereby implementing gray scale levels.

The timing controller 8 generates gate control signals (i.e., GSP, GSC and GOE) and data control signals (i.e., SSP, SSC, SOE and POL) using synchronizing signals V and H supplied from a video card (not illustrated). The gate control signals (i.e., GSP, GSC and GOE) are applied to the gate driver 6 to control the gate driver 6 while the data control signals (i.e., SSP, SSC, SOE and POL) are applied to the data driver 4 to control the data driver 4 . Further, the timing controller 8 aligns red (R), green (G) and blue (B) pixel data VD and applies them to the data driver 4 .

The gate driver 6 drives the gate lines GL 1 to GLn sequentially. To achieve this, the gate driver 6 includes a plurality of gate integrated circuits (IC's) 10 as illustrated in FIG. 2A . The gate IC's 10 sequentially drive the gate lines GL 1 to GLn connected thereto under control of the timing controller 8 . In other words, the gate IC's 10 sequentially apply a gate high voltage VGH to the gate lines GL 1 to GLn in response to the gate control signals (i.e., GSP, GSC and GOE) from the timing controller 8 .

More specifically, the gate driver 6 shifts a gate start pulse GSP in response to a gate shift clock GSC to generate a shift pulse. Then, the gate driver 6 applies a gate high voltage VGH to the corresponding gate line GL every horizontal period in response to the shift pulse. In other words, the shift pulse is shifted line-by-line every horizontal period, and any one of the gate IC's 10 applies the gate high voltage VGH to the corresponding gate line GL in correspondence with the shift pulse. In particular, the gate IC's supply a gate low voltage VGL in the interval remaining when the gate high voltage VGH is not supplied to the gate lines GL 1 to GLn.

The data driver 4 applies pixel signals for each one line to the data lines DL 1 to DLm every horizontal period. To achieve this, the data driver 4 includes a plurality of data IC's 16 as illustrated in FIG. 2B . The data IC's 16 apply pixel signals to the data lines DL 1 to DLm in response to data control signals (i.e., SSP, SSC, SOE and POL) from the timing controller 8 . In particular, the data IC's 16 convert pixel data VD from the timing controller 8 into analog pixel signals using a gamma voltage from a gamma voltage generator (not illustrated).

More specifically, the data IC's 16 shift a source start pulse SSP in response to a source shift clock SSC to generate sampling signals. Then, the data. IC's 16 sequentially latch the pixel data VD for a certain unit in response to the sampling signals. Thereafter, the data IC's 16 convert the latched pixel data VD for one line into analog pixel signals and apply them to the data lines DL 1 to DLm in an enable interval of a source output enable signal SOE. In particular, the data IC's 16 convert the pixel data VD into positive or negative pixel signals in response to a polarity control signal POL.

To accomplish this, as illustrated in FIG. 3 , each of the data IC's 16 includes a shift register part 34 for applying sequential sampling signals, a latch part 36 for sequentially latching the pixel data VD in response to the sampling signals to output them simultaneously, a digital-to-analog converter (DAC) 38 for converting the pixel data VD from the latch part 38 into pixel voltage signals, and an output buffer part 46 for buffering pixel voltage signals from the DAC 38 to output them. Further, the data IC 16 includes a signal controller 20 for interfacing various control signals (i.e., SSP, SSC, SOE, REV and POL, etc.) from the timing controller 8 and the pixel data VD, and a gamma voltage part 32 for supplying positive and negative gamma voltages required for the DAC 38 .

The signal controller 20 controls various control signals (i.e., SSP, SSC, SOE, REV and POL, etc.) from the timing controller 8 and the pixel data VD in order to output them to the corresponding elements.

The gamma voltage part 32 subdivides a plurality of gamma reference voltages inputted from a gamma reference voltage generator (not illustrated) for each gray level to output them.

Shift registers included in the shift register part 34 sequentially shift a source start pulse SSP from the signal controller 20 in response to a source sampling clock signal SSC to output it as a sampling signal.

The latch part 36 sequentially samples the pixel data VD from the signal controller 20 for a certain unit in response to the sampling signals from the shift register part 34 to latch them. To achieve this, the latch part 36 is comprised of i latches (wherein i is an integer) so as to latch i pixel data VD, and each of latches has a dimension corresponding to the bit number of the pixel data VD. Particularly, the timing controller 8 divides the pixel data VD into even pixel data VDeven and odd pixel data VDodd so as to reduce a transmission frequency and simultaneously outputs them through each transmission line. Herein, each of the even pixel data VDeven and the odd pixel data VDodd includes red(R), green(G) and blue(B) pixel data. Thus, the latch part 36 simultaneously latches the even pixel data VDeven and the odd pixel data VDodd supplied via the signal controller 20 for each sampling signal. Then, the latch part 36 simultaneously outputs i latched pixel data VD in response to a source output enable signal SOE from the signal controller 20 .

In particular, the latch part 36 restores pixel data VD modulated such that the transition bit number is reduced in response to a data inversion selection signal REV to output them. The timing controller 8 modulates the pixel data VD such that the number of transition bits are minimized using a reference value to determine whether the bits should be inverted: or not. This minimizes an electromagnetic interference (EMI) upon data transmission due to a minimal number of bit transitions from LOW to HIGH or HIGH to LOW.

The DAC 38 simultaneously converts the pixel data VD from the latch part 36 into positive and negative pixel voltage signals to output them. To achieve this, the DAC 38 includes a positive (P) decoding part 40 and a negative (N) decoding part 42 commonly connected to the latch part 36 , and a multiplexer (MUX) part 44 for selecting output signals of the P decoding part 40 and the N decoding part 42 .

A number n of P decoders included in the P decoding part 40 convert n pixel data inputted simultaneously from the latch part 36 into positive pixel voltage signals using positive gamma voltages from the gamma voltage part 32 . A number i of N decoders included in the N decoding part 42 convert i pixel data inputted simultaneously from the latch part 36 into negative pixel voltage signals using negative gamma voltages from the gamma voltage part 32 . A number i of multiplexers included in the multiplexer part 44 selectively output the positive pixel voltage signals from the P decoder 40 or the negative pixel voltage signals from the N decoder 42 in response to a polarity control signal POL from the signal controller 20 .

A number i output buffers included in the output buffer part 46 are comprised of voltage followers, etc. connected, in series, to the respective i data lines DL 1 to DLi. Such output buffers buffer pixel voltage signals from the DAC 38 to apply them to the data lines DL 1 to DLi.

Such an LCD differentiates output channels of the data IC's 16 included in the data driver 4 depending upon a resolution of the liquid crystal display panel 2 . This is because the data IC's 16 that have certain channels being connectable to the data lines DL for each resolution of the liquid crystal display panel 2 are differentiated from other. Thus, because a different number of data IC's 16 having different output channels for each resolution of the liquid crystal display panel 2 need to be used. This reduces working efficiency and increases manufacturing cost.

More specifically, for a liquid crystal display having a resolution of an eXtended Graphics Array (XGA) display with 3072 data lines DL (1024 horizontal pixels×3 colors, red, green, and blue), it requires four data IC's 16 , each of which has 768 data output channels. For a liquid crystal display having a resolution of a Super eXtended Graphics Adapter+ (SXGA+) display with 4200 data lines DL (1400 horizontal pixels×3 colors, red, green, and blue)), it requires six data IC's 16 , each of which has 702 data output channels. In this case, the remaining 12 data output channels are dummy lines. For a liquid crystal display having a resolution of a Wide eXtended Graphics Array (WXGA) display with 3840 data lines DL (1280 horizontal pixels×3 colors, red green, and blue), it requires six data IC's 16 , each of which has 642 data output channels. In this case, the remaining 12 data output channels are dummy lines.

As mentioned above, a different data IC's 16 having a specific number of output channels have to be used for each resolution type of the related art liquid crystal display panel 2 . As a result, the related liquid crystal display has a reduced working efficiency and manufacturing cost is increased.

Accordingly, the present invention is directed to a liquid crystal display device that substantially obviates one or more problems due to limitations and disadvantages of the related art.

Accordingly, the present invention to provide a liquid crystal display device with improved working efficiency as well as reduced manufacturing cost.

Another advantage of the present invention is to a liquid crystal display device that is capable of controlling output channels of data integrated circuits based upon a resolution type of a liquid crystal display panel.

To achieve these and other advantages of the invention, a liquid crystal display device according to an embodiment of the present invention includes a data integrated circuit having a data output group for supplying pixel data to data lines and provided with a dummy output channel group; a channel selector for selecting an output channel of the data output channel group; and a tape carrier package mounted with the data integrated circuit and having a data output pad group connected to the data output channel group and a dummy data output pad group, wherein said pixel data is applied, via the data output channels selected by the channel selector, to the data lines.

A liquid crystal display device according to another embodiment of the present invention includes a data integrated circuit having first and second data output channel groups for supplying pixel data to data lines and having a dummy output channel group located between the first and second data output channel groups; a channel selector for selecting output channels of the data output channel groups; and a tape carrier package mounted with the data integrated circuit and having first and second data output pad groups connected to the first and second data output channel groups, wherein said pixel data is applied, via the data output channels elected by the channel selector, to the data lines.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

The accompanying drawings, which are included to provide a further understanding: of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.

In the drawings:

FIG. 1 is a block circuit diagram illustrating a related art liquid crystal display;

FIG. 2A illustrates gate integrated circuits included in a related art gate driver;

FIG. 2B illustrates data integrated circuits included in a related art data driver;

FIG. 3 is a block diagram illustrating an internal configuration of the data integrated circuit in FIG. 2B ;

FIG. 4 is a block circuit diagram illustrating a liquid crystal display according to a first embodiment of the present invention;

FIG. 5 illustrates a data integrated circuit set to have 600 data output channels in accordance with first and second output selection signals illustrated in FIG. 4 ;

FIG. 6 illustrates a data integrated circuit set to have 618 data output channels in accordance with first and second output selection signals illustrated in FIG. 4 ;

FIG. 7 illustrates a data integrated circuit set to have 630 data output channels in accordance with first and second output selection signals illustrated in FIG. 4 ;

FIG. 8 illustrates a data integrated circuit set to have 642 data output channels in accordance with first and second output selection signals illustrated in FIG. 4 ;

FIG. 9 is a block diagram illustrating an internal configuration of the data integrated circuit in FIG. 4 ;

FIG. 10 illustrates the data tape carrier package illustrated in FIG. 4 ;

FIG. 11 illustrates the data tape carrier package attached onto the liquid crystal display panel illustrated in FIG. 4 ;

FIG. 12 illustrates the data pad part of the liquid crystal display panel illustrated in FIG. 11 ;

FIG. 13 illustrates a data integrated circuit of a liquid crystal display according to a second embodiment of the present invention;

FIG. 14 illustrates a data integrated circuit set to have 600 data output channels in accordance with first and second output selection signals illustrated in FIG. 13 ;

FIG. 15 illustrates a data integrated circuit set to have 618 data output channels in accordance with first and second output selection signals illustrated in FIG. 13 ;

FIG. 16 illustrates a data integrated circuit set to have 630 data output channels in accordance with first and second output selection signals illustrated in FIG. 13 ;

FIG. 17 illustrates a data integrated circuit set to have 642 data output channels in accordance with first and second output selection signals illustrated in FIG. 13 ;

FIG. 18 illustrates a data tape carrier package mounted with the data integrated circuit of the liquid crystal display according to the second embodiment of the present invention illustrated in FIG. 13 ;

FIG. 19 illustrates a liquid crystal display panel onto which the data tape carrier package illustrated in FIG. 13 is attached;

FIG. 20 illustrates the data pad part of the liquid crystal display panel illustrated in FIG. 19 ;

FIG. 21 illustrates a differently-shaped data tape carrier package mounted with the data integrated circuit of the liquid crystal display according to the second embodiment of the present invention illustrated in FIG. 13 ;

FIG. 22 illustrates a liquid crystal display panel onto which the data tape carrier package illustrated in FIG. 21 is attached; and

FIG. 23 illustrates the data pad part of the liquid crystal display panel illustrated in FIG. 22 .

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings.

FIG. 4 schematically shows a liquid crystal display (LCD) according to a first exemplary embodiment of the present invention. It is understood that the present invention contemplates embodiments other than those discussed herein as well.

Referring to FIG. 4 , the LCD includes a liquid crystal display panel 102 having liquid crystal cells arranged in a matrix type, a gate driver 106 for driving gate lines GL 1 to GLn of the liquid crystal display panel 102 , a data driver 104 for driving data lines DL 1 to DLm of the liquid crystal display panel 102 , and a timing controller 108 for controlling the gate driver 106 and the data driver 104 .

The liquid crystal display panel 102 includes a thin film transistor TFT provided at each intersection between the gate lines GL 1 to GLn and the data lines DL 1 to DLm, and a liquid crystal cell (not illustrated) connected to the thin film transistor TFT. The thin film transistor TFT is turned on when it is supplied with a scanning signal, that is, a gate high voltage VGH from the gate line GL, to apply a pixel signal from the data line DL to the liquid crystal cell. Further, the thin film transistor TFT is turned off when it is supplied with a gate low voltage VGL from the gate line GL. The pixel signal remains charged in the liquid crystal cell.

The liquid crystal cell can be equivalently expressed as a liquid crystal capacitor. The liquid crystal cell includes a pixel electrode connected with a common electrode and a thin film transistor with a liquid crystal therebetween. Further, the liquid crystal cell includes a storage capacitor for the purpose of maintaining the charged pixel signal until the next pixel signal is charged. This storage capacitor is provided between the pixel electrode and the pre-stage gate line. Such a liquid crystal cell 7 varies an alignment state of the liquid crystal having a dielectric anisotropy in accordance with a pixel signal charged through the thin film transistor TFT to control a light transmittance, thereby implementing gray scale levels.

The timing controller 108 generates gate control signals (i.e., GSP, GSC and GOE) and data control signals (i.e., SSP, SSC, SOE and POL) using synchronizing signals V and H supplied from a video card (not illustrated). The gate control signals (i.e., GSP, GSC and GOE) are applied to the gate driver 106 to control the gate driver 106 while the data control signals (i.e., SSP, SSC, SOE and POL) are applied to the data driver 104 to control the data driver 104 . Further, the timing controller 108 aligns pixel data VD and applies them to the data driver 104 .

The gate driver 106 sequentially drives the gate lines GL 1 to GLn. To achieve this, the gate driver 106 includes a plurality of gate integrated circuits (IC's) (not illustrated). The gate IC's sequentially drive the gate lines GL 1 to GLn connected thereto under control of the timing controller 108 . In other words, the gate IC's sequentially apply a gate high voltage VGH to the gate lines GL 1 to GLn in response to the gate control signals (i.e., GSP, GSC and GOE) from the timing controller 108 .

More specifically, the gate driver 106 shifts a gate start pulse GSP in response to a gate shift clock GSC to generate a shift pulse. Then, the gate driver 106 applies a gate high voltage VGH to the corresponding gate line GL every horizontal period in response to the shift pulse. In other words, the shift pulse is shifted line-by-line every horizontal period, and any one of the gate IC's applies the gate high voltage VGH to the corresponding gate line GL in accordance with the shift pulse. In particular, the gate IC's supply a gate low voltage VGL in the remaining gate lines.

The data driver 104 applies pixel signals to the data lines DL 1 to DLm one at a time every horizontal period. To achieve this, the data driver 104 includes a plurality of data IC's 116 . Each of the data IC's 116 is mounted in a data tape carrier package (TCP) 110 . Such data IC's 116 are electrically connected, via a data TCP pad 112 , a data pad 114 and a link 118 , to the data lines DL 1 to DLm. The data IC's 116 apply pixel signals to the data lines DL 1 to DLm in response to data control signals (i.e., SSP, SSC, SOE and POL) from the timing controller 108 . In particular, the data IC's 116 convert pixel data VD from the timing controller 108 into analog pixel signals using gamma voltages from a gamma voltage generator (not illustrated).

More specifically, the data IC's 116 shift a source start pulse SSP in response to a source shift clock SSC to generate sampling signals. Then, the data IC's 116 sequentially latch the pixel data VD for a certain unit in response to the sampling signals. Thereafter, the data IC's 16 convert the latched pixel data VD for one line into analog pixel signals, and apply them to the data lines DL 1 to DLm in an enable interval of a source output enable signal SOE. In particular, the data IC's 116 convert the pixel data VD into positive or negative pixel signals in response to a polarity control signal POL.

Meanwhile, each of the data IC's 116 of the LCD according to the first embodiment of the present invention varies an output channel for applying a pixel signal to each data line DL 1 to DLm in response to first and second channel selection signals P 1 and P 2 input from the exterior thereof. To achieve this, each of the data IC's 116 includes first and second option pins OP 1 and OP 2 , for example, supplied with the first and second channel selection signals P 1 and P 2 .

Each of the first and second option pins OP 1 and OP 2 is selectively connected to a voltage source VCC and a ground voltage source GND to have a 2-bit binary logical value. Thus, the first and second channel selection signals P 1 and P 2 apply, via the first and second option pins OP 1 and OP 2 , logical values of ‘00’, ‘01’, ‘10’ and ‘11’ to the data IC 116 .

Accordingly, each of the data IC's 116 has the number of output channel set in advance depending on a resolution of the liquid crystal display panel 102 using first and second channel selection signals P 1 and P 2 applied via the first and second option pins OP 1 and OP 2 .

The number of data IC's 116 according to output channels of the data IC's 116 depending upon a resolution of the liquid crystal display panel 102 is described in the following Table:

Referring to the above Table 1, it can be seen that all resolutions can be expressed by four channels. More specifically, the liquid crystal display panel 102 having a resolution of XGA requires five data IC's 116 , each of which has 618 data output channels. In particular, the remaining 18 data output channels are treated into dummy lines. The liquid crystal display panel 102 having a resolution of SXGA+ requires seven data IC's 116 , each of which has 600 data output channels. The liquid crystal display panel 102 having a resolution of Ultra eXtended Graphics Adapter (UXGA) requires eight data IC's 116 , each of which has 600 data output channels. The liquid crystal display panel 102 having a resolution of WXGA requires six data IC's 116 , each of which has 642 data output channels. The liquid crystal display panel 102 having a resolution of Wide aspect Super eXtended Graphics Adapter—(WSXGA-) requires seven data IC's 116 , each of which has 618 data output channels. The liquid crystal display panel 102 having a resolution of Wide aspect Super eXtended Graphics Adapter (WSXGA) requires eight data IC's 116 , each of which has 630 data output channels. The liquid crystal display panel 102 having a resolution of Wide aspect Ultra eXtended Graphics Adapter (WUXGA) requires nine data IC's 116 , each of which has 642 data output channels.

Accordingly, the LCD according to the first embodiment of the present invention sets the number of output channels of the data IC's 116 into any one of 600 channels, 618 channels, 630 channels and 642 channels in response to the first and second channel selection signals P 1 and P 2 , thereby expressing all resolutions of the liquid crystal display panel 102 . In other words, the data IC 116 of the LCD according to the first embodiment of the present invention may be made to have 642 data output channels and the number of active output channels of the data IC's 116 set in response to the first and second channel selection signals P 1 and P 2 from the first and second option pins OP 1 and OP 2 , for example, so that it can be compatibly used for all resolution of the liquid crystal display panel 102 .

More specifically, the data IC 116 of the LCD according to the first embodiment of the present invention is manufactured to have 642 data output channels. When a value of the first and second channel selection signals P 1 and P 2 applied to the data IC 116 is ‘00’ by connecting each of the first and second option pins OP 1 and OP 2 to the ground voltage source GND, the data IC 116 outputs pixel voltage signals via the 1st to 600th data output channels from 642 data output channels available as illustrated in FIG. 5 . In particular, the 601st to 642nd output channels become dummy output channels.

When a value of the first and second channel selection signals P 1 and P 2 applied to the data IC 116 is ‘01’ by connecting the first option pin OP 1 to the ground voltage source GND and the second option pin OP 2 to the voltage source VCC, the data IC 116 outputs pixel voltage signals via the 1st to 618th data output channels of 642 data output channels as illustrated in FIG. 6 . In this case, the 619th to 642nd output channels become dummy output channels.

When a value of the first and second channel selection signals P 1 and P 2 applied to the data IC 116 is ‘10’ by connecting the first option pin OP 1 to the voltage source VCC and the second option pin OP 2 to the ground voltage source GND, the data IC 116 only outputs pixel voltage signals via the 1st to 630th data output channels of 642 data output channels as illustrated in FIG. 7 . In particular, the 631st to 642nd output channels become dummy output channels. Finally, when a value of the first and second channel selection signals P 1 and P 2 applied to the data IC 116 is ‘11’ by connecting each of the first and second option pins OP 1 and OP 2 are connected to the voltage source VCC, the data IC 116 outputs pixel voltage signals via the 1st to 642nd data output channels as illustrated in FIG. 8 .

Accordingly, as illustrated in FIG. 9 , the data IC 116 of the LCD according to the first embodiment of the present invention includes a channel selector 130 for setting an output channel of the data IC 116 in response to the first and second channel selection signals P 1 and P 2 applied to the first and second option pins OP 1 and OP 2 , for example, a shift register part 130 for applying sequential sampling signals, a latch part 134 for sequentially latching the pixel data VD in response to the sampling signals to output them simultaneously, a digital-to-analog converter (DAC) 138 for converting the pixel data VD from the latch part 136 into pixel voltage signals, and an output buffer part 146 for buffering pixel voltage signals from the DAC 138 to output them.

Further, the data IC 116 includes a signal controller 120 for interfacing with various control signals from the timing controller 108 and the pixel data VD, and a gamma voltage part 132 for supplying positive and negative gamma voltages required for the DAC 138 .

The signal controller 120 controls various control signals (i.e., SSP, SSC, SOE, REV and POL, etc.) from the timing controller 108 and the pixel data VD so as to output them to the corresponding elements.

The gamma voltage part 132 sub-divides a plurality of gamma reference voltages inputted from a gamma reference voltage generator (not illustrated) for each gray level.

The channel selector 130 applies first to fourth channel control signals CS 1 to CS 3 , via the first and second option pins OP 1 and OP 2 , to the shift register part 134 in response to the first and second channel selection signals P 1 and P 2 . In other words, the channel selector 130 generates the first channel selection signal CS 1 corresponding to the first and second channel selection signals P 1 and P 2 having a value of ‘00’, the second channel selection signal CS 2 corresponding to the first and second channel selection signals P 1 and P 2 having a value of ‘01’, the third channel selection signal CS 3 corresponding to the first and second channel selection signals P 1 and P 2 having a value of ‘10’, and the fourth channel selection signal CS 4 corresponding to the first and second channel selection signals P 1 and P 2 having a value of ‘11’.

Shift registers included in the shift register part 134 sequentially shift a source start pulse SSP from the signal controller 120 in response to a source sampling clock signal SSC and outputs sampling signals. In this example, the shift register part 134 consists of 642 shift registers SR 1 to SR 642 .

Such a shift register part 134 applies output signals of the 600th, 618th, 630th and 642nd shift registers SR 600 , SR 628 , SR 630 and SR 642 to the next stage data IC 116 in response to the first to fourth channel control signals CS 1 to CS 4 from the channel selector 130 .

For example, when the first output control signal CS 1 is applied from the channel selector 130 , the shift register part 134 sequentially shifts a source start pulse SSP from the signal controller 120 in response to a source sampling clock signal SSC using the 1st to 600th shift registers SR 1 to SR 600 , and outputs them as sampling signals. In particular, an output signal (i.e., a carry signal) of the 600th shift register SR 600 is applied to the 1st shift register SR 1 of the next stage data IC 116 (for a daisy chain connection). Thus, the 601st to 642nd shift registers SR 601 to SR 642 do not output sampling signals. Herein, if the shift registers are driven in a bilateral direction, then it becomes possible to use more advantageously them by making a dummy treatment without employing 42 middle channels.

When the second output control signal CS 2 is applied from the channel selector 130 , the shift register part 134 sequentially shifts a source start pulse SSP from the signal controller 120 in response to a source sampling clock signal SSC using the 1st to 618th shift registers SR 1 to SR 618 , and outputs them as sampling signals. In particular, an output signal (i.e., a carry signal) of the 618th shift register SR 618 is applied to the 1st shift register SR 1 of the next stage data IC 116 . Thus, the 619th to 642nd shift registers SR 619 to SR 642 do not output sampling signals.

When the third output control signal CS 3 is applied from the channel selector 130 , the shift register part 134 sequentially shifts a source start pulse SSP from the signal controller 120 in response to a source sampling clock signal SSC using the 1st to 630th shift registers SR 1 to SR 630 , and outputs them as sampling signals. In particular, an output signal (i.e., a carry signal) of the 630th shift register SR 630 is applied to the 1st shift register SR 1 of the next stage data IC 116 . Thus, the 631st to 642nd shift registers SR 601 to SR 642 do not output sampling signals. Herein, if the shift registers are driven in a bilateral direction, then it becomes possible to use more advantageously them by making a dummy treatment without employing 12 middle channels.

When the fourth output control signal CS 4 is applied from the channel selector 130 , the shift register part 134 sequentially shifts a source start pulse SSP from the signal controller 120 in response to a source sampling clock signal SSC using the 1st to. 642nd shift registers SR 1 to SR 642 , and outputs them as sampling signals. In particular, an output signal (i.e., a carry signal) of the 642nd shift register SR 642 is applied to the 1st shift register SR 1 of the next stage data IC 116 .

The latch part 136 sequentially samples the pixel data VD from the signal controller 120 for a certain unit in response to the sampling signals from the shift register part 134 to latch them. To achieve this, the latch part 136 is comprised of at most 642 latches so as to latch 642 pixel data VD, and each of the latches has a dimension corresponding to the number of bits of the pixel data VD. Particularly, the timing controller 108 divides the pixel data VD into even pixel data VDeven and odd pixel data VDodd so as to reduce a transmission frequency, and simultaneously outputs them through each transmission line. Herein, each of the even pixel data VDeven and the odd pixel data VDodd includes red(R), green(G) and blue(B) pixel data.

Thus, the latch part 136 simultaneously latches the even pixel data VDeven and the odd pixel data VDodd supplied via the signal controller 120 for each sampling signal. Then, the latch part 136 simultaneously outputs the pixel data VD through the selected number of output channels (600, 618, 630 or 642 data output channels) in response to a source output enable signal SOE from the signal controller 120 . In particular, the latch part 136 restores pixel data VD which have been modulated such that the transition bit number is reduced in response to a data inversion selection signal REV. The timing controller 8 modulates the pixel data VD such that the number of transition bits are minimized using a reference value due to determine whether the bits should be inverted or not. This minimizes an electromagnetic interference (EMI) upon data transmission due to a minimal number of bit transitions from LOW to HIGH or HIGH to LOW.

The DAC 138 simultaneously converts the pixel data VD from the latch part 136 into positive and negative pixel voltage signals and outputs them. To achieve this, the DAC 138 includes a positive (P) decoding part 140 and a negative (N) decoding part 142 commonly connected to the latch part 136 , and a multiplexer (MUX) part 144 for selecting output signals of the P decoding part 140 and the N decoding part 142 .

A number n of P decoders included in the P decoding part 140 convert n pixel data inputted simultaneously from the latch part 136 into positive pixel voltage signals using positive gamma voltages from the gamma voltage part 132 . A number i of N decoders included in the N decoding part 142 convert i pixel data inputted simultaneously from the latch part 136 into negative pixel voltage signals using negative gamma voltages from the gamma voltage part 132 . In this example, at most 642 multiplexers included in the multiplexer part 144 selectively outputs the positive pixel voltage signals from the P decoder 140 or the negative pixel voltage signals from the N decoder 142 in response to a polarity control signal POL from the signal controller 120 .

At most 642 output buffers included in the output buffer part 146 are comprised of voltage followers, etc. connected, in series, to the respective 642 data lines DL 1 to DL 642 . Such output buffers buffer pixel voltage signals from the DAC 138 to apply them to the data lines DL 1 to DL 642 .

In the LCD according to the first embodiment of the present invention, the data IC 116 having 600 data output channels is used for the liquid crystal display panel 102 having SXGA+ resolution or UXGA resolution; the data IC 116 having 618 data output channels is used for the liquid crystal display panel 102 having XGA or WSXGA resolution; the data IC 116 having 630 data output channels is used for the liquid crystal display panel 102 having WSXGA resolution; and the data IC 116 having 642 data output channels is used for the liquid crystal display panel 102 having WXGA or WUXGA resolution WXGA or WUXGA as indicated in the above Table 1.

The data IC 116 of the LCD according to a first embodiment of the present invention is mounted in the data TCP 110 as illustrated in FIG. 10 .

The data TCP 110 is provided with input pads connected to a data printed circuit board (not illustrated) and a data output pad group 160 and a dummy data output pad group 164 connected to the liquid crystal display panel 102 . In particular, a sum of the pad number of the data output pad group 160 provided at the data TCP 110 with the pad number of the dummy data output pad group 164 becomes equal to the output channel number of the data IC 116 .

The data output pad group 160 is connected, via a signal wiring provided at the data TCP 110 , to the data output channel group of the data IC 116 . The pad number of the data output pad group 160 is equal to the output channel number of the data IC 116 selected by the first and second channel selection signals P 1 and P 2 . For instance, if the output channels of the data IC 116 are selected as 600 data output channels of 642 data output channels by the first and second channel selection signals P 1 and P 2 as mentioned above, then the data output pad group 160 of the data TCP 110 also has 600 output pads.

The dummy data output pad group 164 becomes equal to output channels of the remaining data IC 116 excluding the output channels of the data IC 116 selected by the first and second channel selection signals P 1 and P 2 . For instance, if the output channels of the data IC 116 are selected into 600 data output channels of 642 data output channels by the first and second channel selection signals P 1 and P 2 as mentioned above, then the dummy data output pad group 164 of the data TCP 110 has 42 dummy output pads.

Such a data TCP 110 is attached to a data pad part 186 provided on the lower substrate of the liquid crystal display panel 102 illustrated in FIG. 11 .

The data pad part 186 is provided with a data input pad group 180 to which the data output pad group 160 of the data TCP 110 is attached and a dummy data input pad group 184 to which the dummy data output pad group 164 of the data TCP 110 is attached as illustrated in FIG. 12 .

The number of pads in the data input pad group 180 becomes equal to that of the data output pad group 160 of the data TCP 110 . Each pad of the data input pad group 180 is connected, via a link 118 , to the data lines DL.

In an LCD according to the first embodiment of the present invention, the data output pad group 160 of the data TCP 110 and the data input pad group 180 of the liquid crystal display panel 102 are designed equally in such a manner to correspond to the output channels of the data IC 116 varied in response to the first and second output selection signals P 1 and P 2 as mentioned above.

As described above, the LCD according to the first embodiment of the present invention sets the output channels of the data IC 116 in accordance with a resolution of the liquid crystal display panel 102 as indicated in the above Table 1 in response to the first and second channel selection signals P 1 and P 2 applied to the first and second option pins OP 1 and OP 2 , thereby configuring multiple resolutions using only one type data IC 116 . Accordingly, the LCD according to the first embodiment of the present invention is capable of improving working efficiency as well as reducing a manufacturing cost.

FIG. 13 is a block diagram illustrating a configuration of a data IC in a liquid crystal display according to a second embodiment of the present invention.

Referring to FIG. 13 , the LCD according to the second embodiment of the present invention has the same elements as the LCD according to the first embodiment of the present invention except for a data IC 416 . Therefore, in the LCD according to the second embodiment of the present invention, the data IC 416 only will be described in conjunction with FIG. 13 and FIG. 4 , but an explanation as to other elements will be omitted. Herein, a reference numeral “ 116 ” of the data IC illustrated in FIG. 4 will be replaced by a reference numeral “ 416 ” illustrated in FIG. 13 .

In the LCD according to the second embodiment of the present invention, the data IC 416 includes a first data output channel group 260 and a second data output channel group 262 for always applying a data to the data lines DL 1 to DLm, and a dummy output channel group 264 provided between the first and second data output channel groups 260 and 262 .

Such a data IC 416 includes first and second option pins OP 1 and OP 2 supplied with first and second channel selection signals P 1 and P 2 for determining whether or not pixel data that is applied, via a dummy data output channel group 264 , to the data lines DL 1 to DLm in accordance with the number of the data lines DL 1 to DLm is outputted.

Each of the first and second option pins OP 1 and OP 2 is selectively connected to a voltage source VCC and a ground voltage source GND to have a 2-bit binary logical value. Thus, the first and second channel selection signals P 1 and P 2 applied, via the first and second option pins OP 1 and OP 2 , to the data IC 416 have values of ‘00’, ‘01’, ‘10’ and ‘11’.

Accordingly, each of the data IC's 416 has output channels set in advance depending upon a resolution of the liquid crystal display panel 102 in response to the first and second channel selection signals P 1 and P 2 applied via the first and second option pins OP 1 and OP 2 .

The number of data IC's 416 according to output channels of the data IC's 416 depending upon a resolution of the liquid crystal display panel 102 is as indicated in the above Table 1.

Accordingly, the LCD according to the second embodiment of the present invention sets output channels of the data IC's 416 into any one of 600 channels, 618 channels, 630 channels and 642 channels in response to the first and second channel selection signals P 1 and P 2 , thereby expressing all resolutions of the liquid crystal display panel 102 . In other words, the data IC 416 of the LCD according to the second embodiment of the present invention is made to have 642 data output channels, and output channels of the data IC's 416 are set in response to the first and second channel selection signals P 1 and P 2 from the first and second option pins OP 1 and OP 2 , so that it can be compatibly used for all resolution types of the liquid crystal display panel 102 . Further, the LCD according to the second embodiment of the present invention arranges the dummy data output channel group 264 of the data IC 416 according to a determination of the output channel at the middle portion of data output channels of the data IC 416 . In other words, first and second data output channel groups 260 and 262 of the data IC 416 have the same output channels with having the dummy data output channel group 264 therebetween. Thus, the LCD according to the second embodiment of the present invention equalizes output channels of each of the first and second data output channel groups 260 and 262 of the data IC 416 , thereby reducing an electro-magnetic interference upon output of the pixel data.

More specifically, the data IC 416 of the LCD according to the second embodiment of the present invention is manufactured to have 642 data output channels.

When a value of the first and second channel selection signals P 1 and P 2 applied to the data IC 416 is ‘00’ by connecting each of the first and second option pins OP 1 and OP 2 to the ground voltage source GND, the data IC 416 outputs pixel data 416 outputs pixel data via the first data output channel group 260 having the 1st to 300th output channels of 642 data output channels and the second data output channel group 262 having the 343rd to 642nd output channels as illustrated in FIG. 14 . In particular, the dummy data output channel group 264 includes the 301st to 342nd output channels which are treated as dummy lines.

When a value of the first and second channel selection signals P 1 and P 2 applied to the data IC 416 is ‘01’ by connecting the first option pin OP 1 to the ground voltage source GND and the second option pin OP 2 to the voltage source VCC, the data IC 416 outputs pixel data via the first data output channel group 260 having the 1st to 309th output channels of 642 data output channels and the second data output channel group 262 having the 334th to 642nd output channels as illustrated in FIG. 15 . In particular, the dummy data output channel group 264 includes the 310th to 333rd output channels which are treated as dummy lines.

When a value of the first and second channel selection signals P 1 and P 2 applied to the data IC 416 is ‘10’, by connecting the first option pin OP 1 to the voltage source VCC and the second option pin OP 2 to the ground voltage source GND, the data IC 416 outputs pixel data via the first data output channel group 260 including the 1st to 315th output channels of 642 data output channels and the second data output channel group 262 including the 328th to 642nd output channels as illustrated in FIG. 16 . In particular, the dummy data output channel group 264 includes the 316th to 327th output channels as dummy lines.

Finally, when a value of the first and second channel selection signals P 1 and P 2 applied to the data IC 416 is ‘11’ by connecting each of the first and second option pins OP 1 and OP 2 to the voltage source VCC, the data IC 416 outputs pixel data via the first data output channel group 260 , the dummy data output channel group 264 and the second output channel group 262 , that is, via the 1st to 642nd data output channels as illustrated in FIG. 17 .

Meanwhile, the data IC 416 of the LCD according to the second embodiment of the present invention is mounted in a data TCP 510 as illustrated in FIG. 18 .

The data TCP 510 is provided with input pads connected to a data printed circuit board (not illustrated) and a first data output pad group 560 and a second data output pad group 562 connected to the liquid crystal display panel 102 . In particular, the dummy data output pad group 264 of the data IC 416 mounted in the data TCP 510 is subject to a dummy treatment. In other words, the dummy data output channel group 264 of the data IC 416 is not connected to the first and second data output pads 560 and 562 .

The first data output pad group 560 is connected, via a signal wiring provided at the data TCP 510 , to the first data output channel group 260 of the data IC 416 . The pad number of the first data output pad group 560 becomes equal to the channel number of the first data output channel group 260 of the data IC 416 selected by the first and second channel selection signals P 1 and P 2 . For instance, if the output channels of the data IC 416 are selected into 600 data output channels of 642 data output channels by the first and second channel selection signals P 1 and P 2 as mentioned above, then the first data output pad group 560 of the data TCP 510 also has the 1st to 300th output pads.

The second data output pad group 562 is connected, via a signal wiring provided at the data TCP 510 , to the second data output channel group 262 of the data IC 416 . The pad number of the second data output pad group 562 becomes equal to the channel number of the second data output channel group 262 of the data IC 416 selected by the first and second channel selection signals P 1 and P 2 . For instance, if the output channels of the data IC 416 are selected into 600 data output channels of 642 data output channels by the first and second channel selection signals P 1 and P 2 as mentioned above, then the second data output pad group 562 of the data TCP 510 also has the 300th to 600th output pads.

Such a data TCP 510 is attached to a data pad part 586 provided on the lower substrate of the liquid crystal display panel 102 illustrated in FIG. 19 .

The data pad part 586 is provided with a data input pad group 580 to which the first data output pad group 560 and the second data output pad group 562 of the data TCP 510 is attached as illustrated in FIG. 20 .

The pad number of the data input pad group 580 becomes equal to that of the first and second data output pad groups 560 and 562 of the data TCP 510 . Each pad of the data input pad group 580 is connected, via a link 518 , to the data lines DL.

In such an LCD according to the second embodiment of the present invention, the first and second data output pad groups 560 and 562 of the data TCP 510 and the data input pad group 580 of the liquid crystal display panel 102 are designed equally in such a manner to correspond to the output channels of the data IC 416 varied in response to the first and second output selection signals P 1 and P 2 as mentioned above.

As described above, the LCD according to the second embodiment of the present invention sets the output channels of the data IC 416 in accordance with a resolution of the liquid crystal display panel 102 in response to the first and second channel selection signals P 1 and P 2 applied to the first and second option pins OP 1 and OP 2 , as indicated in the above Table 1. This way, all resolutions may be displayed based only on the data IC 416 . Accordingly, the LCD according to the second embodiment of the present invention is capable of improving operating efficiency as well as reducing the manufacturing cost.

Alternatively, the data IC 416 of the LCD according to the second embodiment of the present invention is mounted in a data TCP 610 as illustrated in FIG. 21 .

The data TCP 610 is provided with input pads connected to a data printed circuit board (not illustrated), a first data output pad group 660 and a second data output pad group 662 connected to the liquid crystal display panel 102 , and a dummy data output pad group 664 provided between the first and second data output pad groups 660 and 662 . In particular, the number of data output pads provided at the data TCP 610 becomes equal to that of output channels of the data IC 416 .

The first data output pad group 660 is connected, via a signal wiring provided at the data TCP 610 , to the first data output channel group 260 of the data IC 416 . The number of pads of the first data output pad group 660 becomes equal to the number of channels of the first data output channel group 260 of the data IC 416 selected by the first and second channel selection signals P 1 and P 2 . For example, if the output channels of the data IC 416 are determined to be 600 data output channels out of 642 data output channels by the first and second channel selection signals P 1 and P 2 as mentioned above, then the first data output pad group 660 of the data TCP 610 also has 300 output pads (i.e., the 1st to 300th output pads).

The second data output pad group 662 is connected, via a signal wiring provided at the data TCP 610 , to the second data output channel group 262 of the data IC 416 . The number of pads of the second data output pad group 662 becomes equal to the number of channels of the second data output channel group 262 of the data IC 416 selected by the first and second channel selection signals P 1 and P 2 . For instance, if the output channels of the data IC 416 are selected into 600 data output channels of 642 data output channels by the first and second channel selection signals P 1 and P 2 as mentioned above, then the second data output pad group 662 of the data TCP 610 also has 300 output pads (i.e., the 300th to 600th output pads).

The dummy output pad group 664 is provided between the first and second data output pad groups 660 and 662 , and is connected, via a signal wiring provided at the data TCP 610 , to the dummy data output channel group 264 of the data IC 416 . The number of pads of the dummy data output pad group 664 becomes equal to the number of channels of the dummy data output channel group 264 of the data IC 416 selected by the first and second channel selection signals P 1 and P 2 . For instance, if the output channels of the data IC 416 are selected into 600 data output channels of 642 data output channels by the first and second channel selection signals P 1 and P 2 as mentioned above, then the dummy data output pad group 664 of the data TCP 610 also has 42 dummy output pads (i.e., the 301st to 342nd output pads).

Such a data TCP 610 is attached to a data pad part 686 provided on the lower substrate of the liquid crystal display panel 102 illustrated in FIGS. 22 and 23 .

The data pad part 686 is comprised of a first data input pad group 680 to which the first data output pad group 660 of the data TCP 610 is attached, a second data input pad group 682 to which the second data output pad group 662 of the data TCP 610 is attached, and a dummy data input pad group 684 to which the dummy data output pad group 664 of the data TCP 610 is attached and provided between the first and second data input pad groups 680 and 682 .

The number of pads of the first data input pad group 680 becomes equal to that of the first data output pad group 660 of the data TCP 610 . Each pad of the first data input pad group 680 is connected, via a link 618 , to the data lines DL.

The number of pads of the second data input pad group 682 becomes equal to that of the second data output pad group 662 of the data TCP 610 . Each pad of the second data input pad group 682 is connected, via the link 618 , to the data lines DL.

The number of pads of the dummy data input pad group 684 becomes equal to that of the dummy data output pad group 664 of the data TCP 610 . Each pad of the dummy data input pad group 684 is subject to being used as a dummy. In other words, the dummy data input pad group 684 is provided between the first and second data input pad groups 680 and 682 and is not connected to the data lines DL.

In an LCD according to the second embodiment of the present invention, the first and second data output pad groups 660 and 662 and the dummy data output pad group 664 of the data TCP 610 and the first and second data input pad groups 680 and 682 and the dummy data input pad group 684 of the liquid crystal display panel 102 are designed equally in such a manner to correspond to each channel of the first and second data output channel groups 260 and 262 and the dummy data output channel group 264 of the data IC 416 varied in response to the first and second output selection signals P 1 and P 2 as mentioned above.

The LCDs according to the first and second embodiments of the present invention as described above is not limited to only those varying output channels of the data IC's 116 and 416 each having 642 data output channels in response to the first and second channel selection signals P 1 and P 2 , but is applicable to the data IC's 116 and 416 having 642 output channels or less and 642 output channels or more.

Furthermore, the output channels of the data IC's 116 and 416 set in response to the first and second channel selection signals P 1 and P 2 is not limited to only 600, 618, 630 and 642 data output channels, but is applicable to any cases. In other words, the output channels of the data IC's 116 and 416 set in response to the first and second channel selection signals P 1 and P 2 is determined depending upon any at least one of a resolution of the liquid crystal display panel 102 , the number of data TCP's, a width of the data TCP and the number of data transmission lines between the timing controller 108 and the data IC's 116 and 416 for applying the pixel data from the timing controller 108 to the data IC's 116 and 416 . Accordingly, the number of output channels of the data IC's 116 and 416 set in response to the first and second channel selection signals P 1 and P 2 may be 600, 618, 624, 630, 642, 645, 684, 696, 702 or 720, etc.

Moreover, the channel selection signals P 1 and P 2 for setting the output channels of the data IC's 116 and 416 is also not limited to a 2-bit binary logical value, but may be a binary logical value having more than two bits.

As described above, the LCD according to the present invention varies channels of the data integrated circuit in accordance with a resolution of the liquid crystal display panel using the channel selection signals, thereby driving all resolution of the liquid crystal display panel using a kind of data integrated circuit.

Furthermore, the LCD according to the present invention includes the data integrated circuit having the dummy data output channel group provided between the first and second data output channel groups for always applying a data to the data lines, and varies channels of the data integrated circuit depending upon a resolution of the liquid crystal display panel using the channel selection signals, thereby driving all resolutions of the liquid crystal display panel using a kind of data integrated circuit.

Accordingly, the LCD according to the present invention may use the data integrated circuit independently of a resolution of the liquid crystal display panel, thereby reducing the number of data integrated circuits. As a result, the LCD according to the present invention has improved operating efficiency as well as reduced manufacturing cost.

Although the present invention has been explained by the embodiments illustrated in the drawings described above, it should be understood to those skilled in the art that the invention is not limited to the above embodiments, but rather that various changes or modifications thereof are possible without departing from the spirit of the invention. Accordingly, the scope of the invention shall be determined only by the appended claims and their equivalents.