Organic electro luminescence device

The present application claims the benefit of Korean Patent Application No. 2004-0030605 filed in Korea on Apr. 30, 2004, which is hereby incorporated by reference.

1. Field of the Invention

The present invention relates to a display device, and more particularly, to an organic electro luminescence device that has an improved image quality.

2. Discussion of the Related Art

In general, an organic electro luminescence device, which also is referred to as an organic light emitting diode (OLED) device, includes a plurality of pixels and an organic light emitting diode in each of the pixels. Each of the organic light emitting diodes has a cathode electrode injecting electrons, an anode electrode injecting holes, and an organic electro-luminescence layer between the cathode and anode electrodes. Each of the organic light emitting diodes generally has a multi-layer structure of organic thin films formed between the anode electrode and the cathode electrode. When a forward current is applied to the organic thin films, electron-hole pairs (often referred to as excitons) are combined in the organic thin films as a result of a P-N junction between the anode electrode and the cathode electrode. The electron-hole pairs have a lower energy when combined together than when they were separated. Thus, the resultant energy gap between the combined and separated electron-hole pairs is converted into light by an organic electro-luminescent layer. In other words, the organic electro-luminescent layer emits the energy generated due to the recombination of electrons and holes in response to an applied current.

Thus, organic electro luminescence devices do not need an additional light source. In addition, organic electro luminescence devices are thin, light weight, and energy efficient, and have a low power consumption, high brightness, and short response time. Because of these advantageous characteristics, the organic electro luminescence devices are regarded as a promising candidate for various next-generation consumer electronic appliances, such as mobile communication devices, personal digital assistance (PDA) devices, camcorders, and palm PCs. Also, the fabrication of organic electro luminescence devices is a relatively simple process, thereby reducing fabrication costs.

An organic electro luminescence device is categorized as a passive matrix type or an active matrix type. The passive matrix type organic electro luminescence device has a relatively simple structure and fabrication process, but requires higher power in comparison to the active matrix type. In addition, the passive matrix type organic electro luminescence device has a larger size and has a poor aperture ratio as the bus lines therein increase. On the contrary, in comparison to the passive matrix type, the active matrix type organic electro luminescence device provides a higher display quality with higher luminosity.

FIG. 1 is a schematic diagram of an active matrix type organic electro luminescence device according to the related art. In FIG. 1 , an active matrix type organic electro luminescence device includes a plurality of scan lines S 1 to Sm along a first direction, and a plurality of data lines D 1 to Dn along a second direction intersecting the scan lines S 1 to Sm, thereby defining a plurality of pixel regions. An organic light emitting diode E, a switching thin film transistor (TFT) P 1 , a driving TFT P 2 , and a capacitor C 1 are formed within each of the pixel regions. The switching TFT P 1 and the driving TFT P 2 are p-type metal oxide semiconductor (PMOS) transistors. In particular, a gate and a source of the switching transistor P 1 are respectively connected to one of the scan lines S 1 to Sm and one of the data lines D 1 to Dn. A drain of the switching transistor P 1 is connected to the capacitor C 1 . A source and a drain of the driving transistor P 2 are connected to a power V DD and an anode of the organic light emitting diode E, respectively. Further, a gate of the driving transistor P 2 is connected to the drain of the switching transistor P 1 .

In addition, when a scan signal is applied to the gate of the switching transistor P 1 through the scan line S, the switching transistor P 1 is turned on. At this time, a data voltage applied to the data line D is transmitted to the capacitor C 1 through the switching transistor P 1 , thereby charging the capacitor C 1 . Thereafter, the driving transistor P 2 is operated, and then the charge stored in the capacitor C 1 determines current level that flows into the organic light emitting diode E through the driving transistor P 2 .

As a result, the organic light emitting diode E can display a gray scale between black and white. In particular, the scan lines S 1 to Sm are sequentially driven to turn on the switching transistors P 1 connected to the corresponding scan line, and then data voltages are applied to the desired data lines to operate the respective organic light emitting diode E.

FIG. 2 is a circuit diagram of a pixel region of an organic electro luminescence device according to the related art. As shown in FIG. 2 , four transistors, instead of two transistors shown in FIG. 1 , are formed in a pixel region. The four-transistor structure shown in FIG. 2 is often referred to as 4-TFT/1-CAP. In FIG. 2 , a data line D and a power line V DD are formed along a first direction, and a first scan line Sc 1 and a second scan line Sc 2 are formed along a second direction intersecting the data line D and the power line V DD , thereby defining the pixel region. First and second driving TFTs M 1 and M 2 , a organic light emitting diode E, first and second switching TFTs SW 1 and SW 2 , and a storage capacitor C st also are formed in the pixel region.

The first and second driving TFTs M 1 and M 2 receive a power voltage from the power line V DD , and the second driving TFT M 2 is connected to the organic light emitting diode E. The first and second switching TFTs SW 1 and SW 2 receive scan signals from the first and second scan lines Sc 1 and Sc 2 , respectively. The first switching TFT SW 1 receives a data signal from the data line D, and the second switching TFT SW 2 receives output signals from the first switching and driving TFTs SW 1 and M 1 . The storage capacitor C st is connected between the power line V DD and gates of the first and second driving TFTs M 1 and M 2 , and supplies a voltage to the gates of the first and second driving TFTs M 1 and M 2 to maintain the voltage signals thereof.

The first switching TFT SW 1 is an n-type metal oxide semiconductor (NMOS) transistor, and the second switching TFT SW 2 , the first driving TFT M 1 , and the second driving TFT M 2 are PMOS transistors. Further, the first and second driving TFTs M 1 and M 2 form a current mirror circuit, such that the drain current of the first driving TFT M 1 is proportional to the drain current of the second driving TFT M 2 irrespective of a load resistance value. As a result, the current mirror circuit controls the organic light emitting diode E, such that a mirror ratio (MR) of the second driving TFT M 2 and the first driving TFT M 1 controls the current level being applied to the organic light emitting diode E.

FIG. 3 is a graph showing scan signals applied to the scan lines Sc 1 and Sc 2 of FIG. 2 , and FIGS. 4A and 4B are equivalent circuit diagrams illustrating ON and OFF states of the device of FIG. 2 . As shown in FIG. 3 , a high-state scan signal is applied to the first scan line Sc 1 and a low-state scan signal is applied to the second scan line Sc 2 during a pre-charging period. In addition, the low-state scan signal of the second scan line Sc 2 is switched to a high-state at the end of a C st charging period, before the high-state scan signal of the first scan line Sc 1 is switched to a low-state.

When the high-state scan signal is applied to the first scan line Sc 1 and when the low-state scan signal is applied to the second scan line Sc 2 during the pre-charging period and during the C st charging period, the first and second switching TFTs SW 1 and SW 2 are turned on. As shown in FIG. 4A , when the first and second switching TFTs SW 1 and SW 2 are turned on, the first driving TFT M 1 functions as a diode. Therefore, a current I OLED applied to the second driving TFT M 2 is controlled by a data current I data of the first driving TFT M 1 . For example, if the first and second driving TFTs M 1 and M 2 are in a mirror ratio (MR) of 5:1 and if the OLED E needs a current of 1 microampere (μA) to display a white color, then a current of 1 microampere (μA) can be applied to the organic light emitting diode E through the second driving TFT M 2 when a current of 5 microamperes (μA) is sunk through the first driving TFT M 1 .

In addition, as shown in FIG. 4B , the pixel has a current sink method, such that gate voltages Vg_m 1 and Vg_m 2 of the first and second driving TFTs M 1 and M 2 have the same value irrespective of elements of the neighboring pixels. Therefore, the pixel having the structure of FIG. 2 can improve the image quality, and the charge stored in the storage capacitor C st can maintain the voltage of the voltage signal on the gates of the driving TFTs M 1 and M 2 . Additionally, although the switching TFTs SW 1 and SW 2 are turned OFF, the current level flowing to the organic light emitting diode E remains constant during one frame.

FIG. 5 illustrates parasitic capacitances in the pixel of FIG. 2 . As shown in FIG. 5 , a first parasitic capacitance C 1 is between the first switching TFT SW 1 and the gates of the first and second driving TFTs M 1 and M 2 . A second parasitic capacitance C 2 is between the second switching TFT SW 2 and the gates of the first and second driving TFTs M 1 and M 2 . As a result, after switching off the first and second switching TFTs SW 1 and SW 2 , a kick back phenomenon occurs. First and second kick back currents caused by the first and second parasitic capacitances C 1 and C 2 can be calculated by the following equations (1) and (2).

Δ ⁢ ⁢ Ip ⁢ ⁢ 1 = C ⁢ ⁢ 1 C ⁢ ⁢ 1 + C ⁢ ⁢ 2 + Cst ⁢ Δ ⁢ ⁢ I ⁢ ⁢ 1 Equation ⁢ ⁢ ( 1 ) Δ ⁢ ⁢ Ip ⁢ ⁢ 2 = C ⁢ ⁢ 2 C ⁢ ⁢ 1 + C ⁢ ⁢ 2 + Cst ⁢ Δ ⁢ ⁢ I ⁢ ⁢ 2 Equation ⁢ ⁢ ( 2 )

where C 1 is the first parasitic capacitance between the first switching TFT SW 1 and the gates of the first and second driving TFTs M 1 and M 2 , and C 2 is the second parasitic capacitance between the second switching TFT SW 2 and the gates of the first and second driving TFTs M 1 and M 2 . Furthermore, ΔI 1 and ΔI 2 represent current values applied to the first and second parasitic capacitors C 1 and C 2 .

FIG. 6 is a simulation graph illustrating kick back currents occurring in the pixel of FIG. 2 . As shown in FIG. 6 , when the second and first switching TFTs SW 2 and SW 1 (shown in FIG. 2 ) are sequentially turned off, the parasitic capacitances C 1 and C 2 induce a voltage drop producing the current drop at portions A and B. The overall kick back current ΔIp may be about 27.1% of the total current. As a result, the organic electro luminescence device displays abnormal lines during operation.

FIG. 7 is a circuit diagram of a pixel of another organic electro luminescence device according to the related art. In FIG. 7 , the pixel includes a data line D, a power line V DD , first and second driving TFTs M 1 and M 2 , a organic light emitting diode E, first and second switching TFTs SW 1 and SW 2 , first and second scan lines Sc 1 and Sc 2 , and a storage capacitor C st . The first and second driving TFTs M 1 and M 2 receive a power voltage from the power line V DD . The second driving TFT M 2 is connected to the organic light emitting diode E.

The first and second switching TFTs SW 1 and SW 2 receive scan signals from the first and second scan lines Sc 1 and Sc 2 , respectively. The first switching TFT SW 1 is connected to the data line D to receive a data signal from the data line D. The second switching TFT SW 2 is connected to the first switching and driving TFTs SW 1 and M 1 . The storage capacitor C st is located between the power line V DD and a drain of the second switching TFT SW 2 , and supplies a voltage to the gate of the second driving TFTs M 2 .

Unlike the pixel shown in FIG. 2 , the first and second switching TFTs SW 1 and SW 2 and the first and second driving TFTs M 1 and M 2 of FIG. 7 are PMOS transistors. An anode of the organic light emitting diode E is connected to the second driving TFT M 2 .

The first and second driving TFTs M 1 and M 2 has a connection of current mirror circuit where the drain current of the first driving TFT M 1 is proportional to the drain current of the second driving TFT M 2 irrespective of the load resistance value. In FIG. 7 , the anode of the organic light emitting diode E is connected to a drain of the second driving TFT M 2 , such that the current mirror circuit controls the data value applied to the organic light emitting diode E. As a result, the mirror ratio (MR) of the second driving TFT M 2 and the first driving TFT M 1 controls the current level being applied to the organic light emitting diode E.

FIG. 8 is a graph showing scan signals applied to the scan lines Sc 1 and Sc 2 of FIG. 7 , and FIGS. 9A and 9B are equivalent circuit diagrams illustrating ON and OFF states of the switching elements of FIG. 7 . As shown in FIG. 8 , a low-state scan signal is applied to both the first and second scan lines Sc 1 and Sc 2 during a pre-charging period. Then, a high-state scan signal is applied to the second scan line Sc 2 at the end of a C st charging period, before another high-state scan signal is applied to the first scan line Sc 1 .

As shown in FIG. 9A , when the low-state scan signals are applied to the first and second scan lines Sc 1 and Sc 2 , the first and second switching TFTs SW 1 and SW 2 are turned ON. Thus, the current sink is formed, gate voltages Vg_m 1 and Vg_m 2 of the first and second driving TFTs M 1 and M 2 are the same.

As shown in FIG. 9B , when the first and second switching TFTs SW 1 and SW 2 are turned OFF, the first and second driving TFTs M 1 and M 2 receive the different gate voltages. Therefore, the different stresses are imposed on the first and second driving TFTs M 1 and M 2 , and those driving TFTs M 1 and M 2 express different characteristics. For example, when the first and second switching TFTs SW 1 and SW 2 are turned OFF, the second gate voltage Vg_m 2 of the second driving TFT M 2 is the data voltage from the data line D, but the first gate voltage Vg_m 1 of the first driving TFT M 1 is a difference between a power V DD and a threshold voltage Vth-m 1 of the first driving TFT M 1 because of the continuous diode connection. Thus, the first and second gate voltages Vg_m 1 and Vg_m 2 are significantly different from each other. As a result, the organic electro luminescence device still fails to uniformly display images.

FIG. 10 illustrates a parasitic capacitance in the pixel of FIG. 7 . As shown in FIG. 10 , a parasitic capacitance C 3 is formed between the gate of the second driving TFT M 2 and a gate terminal of the second switching TFT SW 2 . As a result, after switching off the first and second switching TFTs SW 1 and SW 2 , a kick back phenomenon occurs. A kick back current caused by the parasitic capacitance C 3 can be calculated by the following equation (3).

Δ ⁢ ⁢ Ip ⁢ ⁢ 3 = C ⁢ ⁢ 3 C ⁢ ⁢ 3 + Cst ⁢ Δ ⁢ ⁢ I ⁢ ⁢ 3 Equation ⁢ ⁢ ( 3 )

where C 3 is a parasitic capacitance between the second switching TFT SW 2 and the second driving TFT M 2 , and ΔI 3 represents a current value applied to that parasitic capacitor C 3 .

FIG. 11 is a simulation graph illustrating a kick back current occurring in the pixel of FIG. 7 . As shown in FIG. 11 , when the second and first switching TFTs SW 2 and SW 1 (shown in FIG. 7 ) are sequentially turned off, the parasitic capacitance C 3 (shown in FIG. 10 ) induces a voltage drop producing the current drop at portion A. The overall kick back current ΔIp 3 may be about 6.1% of the total current. However, the organic electro luminescence device still fails to uniformly display images because the first and second driving TFTs M 1 and M 2 receives different electrical stresses as the first and second switching TFTs SW 1 and SW 2 are turned off.

Accordingly, the present invention is directed to an organic electro luminescence device that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.

An object of the present invention is to provide an organic electro luminescence device that minimizes an effect of a kick back current.

Another object of the present invention is to provide an organic electro luminescence device that prevents different stresses being imposed on driving thin film transistors, thereby obtaining higher resolution and better image quality.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described herein, the organic electro luminescence device includes first, second, and third switching elements connected in series with each other, the first switching element controlled by a first signal, and the second and third switching elements controlled by a second signal, the second signal being different from the first signal, a first driving element connected to a power source, a storage capacitor, and the first, second and third switching elements, and a second driving element connected to the power source, the storage capacitor, an organic light emitting diode, and the third switching element.

In another aspect, the organic electro luminescence device includes power and data lines, a first driving TFT connected to the power line, a second driving TFT connected to the power line, an organic light emitting diode connected to the second driving TFT, a first switching TFT connected to the data line, a second switching TFT connected to the first switching TFT and the first driving TFT, a third switching TFT connected to the second switching TFT, the first driving TFT, and the second driving TFT, a storage capacitor connected between the power line and the third switching TFT, a first scan line connected to the first switching TFT, and a second scan line connected to the second switching TFT and the third switching TFT.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention. In the drawings:

FIG. 1 is a schematic diagram of an active matrix type organic electro luminescence device according to the related art;

FIG. 2 is a circuit diagram of a pixel region of an organic electro luminescence device according to the related art;

FIG. 3 is a graph showing scan signals applied to the scan lines Sc 1 and Sc 2 of FIG. 2 ;

FIGS. 4A and 4B are equivalent circuit diagrams illustrating ON and OFF states of the switching elements of FIG. 2 ;

FIG. 5 illustrates parasitic capacitances in the pixel of FIG. 2 ;

FIG. 6 is a simulation graph illustrating kick back currents occurring in the pixel of FIG. 2 ;

FIG. 7 is a circuit diagram of a pixel of another organic electro luminescence device according to the related art;

FIG. 8 is a graph showing scan signals applied to the scan lines Sc 1 and Sc 2 of FIG. 7 ;

FIGS. 9A and 9B are equivalent circuit diagrams illustrating ON and OFF states of the switching elements of FIG. 7 ;

FIG. 10 illustrates a parasitic capacitance in the pixel of FIG. 7 ;

FIG. 11 is a simulation graph illustrating a kick back current occurring in the pixel of FIG. 7 ;

FIG. 12 is an equivalent circuit diagram illustrating one pixel of an organic electro luminescence device according to an embodiment of the present invention;

FIG. 13 is a graph showing scan signals applied to the scan lines Sc 1 and Sc 2 of FIG. 12 ;

FIGS. 14A and 14B are equivalent circuit diagrams illustrating ON and OFF states of the switching elements of FIG. 12 ;

FIG. 15 illustrates a parasitic capacitance in the pixel of FIG. 12 ; and

FIG. 16 is a simulation graph illustrating a kick back current occurring in the pixel of FIG. 12 .

Reference will now be made in detail to the preferred embodiments, examples of which are illustrated in the accompanying drawings.

FIG. 12 is an equivalent circuit diagram illustrating one pixel of an organic electro luminescence device according to an embodiment of the present invention. In FIG. 12 , an organic electro luminescence device may include a data line D and a power line V DD along a first direction spaced apart from each other, and first and second scan lines Sc 1 and Sc 2 along a second direction intersecting the data line D and the power line V DD , thereby defining a pixel region. Although only one data line D, one power line V DD , one first scan line Sc 1 , and one second scan line Sc 2 are shown, the organic electro luminescence device may include a plurality of the data lines D, power lines V DD , the first scan lines Sc 1 , and the second scan lines Sc 2 , thereby having a plurality of pixel regions.

In addition, first and second driving thin film transistors MT 1 and MT 2 , an organic light emitting diode E, first to third switching thin film transistors SWT 1 , SWT 1 and SWT 3 , and a storage capacitor C st may be formed in the pixel region. The first and second driving thin film transistors MT 1 and MT 2 may form a current mirror circuit and may receive a power voltage from the power line V DD . The organic light emitting diode E may connect to a drain of the second driving TFT MT 2 and to a ground source GND.

Further, the data line D may be connected to the first switching TFT SWT 1 and may apply a data signal to the first switching TFT SWT 1 . The second switching TFT SWT 2 may be connected to both of the first switching and driving TFTs SWT 1 and MT 1 , and the third switching TFT SWT 3 may be connected to the second switching TFT SW 2 and the first and second driving TFTs MT 1 and MT 2 . The storage capacitor C st may be connected to the power line V DD and to the third switching TFT SWT 3 . The first scan line Sc 1 may be connected to the first switching TFT SWT 1 for applying a first scan signal thereto, and the second scan line Sc 2 may be connected to the second and third switching TFTs SWT 2 and SWT 3 for applying a second scan signal thereto. As a result, the second switching TFT SWT 2 and the third switching TFT SWT 3 may be operated simultaneously.

FIG. 13 is a graph showing scan signals applied to the scan lines Sc 1 and Sc 2 of FIG. 12 , and FIGS. 14A and 14B are equivalent circuit diagrams illustrating ON and OFF states of the switching elements of FIG. 12 . As shown in FIG. 13 , a low-state scan signal may be applied to both the first and second scan lines Sc 1 and Sc 2 during a pre-charging period. However, a high-state scan signal may be applied to the second scan line Sc 2 at the end of a C st charging period, before another high-state scan signal is applied to the first scan line Sc 1 .

When the low-state scan signals are applied to the first and second scan lines Sc 1 and Sc 2 during the pre-charging period and during the C st charging period, the first to third switching TFTs SWT 1 , SWT 2 and SWT 3 may be turned on. As shown in FIG. 14A , when the first to third switching TFTs SWT 1 , SWT 2 and SWT 3 are turned on, the first driving TFT MT 1 may function as a diode, and the first and second driving TFTs MT 1 and MT 2 may form a current mirror.

When the high-state scan signals are applied to the first and second scan lines Sc 1 and Sc 2 , the first to third switching TFTs SWT 1 , SWT 2 and SWT 3 may be turned off. As shown in FIG. 14B , although the first, second and third switching TFTs SWT 1 , SWT 2 and SWT 3 are switched off, the gate of the first driving TFT MT 1 may be floated because the second and third switching TFTs SWT 2 and SWT 3 are turned off simultaneously. As a result, the first driving transistor MT 1 does not form the diode connection and gate voltages Vg_m 1 and Vg_m 2 of the first and second driving TFTs MT 1 and MT 2 are about the same. Accordingly, the same stress level is imposed on the first and second driving TFTs MT 1 and MT 2 , thereby avoiding non-uniformity in image quality.

FIG. 15 illustrates a parasitic capacitance in the pixel of FIG. 12 . As shown in FIG. 15 , a parasitic capacitance C 4 may be considered to be between a gate terminal of the second driving TFT MT 2 and a gate terminal of the third switching TFT SWT 3 , when the third switching TFT SWT 3 is turned off. As a result, a kick back current ΔIp may occur, and the kick back current ΔIp may be calculated by the following equation (4).

Δ ⁢ ⁢ Ip = C ⁢ ⁢ 4 C ⁢ ⁢ 4 + Cst ⁢ Δ ⁢ ⁢ I ⁢ ⁢ 4 Equation ⁢ ⁢ ( 4 )

where C 4 is a parasitic capacitance between the third switching TFT SWT 3 and the second driving TFT MT 2 , and ΔI 4 represents a current value applied to the parasitic capacitor C 4 . That is, ΔI 4 is the electric current applied between the third switching TFT SWT 3 and the gate of the second driving TFT MT 2 .

FIG. 16 is a simulation graph illustrating a kick back current occurring in the pixel of FIG. 12 . As shown in FIG. 16 , when the high-state scan signal is applied to the second scan line Sc 2 resulting the second and third switching TFTs SWT 2 and SWT 3 (shown in FIG. 12 ) being turned off, a kick back current ΔIp may occur at circle A. The kick back current ΔIp may be about 8.3% of the total current, which is close to that described with reference to FIG. 11 . In particular, the difference between the kick back current ΔIp of 8.3% shown in FIG. 16 and the kick back current ΔIp 3 of 6.1% shown in FIG. 11 is about 2% and is relatively immaterial, especially in light of the similar stress levels being experienced at the gates of the first and second driving TFT MT 1 and MT 2 . As a result, the combination of the first to third switching TFTs SWT 1 , SWT 2 and SWT 3 may protect the first and second driving TFTs MT 1 and MT 2 from experiencing different stress levels and may minimize an effect of a kick back current.

Thus, the organic electro luminescence device according to an embodiment of the present invention avoid different stress level being imposed on the driving TFTs, thereby uniformly displaying images. Moreover, the organic electro luminescence device according to an embodiment of the present invention may minimize an effect of a kick back current due to a parasitic capacitance between the driving TFT and the switching TFT. Therefore, the organic electro luminescence device according to an embodiment of the present invention provides higher resolution and better image quality.

It will be apparent to those skilled in the art that various modifications and variations can be made in the organic electro luminescence device of the present invention without departing from the sprit or scope of the invention. Thus, it is intended that the present invention covers the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.