Memory regulator system with test mode

The present invention is directed to a memory regulator system and, more particularly, to a memory regulator system having a test mode.

Modern print heads often include a memory device (i.e., a memory array) located directly on the print head. Such print head memory arrays are designed to store various bits of information that assist in providing an efficient and user-friendly printer operation. For example, the print head memory array may store information such as the type of ink/toner cartridge, type of printer, amount of ink/toner used, diagnostic data and the like.

One such print head memory array is a floating gate memory array utilizing CMOS EPROM technology. The floating gate memory array may include a two-dimensional array of memory elements or cells, wherein each cell may be programmed to store data.

The memory array may operate as follows. Initially, each cell is in its native (i.e., unprogrammed) state and therefore corresponds to a digital “0.” The cell is programmed by converting the digital “0” into a digital “1” when a sufficient voltage (e.g., 10 volts) is applied to the cell. Thus, data may be stored to the memory array by selectively programming cells in the array (i.e., the “write” mode). During a “read” mode, data may be retrieved from the memory array by applying a second voltage to the cell (e.g., 2.5 volts). The second voltage is not sufficient to write (or program the cell), but is sufficient to generate a current within the cell. The amount of current generated is measured and indicates whether or not the cell has been programmed (i.e., whether the cell is a “1” or a “0”). A small current (e.g., 5 milliamps) may correspond to the cell not being programmed and a large current (e.g., 100 milliamps) may correspond to the cell being programmed.

The printer may toggle between the write mode and the read mode by applying various voltages (e.g., 2.5 volts versus 10 volts) to the cells in the array. Accordingly, there is a need for a memory regulator system capable of supplying at least one voltage that corresponds to a read mode and a second voltage that corresponds to a write mode. Furthermore, there is a need for a memory regulator system having a test mode.

A first embodiment of the present invention is a memory regulator system for switching between a read mode and a write mode. The system includes a voltage regulating circuit and a memory array. The voltage regulating circuit includes a voltage input and a control input, wherein the control input regulates the voltage input between at least a first voltage output and a second voltage output. The voltage regulating circuit is in electrical communication with the memory array and supplies the memory array with the first voltage output to correspond to the read mode and the second voltage output to correspond to the write mode.

In an alternative embodiment, the present invention is an electric circuit having a voltage regulating mode and a test mode, wherein the electric circuit is connected to a load circuit. The electric circuit includes a voltage input, a ground, a control input that regulates the voltage input between at least a first voltage output and a second voltage output when the electric circuit is in the voltage regulating mode, and at least one test input in electrical communication with at least one transistor, wherein the at least one test input supplies a first transistor voltage to the transistor when the electric circuit is in the voltage regulating mode and a second transistor voltage to the transistor when the electric circuit is in the test mode such that the transistor substantially prevents a current flow from the load circuit to the ground when the electric circuit is in the test mode.

The invention can be understood with reference to the following drawings, in which like reference numerals designate corresponding parts throughout the several views.

FIG. 1 is a block diagram of one embodiment of a memory regulator system according to one embodiment of the present invention;

FIG. 2 is a schematic diagram of a voltage regulating circuit of the system of FIG. 1 ; and

FIG. 3 is a schematic diagram of the voltage regulating circuit of FIG. 1 having a test mode.

As shown in FIG. 1 , the memory regulator system 6 includes a memory array 8 , a voltage power rail 9 and a voltage regulating circuit 10 . The memory array 8 may be a floating gate memory array having a two-dimensional array of memory elements or cells 11 . Various other memory arrays may be used, such as fuse memories and the like. The voltage regulator circuit 10 (discussed in greater detail below) includes a voltage source or input 12 , a control input 14 , a ground 16 and a voltage output 18 . The voltage output 18 is in electrical communication with the voltage power rail 9 such that the voltage power rail 9 can distribute the output voltage from the voltage regulator circuit 10 throughout the memory array 8 .

The voltage regulator circuit 10 includes transistors 20 , 22 , 24 , an operational amplifier 26 , capacitors 28 , 30 , 32 , resistors 34 , 36 , 38 , 40 , 42 , 44 , 46 and a power source 48 . The operational amplifier 26 includes inputs V in+ and V in− and output V out .

Voltage input 12 supplies a voltage from the printer (not shown) to the circuit 10 . For example, the voltage input 12 may be 11 volts. The circuit 10 regulates the voltage input 12 according to the control input 14 such that the voltage output 18 corresponds to either the read mode voltage (e.g., 2.5 volts) or the write mode voltage (e.g., 10 volts).

The control input 14 may be high (e.g., 3.3 volts) or low (0 volts). The control input 14 is based on signals received from the printer such as logic decoded serial data. When the control input 14 is high, the transistor 20 is active (i.e., turned on) such that current may flow through the transistor 20 . Thus, resistor 34 is active when the control input 14 is high. When the control input 14 is low, the transistor 20 is inactive (i.e., turned off) such that no current may flow through transistor 20 . Thus, resistor 34 is inactive when the control input 14 is low.

Resistors 34 , 36 , 38 form a resistance divider network 50 that regulates the voltage applied to the V in− input of operational amplifier 26 . Accordingly, the voltage applied to the V in− input depends on whether resistor 34 is active (i.e., whether control input 14 is activating or deactivating transistor 20 ).

When transistor 20 is active, the voltage applied to the V in− input is as follows:

V in - = V 12 ⁢ ( R 34 ⁢ R 38 R 34 + R 38 ) R 36 + ( R 34 ⁢ R 38 R 34 + R 38 )

where V 12 is the voltage input 12 , R 34 is the resistance of resistor 34 , R 36 is the resistance of resistor 36 and R 38 is the resistance of resistor 38 .

When transistor 20 is inactive, the voltage applied to the V in− input is as follows:

V in - = V 12 ⁡ ( R 38 R 36 + R 38 )

where V 12 is the voltage input 12 , R 36 is the resistance of resistor 36 and R 38 is the resistance of resistor 38 .

Accordingly, the resistances of resistors 34 , 36 , 38 can be selected to obtain a first desired voltage at the V in− input when resistor 34 is active (i.e., transistor 20 is active) and a second desired voltage at the V in− input when resistor 34 is inactive (i.e., transistor 20 is inactive). For example, when the input voltage 18 is 11 volts, resistors 34 , 36 , 38 can be selected such that a voltage of 5 volts is applied at the V in− input when resistor 34 is active and a voltage of 1.25 volts is applied at the V in− input when resistor 34 is inactive. It should be apparent to one skilled in the art that various voltage inputs and resistors may be used in combination with transistor 34 to switch between two different output voltages.

The operational amplifier 26 and resistors 40 , 42 (collectively known as a non-inverting amplifier) amplify the voltage applied to the V in− input to provide the final voltage output 18 . Assuming the resistance of resistor 44 is zero, the voltage output 18 may be calculated as follows:

V 18 = V in - ⁡ ( 1 + R 42 R 40 )

where V 18 is the voltage output 18 , R 40 is the resistance of resistor 40 and R 42 is the resistance of resistor 42 . For example, when the resistance of resistors 40 and 42 is equal (i.e., R 40 =R 42 ), the operational amplifier 26 would have a gain of two.

Accordingly, expanding on the example above, when a voltage of 1.25 volts is applied to the V in− input and R 40 =R 42 , the voltage output 18 would be 2.5 volts (corresponding to the read mode) and when a voltage of 5 volts is applied to the V in− input and R 40 =R 42 , the voltage output 18 would be 10 volts (corresponding to the write mode).

Capacitor, resistors 44 , 46 and transistor 22 may be provided on the circuit 10 to enhance the stability of the circuit 10 .

As shown in FIG. 3 , an alternative embodiment of the voltage regulating circuit, generally designated 60 , additionally includes test inputs 62 , 66 , a transistor 64 , capacitor 32 and a resistor 68 . Transistor 64 is provided between resistor 40 and the ground 16 and is controlled by test input 62 . Test input 66 is connected to transistor 22 (with resistor 68 positioned therebetween) for controlling transistor 22 .

Test inputs 62 , 66 ordinarily (i.e., during the voltage regulating mode, discussed above) supply a high voltage (e.g., 3.3 volts) to the corresponding transistors 64 , 22 such that the transistors 64 , 22 are ordinarily open and active (i.e., allow current and voltage to flow). However, when the test mode is initiated and a signal is sent to the test inputs 62 , 66 , the test inputs 62 , 66 decrease the voltage supplied to the transistors 64 , 22 (e.g., zero volts are supplied) such that the transistors 64 , 22 deactivate and electrically isolate the output 18 from the ground 16 . Capacitor 30 also isolates the output 18 from the ground 16 once the capacitor 30 is fully charged.

During the test mode, a voltage may be applied to output 18 for testing a load circuit (e.g., the memory array 8 ) connected to the voltage output 18 . The testing of the load circuit cannot be conducted accurately if current is permitted to leak from the load circuit, through the voltage regulating circuit 10 and to the ground 16 . Thus, the test mode electrically isolates the load circuit from the ground 16 .

Although the invention is shown and described with respect to certain embodiments, it is obvious that equivalents and modifications will occur to those skilled in the art upon reading and understanding the specification. The present invention includes all such equivalents and modifications and is limited only by the scope of the claims.