Robust monolithic automatic bias circuit with current setting apparatus

The present invention relates to automatic bias control, temperature compensation, process variation compensation and reference tracking circuit design.

Field effect transistors (FET) gate threshold voltage varies significantly from wafer to wafer. In addition, bipolar junction transistors (BJT) exhibit collector current temperature dependence. Consequently, the bias point will change with temperature and from transistor to transistor. Solutions already exist to counter these phenomena. The degree of success varies with approach complexity. For example, a simple feedback current source can provide ±20% variation around a targeted quiescent bias current. A regulated solution typically provides a ±5% deviation around a desired quiescent bias current. Both of these approaches attempt to maintain a constant quiescent bias current over temperature and process variations.

FIG. 1 is a circuit diagram 100 of a conventional regulator circuit 101 and a circuit to be biased 102 . Regulator circuit 101 includes voltage source 110 , resistors 120 – 123 , capacitor 130 , and operational amplifier 150 . Voltage source 110 provides a regulated DC voltage V REG to node N 0 . Resistors 120 and 121 are coupled between node N 0 and ground, thereby forming a voltage divider circuit, which provides a reference voltage V REF on node N 1 . Resistors 120 and 121 have resistances of R 0 and R 1 , respectively, such that the reference voltage V REF is equal to V REG ×R 1 /(R 0 +R 1 ) The reference voltage V REF is applied to an input terminal of operational amplifier 150 . A load resistor 123 , having a resistance R L , is coupled between nodes N 0 and N 2 , such that a voltage V OUT is applied to node N 2 . This voltage V OUT is applied to the other input terminal of operational amplifier 150 .

Operational amplifier 150 is designed to operate without saturation. The output terminal of operational amplifier 150 is coupled to node N 3 through resistor 122 . Capacitor 130 is coupled between node N 3 and ground. Resistor 122 and capacitor 130 provide isolation and filtering at the output of operational amplifier 150 . Operational amplifier 150 provides a control voltage V GS to the gate (base) of transistor Q 1 (on node N 3 ). In response, a control current I Q1 flows through transistor Q 1 and load resistor 123 . Operational amplifier 150 adjusts the control voltage V GS such that the voltage V OUT on node N 2 is equal to the reference voltage V REF on node N 1 . Thus, operational amplifier 150 effectively mirrors the reference voltage V REF to the drain (collector) of transistor Q 1 . Under these conditions, the current I Q1 is equal to (V REG −V REF )/R L , wherein V REF is equal to V REG ×R 1 /(R 0 +R 1 ). Stated another way, the current I Q1 is equal to (V REG ×R 0 /(R 0 +R 1 ))/R L . Thus, by selecting the regulated voltage V REG and the resistances R 0 , R 1 and R L , the quiescent current I Q1 through transistor Q 1 is fixed, such that this current is largely independent of process and temperature variations.

The gate (base) of transistor Q 1 is tapped at node N 3 , such that the gate (base) voltage V GS of transistor Q 1 can be used to bias other devices. Although circuit 100 provides a robust current tracking method, the quiescent current I Q1 is undesirably set at the fixed level determined by the regulated voltage V REG and the resistances R 0 , R 1 and R L .

Other regulated self-biased amplifiers are described in more detail in the following references:

[1] K. W. Kobayashi et al., “Monolithic HEMT Regulated Self-biased LNA”, IEEE MMMWC-S Dig., San-Diego, Calif., 1994.

[2] K. W. Kobayashi et al., “A Novel Compact Monolithic Active Regulated Self-biased InP HEMT Amplifier”, IEEE Microwave & Guided Wave Letters, Vol. 4, No 7, July 1994.

[3] U.S. Pat. No. 5,387,880, “Compact Monolithic Wideband HEMT Low Noise Amplifiers with Regulated Self-bias” by K. W. Kobayashi.

It would therefore be desirable to provide an apparatus that offers similar performance to the regulated solution with the added benefit of selectable steady state quiescent current value.

FIG. 1 is a circuit diagram of a conventional regulator circuit and a circuit that is biased by the conventional regulator circuit.

FIG. 2 is a block diagram of a current diverting circuit, which is coupled to the regulator circuit and the biased circuit of FIG. 1 , in accordance with one embodiment of the present invention.

FIG. 3 is a block diagram of the current diverting circuit of FIG. 2 , in accordance with one embodiment of the present invention.

FIG. 4 is a circuit diagram illustrating a current diverting circuit having a switch control circuit, a switch and a current select circuit, in accordance with a particular embodiment of the present invention.

FIG. 5 is a circuit diagram illustrating a current diverting circuit in accordance with another embodiment of the present invention.

FIG. 6 is a circuit diagram illustrating a bias control circuit having a switch control circuit, a switch circuit and a resistance select circuit in accordance with another embodiment of the present invention.

FIG. 2 is a block diagram 200 of a current diverting circuit 201 , which is coupled to regulator circuit 101 and biased circuit 102 , in accordance with one embodiment of the present invention. Regulator circuit 101 and biased circuit 102 have been described above in connection with FIG. 1 .

Current diverting circuit 201 is coupled to terminal N 2 , such that a diverted current I D flows into current diverting circuit 201 . The quiescent bias current I Q1 is equal to the current I N through load resistor 123 minus the diverted current I D . As described in more detail below, the diverted current I D is an adjustable current, such that the quiescent bias current I Q1 can have different values.

Current diverting circuit 201 is also coupled to receive the control voltage V GS from node N 3 . Note that this control voltage would be a base-emitter voltage (V BE ) if current diverting circuit 201 implements a bipolar transistor. As described in more detail below, when current diverting circuit 201 is enabled, the control voltage V GS (or V BE ) is used to control the magnitude of the diverted current I D .

In general, when current diverting circuit 201 is disabled, this circuit 201 does not draw any current, such that the diverted current I D is equal to zero. Under these conditions, the quiescent bias current I Q1 is equal to the current I N flowing through load resistor 123 . That is, regulator circuit 101 and biased circuit 102 operate in the manner described above in connection with FIG. 1 .

However, when current diverting circuit 201 is enabled, the diverted current I D is controlled to have a positive value in response to the control voltage V GS (or V BE ). Under these conditions, the quiescent current I Q1 is reduced to a value equal to I N minus the diverted current I D . Note that the current I N remains the same whether current diverting circuit 201 is enabled or disabled. In the foregoing manner, the quiescent current I Q1 can have at least two selectable values. As described in more detail below, the diverted current I D can be selected to have one or more predetermined values between I N and zero.

Note that current diverting circuit 201 sets the steady state value of the quiescent current I Q1 , while regulating circuit 101 controls the dynamic (transitory) value of the quiescent current I Q1 by canceling temperature and process variations. During steady state conditions, operational amplifier 150 maintains the reference voltage V REF equal to (V REG −R L ×I N ).

FIG. 3 is a block diagram 300 of a current diverting circuit 301 , which is coupled to regulator circuit 101 and biased circuit 102 , in accordance with one embodiment of the present invention. Regulator circuit 101 and biased circuit 102 have been described above in connection with FIG. 1 . Current diverting circuit 301 includes switch control circuit 310 , switch 320 and current select circuit 330 .

Switch control circuit 310 controls switch 320 , such that this switch 320 is either enabled (closed) or disabled (open). When switch 320 is disabled, node N 2 is effectively de-coupled from current select circuit 330 . Under these conditions, the diverted current I D is equal to zero, and the quiescent current I Q1 is equal to I N .

Conversely, when switch 320 is enabled, node N 2 is coupled to current select circuit 330 . Under these conditions, current select circuit 330 draws a current (I D ) in response to the control voltage V GS (or V BE ) on node N 3 . As a result, the quiescent current I Q1 is reduced to a value equal to I N minus the diverted current I D .

FIG. 4 is a circuit diagram 400 illustrating a current diverting circuit 401 having a switch control circuit 410 , a switch 420 and a current select circuit 430 in accordance with a particular embodiment of the present invention. Switch control circuit 410 includes resistors 411 – 412 and adjustable voltage supply 413 . Resistors 411 and 412 exhibit resistances R 11 and R 12 , respectively. Adjustable voltage supply 413 provides an adjustable output voltage V MODE . Resistor 411 is connected between adjustable voltage supply 413 and node N 4 ; and resistor 412 is connected between node N 4 and ground. Thus, a voltage divider circuit is formed, wherein the voltage on node N 4 is equal to V MODE ×R 12 /(R 11 +R 12 ).

Switch 420 includes a transistor 421 , which has a drain (collector) coupled to node N 2 and a gate (base) coupled to node N 4 . Current select circuit 430 includes transistor Q X . The source (emitter) of transistor 421 is coupled to the drain (collector) of transistor Q X in current select circuit 430 . The source (emitter) of transistor Q X is coupled to ground; and the gate (base) of transistor Q X is coupled to receive the control voltage V GS (or V BE ) from node N 3 .

In the described embodiment, transistor 421 turns on when the voltage between node N 4 and the source (emitter) of transistor 421 exceeds the threshold voltage V T . Thus, transistor 421 turns on when the voltage V MODE is large enough to impose the required voltage V ON on node N 4 . When the voltage on node N 4 is less than V ON , transistor 421 is disabled, such that the diverted current I D is approximately equal to zero.

When transistor 421 is turned on, the diverted current I D is controlled by the voltage V GS (or V BE ) on node N 3 . Thus, transistors Q 1 and Q X are biased in the same manner. That is, the gates (bases) of transistors Q 1 and Q X are both biased by V GS (or V BE ), the sources (emitters) of transistors Q 1 and Q X are both coupled to ground, and the drains (collectors) of transistors Q 1 and Q X are both biased by the voltage V OUT on node N 2 . The currents I Q1 and I D are therefore determined by the relative sizes (widths) of transistors Q 1 and Q X . For example, if transistors Q 1 and Q X are identical, then the currents I Q1 and I D are almost equal. Thus, the bias current I Q1 has a value of I N when current diverting circuit 401 is disabled, and a value of I N /2 when current diverting circuit 401 is enabled. In general, if transistor Q X size is M times the size of transistor Q 1 , then the bias current I Q1 has a value of I N /(M+1) when current diverting circuit 401 is enabled.

The bias current I Q1 is mirrored to the biased circuit 102 as the current I Q2 . Advantageously, the quiescent value of the bias current I Q1 (and therefore I Q2 ), is selected to have one of two values in response to current diverting circuit 401 .

FIG. 5 is a circuit diagram 500 illustrating a current diverting circuit 501 having a switch control circuit 510 , a switch 520 and a current select circuit 530 in accordance with another embodiment of the present invention. Switch control circuit 510 includes diodes 511 – 516 and adjustable voltage supply 517 , which provides an adjustable output voltage V MODE . Switch 520 includes transistors 521 1 – 521 N . Current select circuit 530 includes transistors Q X1 –Q XN .

The gate (base) of each transistor 521 X is coupled to receive the output voltage V MODE through X−1 level shifters (in present example, diodes are used, however in other embodiments, source/emitter follower can be used), wherein X is an integer between 1 and N. Thus, the gate (base) of transistor 521 1 is directly coupled to receive the output voltage V MODE ; the gate (base) of transistor 521 2 is coupled to receive the output voltage V MODE through one forward-biased diode 511 ; the gate (base) of transistor 521 2 is coupled to receive the output voltage V MODE through two forward biased diodes 512 – 513 ; and the gate (base) of transistor 521 N is coupled to receive the output voltage V MODE through N−1 forward biased diodes 514 – 516 . The drains (collectors) of transistors 521 1 – 521 N are commonly coupled to node N 2 .

The sources (emitters) of transistors 521 1 – 521 N are coupled to drains of transistors Q X1 –Q XN . The sources (emitters) of transistors Q X1 –Q XN are coupled to ground. The gates (bases) of transistors Q X1 –Q XN are commonly coupled to receive the control voltage V GS (or V BE ) from node N 3 .

The voltage V MODE at which transistor 521 X turns on can be defined as V ON +(X−1)×V D , where X is an integer between 1 and N, V ON is the necessary voltage to turn on the transistor 521 X , and V D is a diode forward bias threshold voltage. Thus, transistor 521 turns on when the voltage V MODE exceeds V ON , and transistor 521 3 turns on when the voltage V MODE exceeds V ON +2V D .

When the voltage V MODE is less than V ON , all of transistors 521 1 – 521 N are disabled, such that the diverted current I D is approximately equal to zero. Transistors Q 1 , Q X1 , Q X2 , Q X3 , . . . Q XN have gate widths W 1 , W X1 , W X2 , W X3 , . . . W XN , respectively. The diverted current I D increases, and the steady state quiescent current I Q1 decreases, as the adjustable voltage V MODE increases. Table 1 below defines values of the diverted current I D for various values of the V MODE voltage. Table 2 below defines values of the steady state quiescent current I Q1 for various values of the V MODE voltage.

Thus, as the adjustable voltage V MODE increases, more of transistors Q X1 –Q XN are turned on, thereby increasing the diverted current I D . When transistors Q X1 –Q XN are turned on, these transistors are connected in parallel with transistor Q 1 , such that these transistors Q X1 –Q XN and Q 1 are biased in the same manner. That is, the gates (bases) of transistors Q X1 –Q XN and Q 1 are all biased by the control voltage V GS (or V BE ). As a result, the magnitude of the diverted current I D through transistors Q X1 –Q XN and the magnitude of the bias current I Q1 through transistor Q 1 are determined by the relative sizes of transistors Q X1 –Q XN and Q 1 . See, e.g., Tables 1 and 2.

The bias current I Q1 is mirrored to the biased circuit 102 as the current I 2 . Advantageously, the quiescent value of the bias current I Q1 (and therefore I Q2 ), is selected to have one of (N+1) values in response to current diverting circuit 501 .

FIG. 6 is a circuit diagram 600 illustrating a bias control circuit 601 having a switch control circuit 610 , a switch circuit 620 and a resistance select circuit 630 in accordance with another embodiment of the present invention. Switch control circuit 610 includes level shifters (diodes or a source/emitter follower) 611 – 616 and adjustable voltage supply 617 , which provides an adjustable output voltage V MODE . Switch circuit 620 includes transistors S 1 –S N . Resistance select circuit 630 includes resistors 631 1 – 631 N , which have resistances R A1 –R AN , respectively. The on-resistances of transistors S 1 –S N are negligible when compared with the resistances R A1 –R AN .

The gate (base) of each transistor S X is coupled to receive the output voltage V MODE through X−1 diodes, wherein X is an integer between 1 and N. Thus, the gate of transistor S 1 is directly coupled to receive the output voltage V MODE ; the gate of transistor S 2 is coupled to receive the output voltage V MODE through one forward-biased diode 611 ; the gate of transistor S 2 is coupled to receive the output voltage V MODE through two forward biased diodes 612 – 613 ; and the gate of transistor S N is coupled to receive the output voltage V MODE through N−1 forward biased diodes 614 – 616 . The sources (emitters) of transistors S 1 –S N are coupled to resistors 631 1 – 631 N respectively, and the drains (collectors) of transistors S 1 –S N are commonly coupled to node N 1 . Resistors 631 1 – 631 N are further commonly coupled to ground.

The voltage V MODE at which transistor S X turns on can be defined as V ON +(X−1)×V D , where X is an integer between 1 and N, V ON is the necessary voltage to turn on the transistor S X , and V D is a diode forward bias threshold voltage. Thus, transistor S 1 turns on when the voltage V MODE exceeds V ON , and transistor S 3 turns on when the voltage V MODE exceeds V ON +2V D .

When the voltage V MODE is less than V ON , all of transistors S 1 –S N are disabled, such that the reference voltage V REF applied to node N 1 is unaffected by bias control circuit 601 . That is, the reference voltage V REF is equal to V REG ×R 1 /(R 0 +R 1 ). When the voltage V MODE is greater than V ON , one or more of the transistors S 1 –S N is enabled, the effective resistance between node N 1 and ground is reduced, such that the reference voltage V REF on node N 1 is reduced. Because the reduced reference voltage V REF is mirrored to node N 2 as the output voltage V OUT , the resulting current I N (which is equal to (V REG −V OUT )/R L ) is increased. As the current I N increases, the steady state quiescent current I Q1 increases. Table 3 below defines values of the steady state quiescent current I N for various values of the V MODE voltage.

Thus, as the adjustable voltage V MODE increases, more of transistors S 1 –S N are turned on, thereby reducing the resistance between node N 1 and ground. This reduced resistance increases the voltage drop across the load resistance R L , thereby increasing the current I N (and the associated steady state quiescent current I Q1 ). In the foregoing manner, bias control circuit 601 can be used to adjust the steady state quiescent current I Q1 . Note that bias control circuit 601 can be used independent of the above-described current diverting circuits or in combination with these above-described current diverting circuits.

The present invention combines two major advantages, namely: (1) the steady state quiescent current I Q1 can be set independent of the control loop present in regulator circuit 101 , and (2) closed loop regulation is used, thereby providing optimal immunity to process and temperature variations.

The present invention can be used virtually in any design that requires quiescent point immunity to temperature and process variation, and at the same time allows the possibility to set the quiescent point. The present invention is particularly useful to provide a versatile bias scheme for multi-mode power amplifiers.

Although the invention has been described in connection with several embodiments, it is understood that this invention is not limited to the embodiments disclosed, but is capable of various modifications, which would be apparent to one of ordinary skill in the art. For example, although the above-described examples use field effect transistors, it is understood that field effect transistors can be replaced with bipolar junction transistors (BJTs) in other embodiments. Moreover, although the present invention is described as implementing enhancement-type transistors, it is understood that the present invention can also be implemented using depletion-type transistors. Note that operational amplifier 150 can be configured to provide a positive or negative output voltage V GS , thereby allowing the invention to be used with depletion mode or enhancement mode transistors (including bipolar RF transistors). Accordingly, the present invention is limited only by the following claims.