Process tracking limiter for VCO control voltages

The present invention relates to electronic circuitry and, in particular, to a process tracking limiter for VCO control voltages.

In self-biased Phase-Locked Loops (PLLs) the Voltage Controlled Oscillator (VCO) will typically have very high gain, on the order of a few GHz per volt. With wide variations in operating conditions and silicon processing, the control voltage for the VCO can go through a wide range while trying to achieve lock. If the control voltage is left unlimited, the very high VCO gain can cause the VCO output frequency to go too high, to a region where the VCO itself does not have the sufficient open-loop gain to sustain oscillations. The control loop of the PLL then forces the control voltage to make the VCO run even faster, thus causing it to stay out of lock and not recover.

Prior art solutions employ either fixed limits for the VCO control voltage or ones that only track power supply changes. These solutions must keep the VCO control voltage window much wider to account for process variations. This can force the VCO into a region where it will not oscillate.

The top portion of FIG. 1 shows a typical self-biased PLL based on “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques”, J. G. Maneatis, Journal of Solid State Circuits, November 1996. The top portion of FIG. 1 includes input Fin; phase frequency detector (PFD) 20 ; dual charge pumps 22 ; bias generator 24 ; VCO 26 ; current mode logic (CML) dividers 28 ; CML to CMOS converter 30 ; output Fout; and source voltage VDD. To keep the VCO control voltage V CTRL from entering regions where the VCO may not oscillate, the circuitry in the lower portion of FIG. 1 has been added. The lower portion of FIG. 1 includes control voltage V CTRL comparators 32 and 34 ; switches 36 and 38 ; variable V CTRL window generator 40 ; and safe V CTRL generator 42 for Pull-in. If the control voltage V CTRL is outside the lower and upper control voltage limits Vcmpl and Vcmph, respectively, one of the two switches 36 and 38 is closed. This will pull voltage V CTRL into the operating window towards a target voltage. Region 44 of FIG. 1 provides limits for the control voltage.

Previous designs typically use a resistor divider from the power supply to generate control limits Vcmpl and Vcmph. This will somewhat track power supply changes, but does not follow process variations. This is not adequate for extreme operating conditions, such as automotive applications where the junction temperature can be −40 to 150° C.

A control voltage window generator that tracks process, voltage supply, and temperature variations for a voltage controlled oscillator includes: a first transistor of a first conductivity type coupled between a supply voltage node and an upper control voltage node; and a second transistor of a second conductivity type coupled to the upper control voltage node to compensate for process variations in devices of the first conductivity type. Additionally, a target pull-in voltage generator includes circuitry for providing a pull-in control voltage that will always be inside the control voltage window, and also tracks process, voltage supply, and temperature variations.

In the drawings:

FIG. 1 is a block diagram of a self-biased PLL with a control voltage window generator;

FIG. 2 is a circuit diagram of a first embodiment self-biased window generator according to the present invention;

FIG. 3 . is a circuit diagram of a second embodiment self-biased window generator according to the present invention;

FIG. 4 . is a circuit diagram of a first embodiment device for generating a target pull-in voltage that will always be inside the control voltage window according to the present invention;

FIG. 5 . is a circuit diagram of a reference-biased window generator according to the present invention;

FIG. 6 . is a circuit diagram of a second embodiment device for generating a target pull-in voltage, when reference biases are available, that will always be inside the control voltage window according to the present invention.

The solution according to the present invention uses dynamically changing thresholds for the VCO control voltage window that tracks process variations, as well as power supply and temperature variations.

This solution makes use of the strong dependency of the self-biased PLL on process variations and moves the limits for the VCO control voltage with a similar dependency.

Therefore, it is necessary to have control limits Vcmpl and Vcmph track process variations. In self-biased PLLs, much of the process dependence is on the strength of the p-channel processing. P-channel devices are used as the resistive element in the loop filter and are the major contributor to the delay in the ring oscillator VCO. If the p-channel processing is ‘weaker’, voltages V CTRL and Vcp will be lower and voltage Vcn will be higher. Voltage Vcn sets the tail currents in the VCO and charge pumps.

FIG. 2 shows a V CTRL window generator that will track process variations in a self-biased PLL. Transistors MPO, MP 1 , and MP 2 form a resistive divider from the power supply VDD. However, the current from transistor MN 1 will move the upper limit for control voltage V CTRL appropriately for p-channel process variations. Control limit Vcmpl will follow a gate-to-source voltage (V GS ) drop below control limit Vcmph. Additionally, a second n-channel device with its gate tied to voltage Vcn, its source to ground, and its drain to control limit Vcmpl, can be added for more process variation tracking. Voltage Vcn is a tail current bias in the voltage controlled oscillator. Voltage Vcn moves opposite to voltages Vctrl and Vcp and is an inverse function of the p-channel drive strength.

To control the difference between control limits Vcmpl and Vcmph as a portion of the difference between source voltage VDD and control limit Vcmph, the circuit of FIG. 3 can be employed. The circuit of FIG. 3 includes transistors MN 1 and MP 0 ; resistors R 1 and R 3 ; and amplifier 50 . The process variation tracking is similar to that in FIG. 2 since it also uses transistor MN 1 connected to voltage Vcn. This has the capability of making the difference between control limits Vcmph and Vcmpl be less than a V GS voltage drop. It is important to make the V CTRL window as small as reasonably possible so that the VCO cannot get into a region where it cannot sustain oscillations and so that the PLL can achieve initial lock quicker—the pull-in time from outside the window is faster than the lock time while inside the window. An additional reason for a smaller control voltage window is that in some very high frequency PLLs, the circuitry after the VCO could have some ac-coupled circuits that have a high-pass pole in them. If the VCO frequency is allowed to go too low, there may not be enough signal swing through the ac-coupled circuit.

It is imperative that when the VCO control voltage is outside the window that it gets pulled-in to the window so that the PLL can then lock. This means that the target voltage that control voltage V CTRL is pulled to must also track process variations. FIG. 4 shows a circuit for generating a target pull-in voltage that will always be inside the V CTRL window. The circuit of FIG. 4 provides the Safe V CTRL for Pull-In 42 , shown in FIG. 1 . The circuit of FIG. 4 includes transistors MN 2 , MN 8 , MN 9 , MP 6 , and MP 7 ; logic gate 52 ; and inverter 54 . Since transistor MP 7 is smaller than transistor MP 0 and there is some voltage drop across transistor MP 6 acting as a switch, the voltage V CTRL target voltage will be a little less than voltage Vcmph. The switching of transistors MP 6 and MP 8 should be done with little charge injection to the control voltage Vctrl. Transistor MN 9 is added for this reason.

In many instances, a self-biased PLL is used for its input frequency vs. loop bandwidth properties, even though bias circuits, such as bandgaps and current generators, exist. In these cases it can be advantageous to employ these references in creating both the window generator and the target pull-in circuit. FIG. 5 details a window generator when these bias circuits are available. The circuit of FIG. 5 includes transistors MN 1 , MN 3 , MN 5 , MN 7 , MP 0 , MP 3 , MP 4 , and MP 5 ; resistors R 5 and R 7 ; current sources I 1 , I 2 , I 3 and I PTAT ; and amplifier 56 . The currents Vbgap/R are developed from a bandgap reference voltage and an on-chip resistor. Using this current I 1 through resistor R 7 , a bandgap voltage is generated and applied to the stack of transistors MP 3 , MP 4 , and MP 5 to develop a current that's proportional to p-channel strength. This current is subtracted from another Vbgap/R current I 2 at node V BN . Transistor MN 1 mirrors this current to transistor MPO. To compensate for temperature variations, a PTAT (proportional to absolute temperature) current I PTAT is added to the current from transistor MN 1 . The difference between control limits Vcmph and Vcmpl can be accurately controlled by applying a Vbgap/R current I 3 through resistor R 5 . This will make the voltage difference temperature independent.

To generate the target pull-in voltage V CTRL when reference biases exist, currents developed from mirrors of currents I MN1 and I PTAT can be used as in FIG. 6 . The circuit of FIG. 6 is similar to the circuit of FIG. 4 with the addition of current source I 4 which is an I PTAT current source. Also, voltage V BN (from FIG. 5 ) is applied to the gate of transistor MN 2 instead of voltage Vcn in FIG. 4 . This will have the same tracking properties as in FIG. 4 .

This solution will keep the window for the VCO control voltage more narrow around its process dependent operating point. This keeps the VCO frequency range limited so that it will not reach a point where it will not oscillate due to insufficient loop gain. Also, when the VCO control voltage is outside of the window, the control voltage is pulled more rapidly into the narrow window where it then proceeds to lock in a normal (slower) fashion, the PLL will tend to lock more quickly when the control voltage is at either supply rail. Keeping the window dynamic and narrow also has the added advantage of limiting the VCO frequency which can simplify the design of the blocks that follow the VCO.

While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.