Switching control circuit having off-time modulation to improve efficiency of primary-side controlled power supply

1. Field of the Invention

The present invention relates to a control circuit for a power supply, and more specifically, to a switching control circuit for switching mode power supplies.

2. Description of Related Art

Various power supplies have been widely used to provide regulated voltage. For the sake of safety, an off-line power supply is used to provide galvanic isolation between its primary side and secondary side. An optical-coupler and a secondary-side regulator are usually needed for regulating the output voltage of the off-line power supply. In order to reduce the device count and do without the secondary feedback circuit, a primary-side control technique has been disclosed in U.S. Pat. No. 4,302,803 “Rectifier-Converter Power Supply with Multi-Channel Flyback Inverter,” issued to Randolph D. W. Shelly, on Nov. 24, 1981. However, foregoing prior art cannot meet the standard of accurate output voltage. Further, in such a design, the power consumption at light load condition is significantly high. Accordingly, the object of the present invention is to provide a switching control circuit for precisely controlling the output voltage of a power supply at the primary side without the optical-coupler and secondary-side regulator. In addition, an off-time modulation is developed to reduce the switching frequency and save the power consumption of the power supply at the light load condition.

A switching control circuit for a primary-side controlled power supply of the present invention comprises a switch for switching a transformer. A switching signal controls the switch for regulating the output voltage of the power supply. A controller is coupled to the transformer to generate a voltage-feedback signal by multi-sampling a voltage signal and a discharge time of the transformer during the off-time of the switching signal. A first operational amplifier and a first reference voltage develop a voltage-loop error amplifier to amplify the voltage-feedback signal and generate a control signal. The controller therefore generates the switching signal in response to the control signal. The controller comprises a voltage-waveform detector for multi-sampling the voltage signal and a discharge-time signal of the transformer to produce the voltage-feedback signal. The voltage-waveform detector is connected to an auxiliary winding of the transformer via a voltage divider. The discharge-time signal represents the discharge time of the transformer and stands for the discharge time of a secondary-side switching current. A PWM circuit controls the pulse width of the switching signal in response to the control signal. The output voltage is thus precisely regulated. An off-time modulator is developed to save the power consumption, in which a discharge-current signal and a standby signal are generated in response to the control signal and an under-voltage signal. The under-voltage signal indicates a low supply voltage of the controller. An oscillator is coupled to the discharge-current signal and the standby signal to generate a pulse signal for determining the off-time of the switching signal. The switching signal has a minimum switching frequency to switch the transformer for multi-sampling the voltage signal. The off-time of the switching signal is increased and the switching frequency is decreased in response to the decrease of the load and therefore the power consumption under light load condition is reduced.

It is to be understood that both the foregoing general descriptions and the following detailed descriptions are exemplary, and are intended to provide further explanation of the invention as claimed. Still further objects and advantages will become apparent from a consideration of the ensuing description and drawings.

The accompanying drawings are included to provide further understanding of the invention, and are incorporated into and constitute a part of this specification. The drawings illustrate embodiments of the invention and, and together with the description, serve to explain the principles of the invention.

FIG. 1 shows a schematic diagram of a power supply having a switching control circuit.

FIG. 2 shows key waveforms of the power supply and the switching control circuit.

FIG. 3 shows one embodiment of a controller according to the present invention.

FIG. 4 shows one embodiment of a voltage-waveform detector according to the present invention.

FIG. 5 shows one embodiment of an oscillator according to the present invention.

FIG. 6 shows one embodiment of an off-time modulator according to the present invention.

FIG. 7 shows one preferred embodiment of a PWM circuit according to the present invention.

FIG. 8 shows one preferred embodiment of a wake-up timer according to the present invention.

FIG. 9 shows one preferred embodiment of an adder according to the present invention.

FIG. 1 shows a power supply. The power supply includes a transformer 10 comprising an auxiliary winding N A , a primary winding N P , and a secondary winding N S . The primary winding N P is coupled to an input voltage V IN of the power supply. In order to regulate an output voltage V O and/or an output current I O of the power supply, a switching control circuit includes a switching signal V PWM to control a switch, such as a transistor 20 . A controller 70 generates the switching signal V PWM .

FIG. 2 shows various signal waveforms of the power supply in FIG. 1 . As the switching signal V PWM is logic-high, a primary-side switching current I P will be generated accordingly. A primary-side switching peak current I P1 can be given by,

where L P is the inductance of the primary winding N P of the transformer 10 ; T ON is an on-time of the switching signal V PWM .

Once the switching signal V PWM is logic-low, the energy stored in the transformer 10 will be transferred to the secondary side of the transformer 10 and to an output of the power supply via a rectifier 40 . A secondary-side switching current I S is thus generated accordingly. A secondary-side switching peak current I S1 can be expressed by,

where V O is the output voltage of the power supply; V F is a forward voltage drop of the rectifier 40 ; L S is the inductance of the secondary winding N S of the transformer 10 ; T DS is a discharge time of the transformer 10 , and T DS also represents the discharge time of the secondary-side switching current Is.

Meanwhile, a voltage signal V AUX is generated at the auxiliary winding N A of the transformer 10 . A voltage level V AUX1 of the voltage signal V AUX can be expressed as,

where T NA and T NS are respectively the winding turns of the auxiliary winding N A and the secondary winding N S of the transformer 10 .

The voltage signal V AUX starts to decrease as the secondary-side switching current I S drops to zero. This also indicates that the energy of the transformer 10 is fully released at this moment. Therefore, as shown in FIG. 2 , the discharge time T DS in equation (2) can be measured from the falling edge of the switching signal V PWM to the point when the voltage signal V AUX decreases. The peak value I S1 of the secondary-side switching current I S is determined by the peak value I P1 of the primary-side switching current I P and the winding turns of the transformer 10 . The peak value I S1 of the secondary-side switching current I S can be expressed as,

I S1 = T NP T NS × I P1 ( 4 )

where T NP is the winding turns of the primary winding N P of the transformer 10 .

The controller 70 comprises a power terminal VCC and a ground terminal GND for being powered. A voltage divider, formed by a resistor 50 and a resistor 51 , for instance, is connected between the auxiliary winding N A of the transformer 10 and a ground reference level. A detection terminal DET of the controller 70 is connected to a joint of the resistor 50 and the resistor 51 . A voltage V DET generated at the detection terminal DET can be given by,

V DET = R 51 R 50 + R 51 × V AUX ( 5 )

where R 50 and R 51 are respectively the resistance of the resistor 50 and the resistor 51 .

The voltage signal V AUX further charges a capacitor 65 via a rectifier 60 for powering the controller 70 . A current-sense resistor 30 is connected from a source of the transistor 20 to the ground reference level for converting the primary-side switching current I P to be a current signal V CS . A sense terminal CS of the controller 70 is connected to the current-sense resistor 30 for detecting the current signal V CS .

An output terminal OUT of the controller 70 provides the switching signal V PWM for switching the transformer 10 . A compensation terminal COMV is connected to a compensation network for voltage-loop frequency compensation. The compensation network can be a capacitor connected to the ground reference level, such as a capacitor 31 .

FIG. 3 shows one embodiment of the controller 70 . A voltage-waveform detector 100 produces a voltage-feedback signal V FB and a discharge-time signal S DS by multi-sampling the voltage V DET . The discharge-time signal S DS represents the discharge time T DS of the secondary-side switching current I S . A positive input of an operation amplifier 71 is supplied with a reference voltage V R1 and a negative input of the operation amplifier 71 is supplied with the voltage-feedback signal V FB . The operational amplifier 71 generates a control signal V CTR .

An off-time modulator 300 is coupled to a voltage-loop error amplifier to generate a discharge-current signal I D and a standby signal V STB in response to the control signal V CTR . An oscillator 200 is coupled to the off-time modulator 300 to generate a pulse signal PLS and a ramp signal RMP. The pulse signal PLS is applied to initiate the switching signal V PWM and determine an off-time of the switching signal V PWM . A comparator 75 and a reference voltage V R2 develop a peak-current limiter to limit the maximum value of the primary-side switching current I P . The input of the peak-current limiter is coupled to the sense terminal CS to detect the current signal V CS and to achieve a cycle-by-cycle current limit. A PWM circuit 500 is coupled to comparators 73 , 75 via an NAND gate 79 to control the pulse width of the switching signal V PWM in response to the output of the voltage-loop error amplifier and the output of the peak-current limit. The NAND gate 79 generates a reset signal RST to reset the switching signal V PWM in response to the outputs of the comparators 73 and 75 .

An output of the operational amplifier 71 is connected to the compensation terminal COMV and a positive input of the comparator 73 . A negative input of the comparator 73 is connected to an output of an adder 600 . The adder 600 generates a slope signal V SLP by adding the current signal V CS with the ramp signal RMP, which forms a slope compensation for the voltage-loop.

A voltage control loop is developed from the voltage signal V AUX sampling to the pulse width modulation of the switching signal V PWM , which controls the magnitude of the voltage signal V AUX in response to the reference voltage V R1 . The voltage level V AUX1 of the voltage signal V AUX and the output voltage V O are positive correlation as shown in equation (3). The voltage signal V AUX is further attenuated to the voltage V DET as shown in equation (5). The voltage-waveform detector 100 generates the voltage-feedback signal V FB by multi-sampling the voltage V DET . The value of the voltage-feedback signal V FB is controlled in response to the value of the reference voltage V R1 via the regulation of the voltage control loop. The voltage-loop error amplifier and the PWM circuit provide the loop gain for the voltage control loop. Therefore the output voltage V O can be briefly defined as,

The voltage signal V AUX is multi-sampled by the voltage-waveform detector 100 . The voltage signal V AUX is sampled and measured instantly before the secondary-side switching current I S falls to zero. Therefore the variation of the secondary-side switching current I S does not affect the value of the forward voltage drop V F of the rectifier 40 .

FIG. 4 shows one embodiment of the voltage-waveform detector 100 according to the present invention. A sample-pulse generator 190 produces a sample-pulse signal for multi-sampling operation. A threshold signal 156 added to the voltage signal V AUX to produce a level-shift signal. A first signal generator including a D flip-flop 171 , two AND gates 165 , 166 generates a first sample signal V SP1 and a second sample signal V SP2 . A second signal generator comprises a D flip-flop 170 , a NAND gate 163 , an AND gate 164 and a comparator 155 for producing the discharge-time signal S DS . A time-delay circuit including an inverter 162 , a current source 180 , a transistor 181 and a capacitor 182 generates a delay time T d as the switching signal V PWM is logic-low. An input of an inverter 161 is supplied with the switching signal V PWM . An output of the inverter 161 is connected to an input of the inverter 162 , a first input of the AND gate 164 and a clock-input of the D flip-flop 170 . An output of the inverter 162 turns on/off the transistor 181 . A capacitor 182 is connected between a drain and a source the transistor 181 . The drain of the transistor 181 is also an output of the time-delay circuit. The current source 180 is applied to charge the capacitor 182 . Therefore the current of the current source 180 and the capacitance of the capacitor 182 determine the delay time T d of the time-delay circuit. A D-input of the D flip-flop 170 is pulled high with a supply voltage V CC . An output of the D flip-flop 170 is connected to a second input of the AND gate 164 . The AND gate 164 outputs the discharge-time signal S DS . The discharge-time signal S DS is thus enabled as the switching signal V PWM is logic-low. An output of the NAND gate 163 is connected to a reset-input of the D flip-flop 170 . Two inputs of the NAND gate 163 are respectively connected to the output of the time-delay circuit and an output of a comparator 155 . An input of the comparator 155 is applied to the level-shift signal. Another input of the comparator 155 is applied to the voltage-feedback signal V FB . Therefore, after the delay time T d , the discharge-time signal S DS can be disabled once the level-shift signal is lower than the voltage-feedback signal V FB . Besides, the discharge-time signal S DS can also be disabled as long as the switching signal V PWM is enabled.

The sample-pulse signal is applied to a clock-input of the D flip-flop 171 and third inputs of AND gates 165 and 166 . A D-input and an inverse output of the D flip-flop 171 are connected together to form a divided-by-two counter. An output and the inverse output of the D flip-flop 171 are respectively connected to second inputs of AND gates 165 and 166 . First inputs of AND gates 165 and 166 are also applied to the discharge-time signal S DS . Fourth inputs of AND gates 165 and 166 are connected to the output of the time-delay circuit. Therefore a first sample signal V SP1 and a second sample signal V SP2 are respectively generated from outputs of the AND gates 165 and 166 . Besides, the first sample signal V SP1 and the second sample signal V SP2 are alternately produced during an enabled period of the discharge-time signal S DS . However, the delay time T d is inserted at the beginning of the discharge-time signal S DS to inhibit the first sample signal V SP1 and the second sample signal V SP2 . The first sample signal V SP1 and the second sample signal V SP2 are thus disabled during the period of the delay time T d .

The first sample signal V SP1 and the second sample signal V SP2 are used for alternately sampling the voltage signal V AUX via the detection terminal DET and the voltage divider. The first sample signal V SP1 controls a switch 121 for obtaining a first hold voltage across a capacitor 110 . The second sample signal V SP2 controls a switch 122 for obtaining a second hold voltage across a capacitor 111 . A switch 123 is connected in parallel with the capacitor 110 to discharge the capacitor 110 . A switch 124 is connected in parallel with the capacitor 111 to discharge the capacitor 111 . A buffer amplifier includes operational amplifiers 150 and 151 , diodes 130 , 131 , and a current source 135 for generating a hold voltage. The positive inputs of operational amplifiers 150 and 151 are connected to the capacitor 110 and capacitor 111 respectively. The negative inputs of the operational amplifiers 150 and 151 are connected to an output of the buffer amplifier. The diode 130 is connected from an output of the operational amplifier 150 to the output of the buffer amplifier. The diode 131 is connected from an output of the operational amplifier 151 to the output of the buffer amplifier. The hold voltage is thus obtained from the higher voltage of the first hold voltage and the second hold voltage. The current source 135 is used for termination. A switch 125 periodically conducts the hold voltage to a capacitor 115 for producing the voltage-feedback signal V FB . The switch 125 is turned on/off by the pulse signal PLS. The first sample signal V SP1 and the second sample signal V SP2 start to produce the first hold voltage and the second hold voltage after the delay time T d , which eliminates the spike interference of the voltage signal V AUX . The spike of the voltage signal V AUX would be generated when the switching signal V PWM is disabled and the transistor 20 is turned off.

The voltage signal V AUX starts to decrease as the secondary-side switching current I S drops to zero, which will be detected by the comparator 155 for disabling the discharge-time signal S DS . The pulse width of the discharge-time signal S DS is therefore correlated to the discharge time T DS of the secondary-side switching current I S . Meanwhile the first sample signal V SP1 and the second sample signal V SP2 are disabled, and the multi-sampling operation is stopped when the discharge-time signal S DS is disabled. At the moment, the hold voltage generated at the output of the buffer amplifier represents an end voltage. The end voltage is thus correlated to the voltage signal V AUX that is sampled just before the secondary-side switching current I S dropping to zero. The hold voltage is obtained from the higher voltage of the first hold voltage and the second hold voltage, which will ignore the voltage that is sampled when the voltage signal starts to decrease.

FIG. 5 shows one embodiment of the oscillator 200 according to the present invention. An operational amplifier 201 , a resistor 210 and a transistor 250 form a first V-to-I converter. The first V-to-I converter generates a reference current I 250 in response to a reference voltage V REF . A plurality of transistors, such as 251 , 252 , 253 , 254 and 255 form current mirrors for generating a charge current I 253 and constant currents I 321 ,I 325 and I 329 in response to the reference current I 250 . A drain of the transistor 253 generates the charge current I 253 . A switch 230 is connected between the drain of the transistor 253 and a capacitor 215 . A first terminal of a switch 231 is connected to the capacitor 215 . A second terminal of the switch 231 is driven by the discharge-current signal I D . The ramp signal RMP is obtained across the capacitor 215 . A comparator 205 has a positive input connected to the capacitor 215 . The comparator 205 outputs the pulse signal PLS. The pulse signal PLS determines the switching frequency. A first terminal of a switch 232 is supplied with a high threshold voltage V H . A first terminal of a switch 233 is supplied with a low threshold voltage V L . A second terminal of the switch 232 and a second terminal of the switch 233 are both connected to a negative input of the comparator 205 . An input of an inverter 260 is connected to an output of the comparator 205 for producing an inverse pulse signal /PLS. The pulse signal PLS turns on/off the switch 231 and the switch 233 . The inverse pulse signal /PLS turns on/off of the switch 230 and the switch 232 .

FIG. 6 shows an embodiment of the off-time modulator 300 according to the present invention. The off-time modulator 300 is coupled to the oscillator 200 for connecting a minimum-discharge current I 329 , a maximum-discharge current I 325 and a threshold current I 321 . An operational amplifier 310 , a transistor 314 and a resistor 311 form a second V-to-I converter. The second V-to-I converter is used for generating a control current I 314 in response to the control signal V CTR . The control current I 314 is coupled to the minimum-discharge current I 329 , the maximum-discharge current I 325 and the threshold current I 321 to generate the discharge-current signal I D . The control current I 314 is coupled to delete the threshold current I 321 , and produce the discharge-current signal I D through a current mirror formed by transistors 315 and 316 . The discharge-current signal I D is lowered as the control signal V CTR decreases. As the discharge-current signal I D decreases, the period of the pulse signal PLS and the off-time of the switching signal V PWM will be extended. However, the minimum-discharge current I 329 determines a minimum value of the discharge-current signal I D . The maximum-discharge current I 325 clamps a maximum value of the discharge-current signal I D . The voltage of the control signal V CTR is proportional to the load condition. Therefore the discharge-current signal I D is lowered as the load decreases. And the minimum value and the maximum value of the discharge-current signal I D are clamped.

A comparator 331 produces a first enable signal via an inverter 350 once the control signal V CTR is lower than a threshold voltage V TH1 . The comparator 331 also produces a first disable signal via a NAND gate 351 once the control signal V CTR is higher than the threshold voltage V TH . A comparator 332 produces an under-voltage signal via a NAND gate 352 once an attenuated supply voltage of the controller is lower than a threshold voltage V TH2 . The attenuated supply voltage is attenuated from the supply voltage V CC via an attenuator, which is formed by resistors 381 and 382 . A delay counter 330 having a delay time T d1 generates a standby-enable signal once the first enable signal is enabled longer than the delay time T d1 . A standby-signal generator is formed by a register 340 , AND gates 356 , 357 . The AND gate 356 is connected to the delay counter 330 to enable the standby signal V STB in response to the standby-enable signal. The standby signal V STB is disabled via the AND gate 357 in response to the first disable signal and the under-voltage signal.

FIG. 7 shows a schematic diagram of the PWM circuit 500 according to one embodiment of the present invention. The PWM circuit 500 includes a NAND gate 511 , a D flip-flop 515 , an AND gate 519 , a blanking circuit 520 , inverters 512 , 518 , 551 and a wake-up timer 550 . A D-input of the D flip-flop 515 is pulled high with the supply voltage V CC . The pulse signal PLS drives an input of the inverter 512 . An output of the inverter 512 is connected to the clock-input of the D flip-flop 515 for enabling the switching signal V PWM . An output of the D flip-flop 515 is connected to a first input of the AND gate 519 . A second input of the AND gate 519 is coupled to the output of the inverter 512 . The AND gate 519 outputs the switching signal V PWM to switch the power supply. The switching signal V PWM is disabled as the pulse signal PLS is enabled. Therefore the pulse width of the pulse signal PLS can control the off-time of the switching signal V PWM .

A reset-input of the D flip-flop 515 is connected to an output of the NAND gate 511 . A first input of the NAND gate 511 is supplied with the reset signal RST for cycle-by-cycle disabling the switching signal V PWM . The second input of the NAND gate 511 is connected to an output of the blanking circuit 520 for ensuring a minimum on-time of the switching signal V PWM once the switching signal V PWM is enabled. The third input of the NAND gate 511 is connected to an output of the wake-up timer 550 via the inverter 551 to ensure the minimum switching frequency of the switching signal V PWM . The minimum on-time of the switching signal V PWM will ensure a minimum value of the discharge time T DS , which will ensure a proper multi-sampling operation for sampling the voltage signal V AUX in the voltage-waveform detector 100 . The discharge time T DS is related to the on-time T ON of the switching signal V PWM . With reference to equations (1), (2), (4) and (7), the discharge-time T DS can be expressed as equation (8),

An input of the blanking circuit 520 is supplied with the switching signal V PWM . When the switching signal V PWM is enabled, the blanking circuit 520 will generate a blanking signal V BLK to inhibit the reset of the D flip-flop 515 . The blanking circuit 520 further comprises a NAND gate 523 , a current source 525 , a capacitor 527 , a transistor 526 and inverters 521 , 522 . The switching signal V PWM is applied to an input of the inverter 521 and the first input of the NAND gate 523 . The current source 525 is applied to charge the capacitor 527 . The capacitor 527 is connected between a drain and a source of the transistor 526 . An output of the inverter 521 turns on/off the transistor 526 . An input of the inverter 522 is coupled to the drain of the transistor 526 . An output of the inverter 522 is connected to a second input of the NAND gate 523 . An output of the NAND gate 523 outputs the blanking signal V BLK . The current of the current source 525 and the capacitance of the capacitor 527 determine the pulse width of the blanking signal V BLK . The input of an inverter 518 is connected to the output of the NAND gate 523 . An output of the inverter 518 generates a clear signal CLR to turn on/off switches 123 and 124 .

The minimum switching frequency of the switching signal V PWM ensures a switching of the transformer 10 for multi-sampling the voltage signal V AUX . The wake-up timer 550 is coupled to the off-time modulator 300 to generate a wake-up signal and enable the switching signal V PWM in response to the standby signal V STB . A permanent reset signal RST might be produced if the voltage-waveform detector 100 samples an extremely high voltage due to the overshoot of the output voltage V O , which would result in a permanent disabled switching signal V PWM . Nevertheless, the wake-up timer 550 will enable V PWM . The timer of the wake-up timer 550 is counted by the pulse signal PLS. A reset input of the wake-up timer 550 is supplied with the blanking signal V BLK . Therefore, the wake-up timer and the wake-up signal will be reset once the switching signal V PWM is generated. A mode input of the wake-up timer 550 is coupled to the standby signal V STB . The wake-up timer 550 will generate the wake-up signal for every cycle of the pulse signal PLS as the standby signal V STB is disabled. Once the standby signal V STB is enabled, the wake-up timer 550 will generate the wake-up signal after the specific cycles of the pulse signal PLS, which ensures a minimum switching frequency of the switching signal V PWM . FIG. 8 shows a schematic diagram of the wake-up timer 550 .

FIG. 9 shows an embodiment of the adder 600 according to the present invention. An operational amplifier 610 , transistors 620 , 621 , 622 and a resistor 650 develop a third V-to-I converter for generating a current I 622 in response to the ramp signal RMP. A positive input of an operational amplifier 611 is applied to the current signal V CS . A negative input and an output of the operational amplifier 611 are connected together to build the operational amplifier 611 as a buffer. A drain of the transistor 622 is connected to the output of the operational amplifier 611 via a resistor 651 . The slope signal V SLP is generated at the drain of the transistor 622 . The slope signal V SLP is therefore correlated to the ramp signal RMP and the current signal V CS .

It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention covers modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.