High reliability triple redundant memory element with integrated testability and voting structures on each latch

This invention relates generally to latch design. More particularly, this invention relates to improving soft error immunity in latches.

High-energy neutrons lose energy in materials mainly through collisions with silicon nuclei that lead to a chain of secondary reactions. These reactions deposit a dense track of electron-hole pairs as they pass through a p-n junction. Some of the deposited charge will recombine, and some will be collected at the junction contacts. When a particle strikes a sensitive region of a latch, the charge that accumulates could exceed the minimum charge that is needed to “flip” the value stored on the latch, resulting in a soft error.

The smallest charge that results in a soft error is called the critical charge of the latch. The rate at which soft errors occur (SER) is typically expressed in terms of failures in time (FIT).

A common source of soft errors are alpha particles which may be emitted by trace amounts of radioactive isotopes present in packing materials of integrated circuits. “Bump” material used in flip-chip packaging techniques has also been identified as a possible source of alpha particles.

Other sources of soft errors include high-energy cosmic rays and solar particles. High-energy cosmic rays and solar particles react with the upper atmosphere generating high-energy protons and neutrons that shower to the earth. Neutrons can be particularly troublesome as they can penetrate most man-made construction (a neutron can easily pass through five feet of concrete). This effect varies with both latitude and altitude. In London, the effect is two times worse than on the equator. In Denver, Colo. with its mile-high altitude, the effect is three times worse than at sea-level San Francisco. In a commercial airplane, the effect can be 100–800 times worse than at sea-level.

Radiation induced soft errors are becoming one of the main contributors to failure rates in microprocessors and other complex ICs (integrated circuits). Several approaches have been suggested to reduce this type of failure. Adding ECC (Error Correction Code) or parity in data paths approaches this problem from an architectural level. Adding ECC or parity in data paths can be complex and costly.

At the circuit level, SER may be reduced by increasing the ratio of capacitance created by oxides to the capacitance created by p/n junctions. The capacitance in a latch, among other types, includes capacitance created by p/n junctions and capacitance created by oxides. Since electron/hole pairs are created as high-energy neutrons pass through a p/n junction, a reduction in the area of p/n junctions in a latch typically decreases the SER. Significant numbers of electron/hole pairs are not created when high-energy neutrons pass through oxides. As a result, the SER may typically be reduced by increasing the ratio of oxide capacitance to p/n junction capacitance in a SRAM cell.

There is a need in the art to reduce the SER in latches. An embodiment of this invention reduces the SER in triple redundant latches while adding only a small increase in physical size of the triple redundant latch and reducing the delay time through a triple redundant latch. In addition, two redundant latches are used to scan data into and from the triple redundant latch.

In a preferred embodiment, the invention provides a circuit and method for a high reliability triple redundant latch with integrated testability. Three settable memory elements set an identical logical value into each settable memory element. After the settable memory elements are set, three voting structures with inputs from the first, second, and third settable memory elements, determine the logical value held on each of the settable memory elements. Data may be scanned into and out of the second settable memory element. Data is propagated through the buffer into the third settable memory element. The third settable memory element may be used to scan data out of the triple redundant latch. The propagation delay through a latch is the only propagation delay of the triple redundant latch.

Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.

FIG. 1 is a schematic of a triple redundant latch. Prior Art

FIG. 2 is a block diagram of an embodiment of an improved triple redundant latch with integrated testability.

FIG. 3 is a block diagram of an improved triple redundant latch with integrated testability.

FIG. 4 is a schematic of an improved triple redundant latch with integrated testability.

FIG. 1 is a schematic of a triple redundant latch. The input, 100 , to the triple redundant latch is connected to the input of transfer gates, TG 1 , TG 2 , and TG 3 . Control signal, 102 , is connected to transfer gates, TG 1 , TG 2 , and TG 3 . Control signal, 102 , controls when the signal on the input of transfer gates, TG 1 , TG 2 , and TG 3 is transferred to the outputs, 104 , 106 , and 108 of transfer gates, TG 1 , TG 2 , and TG 3 respectively. The signal presented to outputs, 104 , 106 , and 108 , is stored in LATCH 1 , LATCH 2 , and LATCH 3 respectively.

After control signal, 102 , is turned off, the signal on LATCH 1 drives the input of inverter, INV 1 . After control signal, 102 , is turned off, the signal on LATCH 2 drives the input of inverter, INV 2 . After control signal, 102 , is turned off, the signal on LATCH 3 drives the input of inverter, INV 3 . The output, 110 , of inverter, INV 1 , drives an input to AND 1 and an input to AND 2 . The output, 112 , of inverter, INV 2 , drives an input to AND 1 and an input to AND 3 . The output, 114 , of inverter, INV 3 , drives an input to AND 2 and an input to AND 3 . The output, 116 , of AND 1 drives an input of OR 1 . The output, 118 , of AND 2 drives an input of OR 1 . The output, 120 , of AND 3 drives an input of OR 1 . The output of the triple redundant latch is the output, 122 of OR 1 .

A triple redundant latch reduces soft errors by storing the same data in three different latches. For example, when the control signal, 102 is on, a logical high value may be driven from the inputs, 100 , of transfer gates, TG 1 , TG 2 , and TG 3 to the outputs, 104 , 106 , and 108 , of transfer gates, TG 1 , TG 2 , and TG 3 respectively. After turning control signal 102 off, a logical high value is stored in latches, LATCH 1 , LATCH 2 , and LATCH 3 . The stored logical high value on LATCH 1 drives the input of inverter, INV 1 , and produces a logical low value on the output, 110 , of inverter, INV 1 . The stored logical high value on LATCH 2 drives the input of inverter, INV 2 , and produces a logical low value on the output, 112 , of inverter, INV 2 . The stored logical high value on LATCH 3 drives the input of inverter, INV 3 , and produces a logical low value on the output, 114 , of inverter, INV 3 .

Since the output, 110 , 112 , and 114 of inverters, INV 1 , INV 2 , and INV 3 , respectively, are low, all the inputs, 110 , 112 , and 114 to AND 1 , AND 2 , and AND 3 respectively are a logical low value. Since all the inputs, 110 , 112 , and 114 , to AND 1 , AND 2 , and AND 3 respectively are a logical low value, the output, 116 , 118 , and 120 of AND 1 , AND 2 , and AND 3 respectively are a logical low value. Since the output, 116 , 118 , and 120 of AND 1 , AND 2 , and AND 3 , respectively are a logical low value, all the inputs of OR 1 are a logical low value. Since all the inputs, 116 , 118 , and 120 to OR 1 are logical low value, the output, 122 , is logical low value.

If a soft error occurs, for example, in LATCH 2 , and changes the stored logical value from a logical high value to a logical low value, a logical low value is now presented to the input, 106 , of inverter, INV 2 . The output, 112 , of inverter, INV 2 , presents a logical high value to an input of AND 1 and AND 3 . Since, in this example, the other input, 110 to AND 1 and the other input, 114 , to AND 3 , is a logical low value, the output, 116 and 120 of AND 1 and AND 3 respectively remains a logical low value and the output, 122 , does not change. This example illustrates how a single soft error in one latch does not change the original stored value in a triple redundant latch.

As a further example, assume, in addition to the soft error in LATCH 2 , there is an additional soft error in LATCH 3 . Now, the input, 108 , to inverter, INV 3 , is a logical low value and as a result, the output, 114 , of inverter, INV 3 , is a logical high value. A logical high value in now presented to an input, 114 , of AND 2 , and to an input, 114 , of AND 3 . Since a logical low and logical high value are presented on the inputs of AND 1 , the output, 116 of AND 1 is still a logical low value. Since a logical low and logical high value are presented on the inputs of AND 2 , the output, 118 of AND 2 is still a logical low value. However, since inputs, 112 and 114 , to AND 3 are a logical high value, the output, 120 , is a logical high value. Since input, 120 , to OR 1 is a logical high value, the output, 122 , changes from a logical low value to a logical high value. This example illustrates how soft errors in two latches of a triple redundant latch do change the original stored value of the triple redundant latch.

A triple redundant latch prevents a single soft error from changing the original value stored in the latch. However, this comes at the cost of additional circuitry which results in a physically larger latch. In addition, a triple redundant may introduce time delay in the delay path of the latch. As consequence, a triple redundant latch is usually larger and slower than a single latch.

FIG. 2 is a block diagram of an embodiment of an improved triple redundant latch. In this embodiment, an identical logical value, data-in, DIN, is set into settable memory element 1 , SME 1 , settable memory element 2 , SME 2 , and settable memory element 3 , SME 3 , by controlling signal SET. After an identical logical value, DIN, is set into settable memory element 1 , SME 1 , settable memory element 2 , SME 2 , and settable memory element 3 , SME 3 , by controlling signal SET, the identical logical value is held in the three settable memory elements, SME 1 , SME 2 , and SME 3 . The voting structure, VS 1 , after an identical logical value, DIN, is set into settable memory element 1 , SME 1 , settable memory element 2 , SME 2 , and settable memory element 3 , SME 3 , determines the logical value presented on the output, VS 1 OUT, of voting structure VS 1 , based on the logical values on nodes, NOUT 2 and NOUT 3 . The voting structure, VS 2 , after an identical logical value, DIN, is set into settable memory element 1 , SME 1 , settable memory element 2 , SME 2 , and settable memory element 3 , SME 3 , determines the logical value presented on the output, VS 2 OUT, of voting structure VS 2 , based on the logical values on nodes, DOUT and SOUT. The voting structure, VS 3 , after an identical logical value, DIN, is set into settable memory element 1 , SME 1 , settable memory element 2 , SME 2 , and settable memory element 3 , SME 3 , determines the logical value presented on the output, VS 3 OUT, of voting structure VS 3 , based on the logical values on nodes, DOUT and OUT 2 .

If the logical value, DIN, stored in the settable memory element 1 , SME 1 , is disturbed by a soft error event, and the other two settable memory elements, SME 2 and SME 3 , are not disturbed by a soft error event, the voting structure 1 , VS 1 , will restore the original logical value stored in the settable memory element 1 , SME 1 .

If the logical value, DIN, stored in the settable memory element 2 , SME 2 , is disturbed by a soft error event, and the other two settable memory elements, SME 1 and SME 3 , are not disturbed by a soft error event, the voting structure 2 , VS 2 , will restore the original logical value stored in the settable memory element 2 , SME 2 .

If the logical value, DIN, stored in the settable memory element 3 , SME 3 , is disturbed by a soft error event, and the other two settable memory elements, SME 1 and SME 2 , are not disturbed by a soft error event, the voting structure 3 , VS 3 , will restore the original logical value stored in the settable memory element 3 , SME 3 .

If the logical value stored in settable memory element two, SME 2 , is disturbed by a soft error event, the voting structures, VS 1 and VS 3 , will tri-state their outputs, VS 1 OUT and VS 3 OUT respectively, leaving the original logical value stored in settable memory elements, SME 1 and SME 3 . If the two settable memory elements, for example, SME 2 and SME 3 , are disturbed by a soft error event, at nearly the same time, the logical value original stored in the triple redundant latch may fail. The triple redundant latch will most likely not fail unless two or more soft error events occur at nearly the same time. If a single soft error event occurs and changes the logical value on a settable memory element, the voting structure on that settable memory element will restore the correct value to that settable memory element.

The original logical value stored in the triple redundant latch may be scanned from the triple redundant latch for test purposes. The logical value, DIN, held on settable memory 2 , SM 2 , is presented to the input, OUT 2 , of buffer 1 , BUF 1 . The output, BOUT, of buffer 1 , BUF 1 , is presented to the input of transfer gate 9 , TG 9 . Activating control signal, NSHIFT, with the system clocks halted, allows the logical value presented on BOUT to be propagated to the output, SOUT. The logical value on SOUT may be scanned to a tester to be evaluated.

Scan data, SIN, may also be scanned into the triple redundant latch. When control signal, SHIFT, is activated and control signal, SET, is inactivated, and the system clocks are halted, scan data, SIN, may be scanned into settable memory element 2 , SME 2 . Next, the scan data may be scanned into settable memory element 3 , SME 3 , by keeping control signal, SET, inactivated, inactivating control signal SHIFT, and activating control signal, NSHIFT. The logical value scanned into settable memory elements, SME 2 and SME 3 , may be forced into settable memory element 1 , SME 1 , if control signal, TEST 2 is high, and control signal, NTEST 2 , is low. Because the output, VS 1 OUT, of voting structure 1 , VS 1 , produces the same logical value that is scanned into settable memory elements, SME 2 and SME 3 , the same logical value scanned into settable memory elements, SME 2 and SME 3 , may be forced onto settable memory element 1 , SME 1 .

During sample-on-the-fly, a test mode may be turned on with the system clocks running. The initial logical values stored in settable memory elements, SME 2 and SME 3 will be the same as the logical value stored in settable memory element, SME 1 . As the system clocks run, the logical value in settable memory element 1 , SME 1 , will possibly change. On any subsequent system clock cycle, the signal, SAMPLE, may be activated to load the latest value from settable memory element 1 , SME 1 , to settable memory elements, SME 2 and SME 3 . After loading this logical value into settable memory elements, SME 2 and SME 3 , the logical value may be scanned out using the control signals, SHIFT and NSHIFT.

The propagation delay through the triple redundant latch shown in FIG. 2 is determined only by the propagation delay of settable memory element, SME 1 . This embodiment of the invention significantly improves the delay time of a triple redundant latch. The delay time through the prior art shown in FIG. 1 , for example, includes the propagation delay through the slowest latch among latches LATCH 1 , LATCH 2 , and LATCH 3 , the propagation delay through an inverter, INV 2 , the propagation delay through an AND gate, AND 2 , and the propagation delay through an OR gate, OR 1 .

FIG. 3 is a block diagram of a triple redundant latch with improved delay, higher reliability, and integrated testability. The input of the triple redundant latch shown in this example is connected to the inputs, DIN, of transfer gates, TG 1 , and TG 3 . In addition, a tristatable input inverter, a cross-coupled NAND gate, and a cross-coupled NOR gate may used in place of a transfer gate. If the control signal, SET, is on, the signal at the input, DIN, of transfer gates, TG 1 and TG 3 , is transferred to the output, DOUT, of transfer gate 1 , TG 1 , and the output, 300 , of transfer gate 3 , TG 3 . The logical value presented on the output, DOUT, of transfer gate TG 1 , is also an input to latch 1 , L 1 . The logical value presented on the output, 300 , of transfer gate TG 3 , is also an input to transfer gate 4 , TG 4 . If transfer gate 4 , TG 4 , is activated, the logical value on the input, 300 , will be presented to the input of latch 2 , L 2 . The logical value presented on the output, SOUT, of transfer gates TG 8 and TG 9 , is also connected to the input, SOUT, of the latch 3 , L 3 .

The output, NOUT 2 , of latch 2 , L 2 , is connected to an input of voting structure, VS 1 , and the output of transfer gate 7 , TG 7 . The output, NOUT 3 , of latch 3 , L 3 , is connected to an input of the voting structure, VS 1 and to the output of transfer gate 10 , TG 10 .

The input, DOUT, of latch 1 , L 1 , is connected to an input of voting structure, VS 2 , an input of voting structure, VS 3 , the output of transfer gate 2 , TG 2 and the input of transfer gate 6 , TG 6 . The input, OUT 2 , of latch 2 , L 2 , is connected to an input of the voting structure, VS 3 , the output of transfer gate 5 , TG 5 , the input of buffer 1 , BUF 1 and to the output of transfer gate 6 , TG 6 . The input, SOUT, of latch 3 , L 3 , is connected to an input of the voting structure, VS 2 , the output of transfer gate 8 , TG 8 , and the output of transfer gate 9 , TG 9 .

As an example of how redundancy applies for this embodiment, assume that a logical high value is stored. Storage nodes DOUT, OUT 2 , and SOUT each have a logical high value stored in this example. The output, NOUT 2 , of latch 2 , L 2 , provides a logical low value to an input of voting structure 1 , VS 1 . The output, NOUT 3 , of latch 3 , L 3 , provides a logical low value to an input of voting structure 1 , VS 1 . Since both inputs to the voting structure, VS 1 , are a low logical value, the output is a logical high value. If the control signal, TEST 2 is activated, the high logical value on VS 1 OUT is transferred to DOUT.

If, in this example, a soft error event changes the logical value stored on latch 1 , L 1 , from a logical high value to a logical low value, voting structure 1 , VS 1 , will restore the original logical high value stored in latch 1 , L 1 , restoring the triple redundant latch to its original undisturbed state. As a result, the triple redundant latch retains the original logical value stored on it despite a single soft error.

If, in this example, a soft error event changes the logical value stored on latch 2 , L 2 , from a logical high value to a logical low value, voting structure 1 , VS 1 , will be tri-stated and the original value stored in latch 1 , L 1 , will remained a logical high value. As a result, the triple redundant latch retains the original logical value stored on it despite a single soft error.

If, in this example, a soft error event changes the logical value stored on latch 3 , L 3 , from a logical high value to a logical low value, voting structure 1 , VS 1 , will be tri-stated and the original value stored in latch 1 , L 1 , will remained a logical high value. As a result, the triple redundant latch retains the original logical value stored on it despite a single soft error.

If, however, in this example, a soft error event changes the values stored on nodes OUT 2 and SOUT, at nearly the same time, the triple redundant latch may change from its original value. If a soft error event changes the logical values stored on nodes OUT 2 and OUT 3 , at nearly the same time, from logical high values to a logical low values, the inputs, NOUT 2 and SOUT, to voting structure 1 , VS 1 , change from logical low values to logical high values. As a result of having logical high values on the inputs, NOUT 2 and SOUT, the output, VS 1 OUT, of voting structure 1 , VS 1 , is a logical low value. As a result, the logical value stored on DOUT is changed from the original logical high value to a logical low value. In this example, the original value stored in the triple redundant latch is changed from a logical high value to a logical low value. The triple redundant latch should not fail unless two or more soft error events occur at nearly the same time. If a single soft error event occurs and changes the logical value on a settable memory element, the voting structure on that settable memory element will restore the correct value to that settable memory element.

The original logical value stored in the triple redundant latch may be scanned from the triple redundant latch for test purposes. The logical value held in latch 2 , L 2 , is presented to the input, OUT 2 , of buffer 1 , BUF 1 . The output, BOUT, of buffer 1 , BUF 1 , is presented to the input of transfer gate 9 , TG 9 . Activating control signal, NSHIFT, allows the logical value presented on BOUT to be propagated to the output, SOUT and stored in latch 3 , L 3 . The logical value on SOUT may be scanned to a tester to be evaluated.

Scan data, SIN, may also be scanned into the triple redundant latch. When control signal, SHIFT, is activated and control signal, SET, is inactivated, scan data, SIN, may be transferred through transfer gate 5 , TG 5 , into latch 2 , L 2 . Next, the scan data is propagated through buffer 1 , BUF 1 , and presented to the input of transfer gate 9 , TG 9 . Scan data may be scanned into latch 3 , L 3 , by keeping control signal, SET, inactivated, inactivating control signal SHIFT, and activating control signal, NSHIFT. The logical value scanned into latches, L 2 and L 3 , may be forced into latch 1 , L 1 , when control signal, TEST 2 , is active. Because the output, VS 1 OUT, of voting structure 1 , VS 1 , produces the same logical value that is scanned into latches, L 2 and L 3 , the same logical value scanned into latches, L 2 and L 3 , may be forced onto latch 1 , L 1 .

During sample-on-the-fly, a test mode may be turned on with the system clocks running. The initial logical values stored in latches, L 2 and L 3 will be the same as the logical value stored in latch 1 , L 1 . As the system clocks run, the logical value in latch 1 , L 1 , will possibly change. On any subsequent system clock cycle, the signal, SAMPLE, may be activated to load the latest value from latch 1 , L 1 , to latches, L 2 and L 3 . After loading this logical value into latches, L 2 and L 3 , the logical value may be scanned out using the control signals, SHIFT and NSHIFT.

In addition to improving the soft error rate of a latch, the triple redundant latch shown in FIG. 3 also reduces the delay time through a triple redundant latch because the number of logic delays is reduced.

FIG. 4 is a schematic of an improved triple redundant latch. FIG. 4 contains the same basic blocks that FIG. 3 contains; transfer gate 1 , TG 1 , transfer gate 2 , TG 2 , transfer gate 3 , TG 3 , transfer gate 4 , TG 4 , transfer gate 5 , TG 5 , transfer gate 6 , TG 6 , transfer gate 7 , TG 7 , transfer gate 8 , TG 8 , transfer gate 9 , TG 9 , transfer gate 10 , TG 10 , latch 1 , L 1 , latch 2 , L 2 , latch 3 , L 3 , voting structure 1 , VS 1 , voting structure 2 , VS 2 , voting structure 3 , VS 3 , and buffer 1 , BUF 1 .

An embodiment of a transfer gate 1 , TG 1 , for the triple redundant latch contains a PFET, MP 2 and an NFET MN 2 . In this embodiment, the drains of PFET, MP 2 , and NFET, MN 2 , are connected to the input, DIN, of transfer gate 1 , TG 1 . The sources of PFET, MP 2 , and NFET, MN 2 , are connected to the output, DOUT, of transfer gate 1 , TG 1 . The gate of PFET, MP 2 , is connected to the control input, NSET, of transfer gate 1 , TG 1 . The gate of NFET, MN 2 , is connected to the control input, SET, of transfer gate 1 , TG 1 .

An embodiment of a transfer gate 3 , TG 3 , for the triple redundant latch contains a PFET, MP 1 and an NFET MN 1 . In this embodiment, the drains of PFET, MP 1 , and NFET, MN 1 , are connected to the input, DIN, of transfer gate 3 , TG 3 . The sources of PFET, MP 1 , and NFET, MN 1 , are connected to node, 400 , of transfer gate 3 , TG 3 . The gate of PFET, MP 1 , is connected to the control input, TEST 1 , of transfer gate 3 , TG 3 . The gate of NFET, MN 1 , is connected to the control input, NTEST 1 , of transfer gate 3 , TG 3 .

An embodiment of a transfer gate 2 , TG 2 , for the triple redundant latch contains a PFET, MP 12 and an NFET MN 12 . In this embodiment, the drains of PFET, MP 12 , and NFET, MN 12 , are connected to, VS 1 OUT, of transfer gate 2 , TG 2 . The sources of PFET, MP 12 , and NFET, MN 12 , are connected to the output, DOUT, of transfer gate 2 , TG 2 . The gate of PFET, MP 12 , is connected to the control input, NTEST 2 , of transfer gate 2 , TG 2 . The gate of NFET, MN 12 , is connected to the control input, TEST 2 , of transfer gate 2 , TG 2 .

An embodiment of a transfer gate 4 , TG 4 , for the triple redundant latch contains a PFET, MP 3 and an NFET MN 3 . In this embodiment, the drains of PFET, MP 3 , and NFET, MN 3 , are connected to the input, 400 , of transfer gate 4 , TG 4 . The sources of PFET, MP 3 , and NFET, MN 3 , are connected to the output, OUT 2 , of transfer gate 4 , TG 4 . The gate of PFET, MP 3 , is connected to the control input, NSET, of transfer gate 4 , TG 4 . The gate of NFET, MN 3 , is connected to the control input, SET, of transfer gate 4 , TG 4 .

An embodiment of a transfer gate 7 , TG 7 , for the triple redundant latch contains a PFET, MP 13 and an NFET MN 13 . In this embodiment, the drains of PFET, MP 13 , and NFET, MN 13 , are connected to, VS 2 OUT, of transfer gate 7 , TG 7 . The sources of PFET, MP 13 , and NFET, MN 13 , are connected to the output, NOUT 2 , of transfer gate 7 , TG 7 . The gate of PFET, MP 13 , is connected to the control input, TEST 1 , of transfer gate 7 , TG 7 . The gate of NFET, MN 13 , is connected to the control input, NTEST 1 , of transfer gate 7 , TG 7 .

An embodiment of a transfer gate 10 , TG 10 , for the triple redundant latch contains a PFET, MP 14 and an NFET MN 14 . In this embodiment, the drains of PFET, MP 14 , and NFET, MN 14 , are connected to the input, VS 3 OUT, of transfer gate 10 , TG 10 . The sources of PFET, MP 14 , and NFET, MN 14 , are connected to the output, NOUT 3 , of transfer gate 10 , TG 10 . The gate of PFET, MP 14 , is connected to the control input, TEST 1 , of transfer gate 10 , TG 10 . The gate of NFET, MN 14 , is connected to the control input, NTEST 1 , of transfer gate 10 , TG 10 .

An embodiment of a transfer gate 5 , TG 5 , for the triple redundant latch contains an NFET MN 21 . In this embodiment, the drain of NFET, MN 21 , is connected to the input, SIN, of transfer gate 5 , TG 5 . The source of NFET, MN 21 , is connected to the output, OUT 2 , of transfer gate 5 , TG 5 . The gate of NFET, MN 21 , is connected to the control input, SHIFT, of transfer gate 5 , TG 5 .

An embodiment of a transfer gate 6 , TG 6 , for the triple redundant latch contains an NFET MN 24 . In this embodiment, the drain of NFET, MN 24 , is connected to the input, DOUT, of transfer gate 6 , TG 6 . The source of NFET, MN 24 , is connected to the output, OUT 2 , of transfer gate 6 , TG 6 . The gate of NFET, MN 24 , is connected to the control input, SAMPLE, of transfer gate 6 , TG 6 .

An embodiment of a transfer gate 8 , TG 8 , for the triple redundant latch contains an NFET MN 22 . In this embodiment, the drain of NFET, MN 22 , is connected to the input, BOUT, of transfer gate 8 , TG 8 . The source of NFET, MN 22 , is connected to the output, SOUT, of transfer gate 8 , TG 8 . The gate of NFET, MN 22 , is connected to the control input, SAMPLE, of transfer gate 8 , TG 8 .

An embodiment of a transfer gate 9 , TG 9 , for the triple redundant latch contains an NFET MN 23 . In this embodiment, the drain of NFET, MN 23 , is connected to the input, BOUT, of transfer gate 9 , TG 9 . The source of NFET, MN 23 , is connected to the output, SOUT, of transfer gate 9 , TG 9 . The gate of NFET, MN 23 , is connected to the control input, NSHIFT, of transfer gate 9 , TG 9 .

An embodiment of latch 1 , L 1 , for the triple redundant latch contains PFET, MP 6 , NFET, MN 6 , PFET, MP 7 , and NFET, MN 7 . In this embodiment, the gate of PFET, MP 6 , and the gate of NFET, MN 6 , is connected to the drain of PFET, MP 7 and to the drain of NFET, MN 7 , the input, DOUT, of latch 1 , L 1 . The drain of PFET, MP 6 , and the drain of NFET, MN 6 , is connected to the gate of PFET, MP 7 and to the gate of NFET, MN 7 , the output, 401 , of latch 1 , L 1 . The sources of PFET, MP 6 and PFET, MP 7 are connected to VDD. The sources of NFET, MN 6 , and NFET, MN 7 are connected to GND.

An embodiment of latch 2 , L 2 , for the triple redundant latch contains PFET, MP 8 , NFET, MN 8 , PFET, MP 9 , and NFET, MN 9 . In this embodiment, the gate of PFET, MP 8 , and the gate of NFET, MN 8 , is connected to the drain of PFET, MP 9 and to the drain of NFET, MN 9 , the input, OUT 2 , of latch 2 , L 2 . The drain of PFET, MP 8 , and the drain of NFET, MN 8 , is connected to the gate of PFET, MP 9 and to the gate of NFET, MN 9 , the output, NOUT 2 , of latch 2 , L 2 . The sources of PFET, MP 8 and PFET, MP 9 are connected to VDD. The sources of NFET, MN 8 , and NFET, MN 9 are connected to GND.

An embodiment of latch 3 , L 3 , for the triple redundant latch contains PFET, MP 10 , NFET, MN 10 , PFET, MP 11 , and NFET, MN 11 . In this embodiment, the gate of PFET, MP 10 , and the gate of NFET, MN 10 , is connected to the drain of PFET, MP 11 and to the drain of NFET, MN 11 , the input, SOUT, of latch 3 , L 3 . The drain of PFET, MP 10 , and the drain of NFET, MN 10 , is connected to the gate of PFET, MP 11 and to the gate of NFET, MN 11 , the output, NOUT 3 , of latch 3 , L 3 . The sources of PFET, MP 10 and PFET, MP 11 are connected to VDD. The sources of NFET, MN 10 , and NFET, MN 11 are connected to GND.

An embodiment of voting structure 1 , VS 1 , for the triple redundant latch contains PFET, MP 15 , PFET, MP 16 , NFET, MN 15 , and NFET, MN 16 . In this embodiment, the gates of PFET, MP 15 , and NFET, MN 15 , are connected to the first input, NOUT 2 , of voting structure 1 , VS 1 . The gates of PFET, MP 16 , and NFET, MN 16 , are connected to the second input, NOUT 3 , of the voting structure 1 , VS 1 . The source of PFET, MP 15 , is connected to VDD. The source of NFET, MN 15 , is connected to GND. The drain, 403 , of PFET, MP 15 , is connected to the source of PFET, MP 16 , 403 . The drain, VS 1 OUT, of PFET, MP 16 , is connected to the drain of NFET, MN 16 , and VS 1 OUT. The source, 404 , of NFET, MN 16 , is connected to the drain of NFET, MN 15 , 404 .

An embodiment of voting structure 2 , VS 2 , for the triple redundant latch contains PFET, MP 17 , PFET, MP 18 , NFET, MN 17 , and NFET, MN 18 . In this embodiment, the gates of PFET, MP 17 , and NFET, MN 17 , are connected to the first input, DOUT, of voting structure 2 , VS 2 . The gates of PFET, MP 18 , and NFET, MN 18 , are connected to the second input, SOUT, of the voting structure 2 , VS 2 . The source of PFET, MP 17 , is connected to VDD. The source of NFET, MN 17 , is connected to GND. The drain, 405 , of PFET, MP 17 , is connected to the source of PFET, MP 18 , 405 . The drain, VS 2 OUT, of PFET, MP 18 , is connected to the drain of NFET, MN 18 , and VS 2 OUT. The source, 406 , of NFET, MN 18 , is connected to the drain of NFET, MN 17 , 406 .

An embodiment of voting structure 3 , VS 3 , for the triple redundant latch contains PFET, MP 19 , PFET, MP 20 , NFET, MN 19 , and NFET, MN 20 . In this embodiment, the gates of PFET, MP 19 , and NFET, MN 19 , are connected to the first input, OUT 2 , of voting structure 3 , VS 3 . The gates of PFET, MP 20 , and NFET, MN 20 , are connected to the second input, DOUT, of the voting structure 3 , VS 3 . The source of PFET, MP 19 , is connected to VDD. The source of NFET, MN 19 , is connected to GND. The drain, 407 , of PFET, MP 17 , is connected to the source of PFET, MP 18 , 407 . The drain, VS 3 OUT, of PFET, MP 20 , is connected to the drain of NFET, MN 20 , and VS 3 OUT. The source, 408 , of NFET, MN 20 , is connected to the drain of NFET, MN 19 , 408 .

An embodiment of Buffer 1 , BUF 1 , for the triple redundant latch contains PFET, MP 4 , NFET, MN 4 , PFET, MP 5 , and NFET, MN 5 . In this embodiment, the gate of PFET, MP 4 , and the gate of NFET, MN 4 , is connected to the input of BUF 1 , OUT 2 . The drain of PFET, MP 4 , and the drain of NFET, MN 4 , is connected to the gate of PFET, MP 5 and to the gate of NFET, MN 5 , 402 . The drain of PFET, MP 5 , and NFET, MN 5 , are connected to the output of buffer 1 , BUF 1 , BOUT. The sources of PFET, MP 4 and PFET, MP 5 are connected to VDD. The sources of NFET, MN 4 , and NFET, MN 5 are connected to GND.

FIG. 4 is a schematic of an improved triple redundant latch. An input signal drives the inputs, DIN, of transfer gate 1 , TG 1 , and transfer gate 3 , TG 3 . If control signal, SET is a logical high value, control signal, NSET, is a logical low value, and transfer gate 3 , TG 3 , is active, the signal at the input, DIN, of transfer gate 1 , TG 1 , and transfer gate 3 , TG 3 is transferred to the output, DOUT, of transfer gate 1 , TG 1 , and the output, OUT 2 , of transfer gate 4 , TG 4 .

The signal transferred to nodes DOUT, OUT 2 , and SOUT is also presented to the input, DOUT, of latch 1 , L 1 , the input, OUT 2 , of latch 2 , L 2 , and the input SOUT, of latch 3 , L 3 . Latches L 1 , L 2 , and L 3 store the same logical value. The outputs, 401 , NOUT 2 , and NOUT 3 , of latches, L 1 , L 2 and L 3 respectively, output the opposite sense of the logical value stored. The outputs, NOUT 2 and NOUT 3 , of latches, L 2 , and L 3 respectively, are inputs to voting structure, VS 1 . The inputs, NOUT 2 and NOUT 3 , into voting structure 1 , VS 1 , cause the output, VS 1 OUT, of voting structure 1 , VS 1 , to reinforce the signal presented at the input, DOUT, of latch 1 , L 1 , when the transfer gate 1 , TG 1 is off and transfer gate 2 , TG 2 is on.

The inputs, OUT 2 and DOUT, into voting structure 3 , VS 3 , cause the output, VS 3 OUT, of voting structure 3 , VS 3 , to reinforce the signal presented at the output, SOUT, of latch 3 , L 3 , when the transfer gates, TG 8 and TG 9 , are off and transfer gate 10 , TG 10 is on.

The inputs, SOUT and DOUT, into voting structure 2 , VS 3 , cause the output, VS 2 OUT, of voting structure 2 , VS 2 , to reinforce the signal presented at the input, OUT 2 , of latch 2 , L 2 , when the transfer gates, TG 4 and TG 5 , are off and transfer gate 10 , TG 10 is on.

After control input, SET, is driven to a logical low value, and control input, NSET, is driven to a logical high value, latch 1 , L 1 , latch 2 , L 2 , and latch 3 , L 3 store the original logical value presented on nodes DOUT, OUT 2 , and SOUT, respectively. If none of the nodes, DOUT, OUT 2 , and SOUT, is disturbed, then a signal of the same sense is presented on the output, DOUT, of the triple redundant latch.

For example, if a logical high value is stored on nodes DOUT, OUT 2 , and SOUT, then a logical high value is presented on the output, DOUT, of the triple redundant latch. A logical low value on the output, NOUT 2 , of latch 2 , L 2 , is applied to the first input of voting structure 1 , VS 1 . A logical low value on the output, NOUT 3 , of latch 3 , L 3 , is applied to the second input of voting structure 1 , VS 1 . Because control signal NTEST 2 is low and control signal TEST 2 is high, a logical high value is transferred from the input, VS 1 OUT, of the second transfer gate, TG 2 , to the input of latch 1 , L 1 . With these logical values applied to voting structure 1 , VS 1 , the output, DOUT, of the triple redundant latch, remains a high logical value.

If in this example where a logical high value is stored on nodes, DOUT, OUT 2 , and SOUT, node DOUT is changed to a logical low value by a soft error event, DOUT will be recovered to a high logical value because the output, VS 1 OUT, of the voting structure, VS 1 , remains high. Since TEST 2 is a logical high value and NTEST 2 is a logical low value, the high value on VS 1 OUT is transferred to DOUT.

If a single soft error event changes the logical value stored in latch 3 , L 3 , voting structure 1 , VS 1 , will tri-state and not disturb the correct value on DOUT. If a single soft error event changes the logical value stored in latch 2 , L 2 , voting structure 1 , VS 1 , will tri-state and not disturb the correct value on DOUT.

If, however, a soft error event changes the values stored on nodes, OUT 2 and SOUT, at nearly the same time, the triple redundant latch may change from its original value. For example, if a logical high value is stored on nodes DOUT, OUT 2 , and SOUT, a logical high value is presented on the output, DOUT, of the triple redundant latch. If a soft error event changes the logical value stored on nodes, OUT 2 and SOUT, at nearly the same time, from a logical high value to a logical low value, inputs, NOUT 2 and NOUT 3 , into voting structure 1 , VS 1 , change from logical low values to logical high values. Since inputs, NOUT 2 and NOUT 3 , of voting structure 1 , VS 1 , are a logical high value, the output, VS 1 OUT, is pulled to a logical low value. Because transfer gate 2 , TG 2 , is on, the high logical value stored on latch 1 , L 1 , is then flipped to a logical low value. The output, DOUT, of the triple redundant latch, is then changed from a logical high value to a logical low value. The triple redundant latch should not fail unless two or more soft error events occur at nearly the same time. If a single soft error event occurs and changes the logical value on a settable memory element, the voting structure on that settable memory element will restore the correct value to that settable memory element.

The original logical value stored in the triple redundant latch may be scanned from the triple redundant latch for test purposes. The logical value held in latch 2 , L 2 , is presented to the input, OUT 2 , of buffer 1 , BUF 1 . The output, BOUT, of buffer 1 , BUF 1 , is presented to the input of transfer gate 9 , TG 9 . Driving control signal, NSHIFT, high, and driving control signal, SHIFT, low, allows the logical value presented on BOUT to be propagated to the output, SOUT and stored in latch 3 , L 3 . The logical value on SOUT may be scanned to a tester to be evaluated.

Scan data, SIN, may also be scanned into the triple redundant latch. When control signal, SHIFT, is driven high, NSHIFT, is driven low, and control signal, SET, is driven low, scan data, SIN, may be transferred through transfer gate 5 , TG 5 , into latch 2 , L 2 . Next, the scan data is propagated through buffer 1 , BUF 1 , and presented to the input of transfer gate 9 , TG 9 . Scan data may be scanned into latch 3 , L 3 , by keeping control signal, SET, low, driving control signal SHIFT, low, and driving control signal, NSHIFT, high. The logical value scanned into latches, L 2 and L 3 , is then forced into latch 1 , L 1 , because the output, VS 1 OUT, of voting structure 1 , VS 1 , produces the same logical value when latches, L 2 and L 3 , have the same logical value.

During sample-on-the-fly, the test mode may be turned on with the system clocks running. The initial logical values stored in latches, L 2 and L 3 will be the same as the logical value stored in latch 1 , L 1 . As the system clocks run, the logical value in latch 1 , L 1 , will possibly change. On any subsequent system clock cycle, the signal, SAMPLE, may be activated to load the latest value from latch 1 , L 1 , to latches, L 2 and L 3 . After loading this logical value into latches, L 2 and L 3 , the logical value may be scanned out using the control signals, SHIFT and NSHIFT.

In addition to improving the soft error rate of a latch, the triple redundant latch shown in FIG. 4 also reduces the delay time through a triple redundant latch because the number of logic delays is reduced.

The foregoing description of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and other modifications and variations may be possible in light of the above teachings. The embodiment was chosen and described in order to best explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and various modifications as are suited to the particular use contemplated. It is intended that the appended claims be construed to include other alternative embodiments of the invention except insofar as limited by the prior art.