Frequency tuning loop for active RC filters

1. Field of the Invention

The present invention relates to an analog filter circuit, and more particularly to a frequency tuning loop capable of continuously tuning and compensating the cut-off frequency of a filter.

2. Description of the Prior Art

A filter, which is common and the most important element in a typical signal process system, is configured to eliminate the unnecessary frequency signal for preserving or amplifying the required frequency signal (a filter generally refers to a component which allows/passes a range of frequencies and rejects all other frequencies from an input signal). The filter integrated into the chip is a trend in the development of integrated circuit process. However, many factors can not be properly controlled in integrated circuit process to maintain electrical elements at their perfect properties. Furthermore, the circuit integration may cause the unstable performance of the electrical elements according to the environment and time in use. For example, according to a portable communication product in rapid development, a set of circuit system may be applied in any environments to cause the cut-off frequency of filter aberrant from a preset value. Thus, it is an important key for the signal process of communication system to compensate and keep the cut-off frequency at a preset level.

The cut-off frequency of a filter is proportional to the reciprocal of time constant τ(i.e. f=½πτ) and the time constant τ is the product of equivalent resistance and capacitance (i.e. τ=R×C) of the active RC filter. Therefore, the cut-off frequency may be tuned to a preset value by efficiently controlling the equivalent resistance or equivalent capacitance in an active RC filter. Accordingly aforementioned, a tuning loop is added in the general RC filter for tuning the cut-off frequency back to the preset value by immediately tuning the equivalent resistance or equivalent capacitance in the filter, as soon as the original cut-off frequency of the filter is aberrant. FIG. 1 is a schematic diagram illustrating a known tuning loop. In general, input signal 112 is processed by the RC filter 110 and then output signal 114 outputs from the RC filter 110 . As soon as the time constant of the RC filter 110 is aberrant from a preset value (compared through the line 122 ) and detected by the tuning loop 120 , a tuning signal is generated from line 124 . Then, the equivalent resistance or equivalent capacitance in the RC filter 110 is tuned for making the cut-off frequency back to the original setting.

FIG. 2A is the typical circuit of a tuning loop with a resistor R 22 and a capacitor C 22 as the equivalent resistor and equivalent capacitor in the filter. When the constant current sources I 22 , I 24 with a constant current ratio are respectively through the resistor R 22 and capacitor C 22 , a voltage V 22 is generated across the resistor R 22 , while the voltage V 24 of the capacitor C 22 will increase in accordance with the charging of the capacitor C 22 shown in FIG. 2B . When the constant current source begins charging to the capacitor C 22 , the pulse comparator 220 starts count at the same time; and then stops after reaching a preset time cycle. The preset time cycle is a reference value of time constant. The voltage comparator 210 checks whether voltage V 24 is greater than voltage V 22 at the moment of stopping counting by the pulse comparator 220 . The result acquired by the voltage comparator 210 can be used to decide either increase or decrease the value of capacitor C 22 by the tuning loop 230 , as well as the charge time of capacitor C 22 . The tuning loop would repeat the aforementioned process to make the charge time of voltage V 22 on the capacitor C 22 equal the preset time cycle. Finally, the equivalent capacitance of tuning loop is equal the one of the capacitor C 22 .

In FIG. 2A , both the resistor R 22 and capacitor C 22 are grounded at one end respectively. However, it is not the situation in a practical filter circuit. Thus, the equivalent resistance and capacitance in the real filter circuit are different from the ones in FIG. 2A . Therefore, it is necessary to design one having the cut-off frequency of the tuning loop equal the real filter circuit under the accuracy requirement.

Accordingly, one of objects of the invention provides a frequency tuning loop which is operatable under a practical environment or real condition. It can compensate and prevent frequency shift caused by process or environment.

It is another object of the present invention to provide one or more variable resistors to tune the time constant of the filter circuit by changing the equivalent resistance.

It is yet another object of the present invention to provide a time constant comparison and tuning device, which determine whether the time constant of the filter circuit is equal to a preset time, and tune the equivalent resistance according to a compared result.

FIG. 1 is a schematic diagram illustrating a known tuning loop;

FIG. 2A is the typical circuit diagram of a tuning loop;

FIG. 2B shows the relationship between the input terminal voltages in the voltage comparator of the typical tuning loop;

FIG. 3A is one of the preferred embodiments illustrating the frequency tuning loop circuit in accordance with the present invention;

FIG. 3B is a schematic diagram illustrating the preset circle PSC; and

FIG. 4 is another preferred embodiment of the present invention.

The circuit structure of the present invention is described below, but not including the complete circuit structure of the frequency tuning loop for active resistive-capacitive filer. In order to describe the present invention more easy, the prior art introduced in the present invention are cited centrally. The related drawings in the below just for displaying the feature structure of the present invention are not drawn in proportion to the real cases.

FIG. 3A is one of the preferred embodiments illustrating the frequency tuning loop circuit in accordance with the present invention. A filter circuit, such as an active RC filter circuit, is composed of a dual-input/dual-output differential amplifier 310 , two feedback capacitors C 32 and two variable resistors R 32 . The variable resistors R 32 can be implemented by any prior art, for instance, by applying a resistor selective circuit consisting of the same cells of resistors and switches in parallel or series. In addition, a differential voltage comparator 320 is used to determine a value of output voltage and, while in the transition period of the output voltage (for example, form a high state to a low state), acquire a corresponding time constant from a comparing/adjusting signal device (such as a successive-approximation register, SAR). Then, a successive-approximation register 330 appropriately tunes the variable resistor R 32 in accordance with the comparison result between the time constant and the preset circle PSC.

The generation of the preset circle PSC is shown in FIG. 3B . When the time cycle of the external system time clock CLK is “T”, the enable duration of the preset circle PSC, as well as the disable duration thereof for resetting frequency tuning loop, is designed as a multiple of “T” and further in constant proportion to the preset time constant of a filter circuit. On the other hand, the preset circle PSC controls the on and off states of the switch devices S 32 shown in FIG. 3A . The switch device S 32 is off on condition that the preset circle (PSC) is enabling, or on, reversely.

In analysis of the frequency tuning loop in FIG. 3A , first, the currents provided by the constant current sources I 34 are 0, as well as ones in the opening state. At the moment, the feedback capacitors C 32 are charged only by the currents that are provided by the constant current sources I 32 and flow through the variable resistors R 32 . The frequency tuning loop starts to operate on condition that the preset circle PSC starts to enable at the moment of switch devices S 32 on the off state. According to the operation characters of the differential amplifier, the voltage difference between the non-inverting and inverting terminals is assumed 0, namely, it is on the state of virtual short between the non-inverting and inverting terminals, so as to generate two positive voltages V 32 , V 38 and two negative voltages V 34 , V 36 . For the symmetry on upper half and down half of the circuit, for instance the upper half circuit, the value of the voltage V 32 and the voltage V 36 are respectively:

V 32 =I 32 ×R 32

V 36 =( I 32 /C 32 )× t

wherein t is the duration after PSC is enabling. Accordingly, “t” is equal to the multiple of R 32 and C 32 when V 32 is equal to V 36 . That is, the time “t”, the time constant of the circuit, indicates the duration for charging from zero bridging voltage of the capacitor C 32 to a level equal to the one of the variable resistor R 32 . The time “t” on successive-approximation register 330 is acquired by transferring the output voltage of the differential voltage comparator 320 .

The voltage comparison in the differential voltage comparator 320 is implemented by a result through the operation: (V 38 −V 36 )−(V 32 −V 34 ). The result less than 0 volt indicates the bridging voltage of the capacitor C 32 is below the one of the resistor R 32 . At the moment, the voltage V 31 outputs a “0” level voltage potential, such as 0 volt. Reversely, the result more than 0 volt indicates the bridging voltage of the capacitor C 32 reaches to or over the one of the resistor R 32 . At the moment, the voltage V 31 outputs a “1” level voltage potential, such as 5 volts.

When the circuit persistently operates to the moment of the preset circle PSC is disabling, the successive-approximation register 330 judges dependent on the level of the voltage V 31 . The level “0” of the voltage V 31 indicates the current time constant of the circuit is more than the preset value. Thus, the level of the voltage V 32 is reduced with tuning the resistance of the variable resistor R 32 down. Furthermore, the charging time from the level of the capacitor C 32 to the level of the voltage V 32 is also shortened. On the contrary, the level “1” of the voltage V 31 indicates the current time constant of the circuit is less than the preset value. Thus, the level of the voltage V 32 is raised with tuning the resistance of the variable resistor R 32 up. Furthermore, the charging time from the level of the capacitor C 32 to the level of the voltage V 32 is also lengthened. At the same time, each switch device S 32 is also set “on” state to provide the capacitor C 32 a discharging route for resetting the current. It is noted that when switch device S 32 is “on”, the resistance is so low enough to be neglected for the sake of ensuring a low initial resistance derived from the product of the resistance and the current I 32 being generated on the capacitor C 32 . When the preset time cycle is enabled again, the frequency tuning loop will repeat the above-mentioned procedure again until the time constant of the circuit is completely coincided with or closely reaches to the enable duration of the preset circle PSC. At the moment, the equivalent resistance value of the main circuit on the filter can be regulated according to the result.

The trend for regulating the resistors may be dependent on either the constant charging time of a capacitor aforementioned or a variable one thereof. In an alternative embodiment with variable charging time, the capacitor C 32 has not stopped charging until the output voltage of the differential voltage comparator 320 reaching the transfer state, and then the system time clock CLK period responding to the charging time is acquired with the successive-approximation register 330 . When the system time clock CLK period is larger than the preset time constant, the resistance value should be tuned down, or tuned up reversely. In such a trend, the bigger error on the time constant results from the enable duration of the preset cycle PSC not only the integer multiple of the system time CLK period in application but also the definition of the so-called the constant time of the filer, when the frequency of the system CLK is not high enough. At this moment, if the constant current source I 34 is applied into the circuit and supposed to have a value in a proportion “a” to the value of the constant current source I 32 , such as half of the current value of the constant current source I 32 for current of the constant current source I 34 , the constant current source I 34 has a shunt effect for the constant current source I 32 . In other words, the current flowing through the capacitor C 32 is reduced, but the charging time of the capacitor C 32 is increased however. At the moment, the time constant becomes to:

I 32 ×R 32 =( a×I 32 /C 32 )× I

when a=0.5,

t= 2× R 32 ×C 32

From above, the larger the current value of the constant current source I 34 is, the longer the time t is necessary, such that the error caused form above-mentioned problems will be reduced. The controllable shunt devices of the circuit in the present invention could be consisted of one or more resistor ladder circuits, the series selective resistance circuits or the parallel selective resistance circuits. In the embodiment, the resistor ladder circuits are especially more suitable for implementing the circuit configuration of the active AC filter. However, the equivalent resistance in the controllable shunt device of the invention could be controlled by one or more digital control signals. FIG. 4 is another preferred embodiment of the present invention. The configuration of the 4-level R-R 2 resistance ladders basically includes the controllable shunt devices 410 and 420 in which the resistive value of the resistor R 44 is double of the one of the resistor R 42 , and the interior switch devices b 3 , b 2 , b 1 and b 0 control the flowing direction of the current, respectively. The currents are directed to the controllable shunt devices 410 and 420 by each switch device would be illustrated by the following paragraph.

Further, the R-2R resistance ladder is applied in the embodiment of the present invention. Its property and basic principle are well known and need not be described herein.

It could be known from the basic principle of the R-2R resistor ladder, after the current I 42 flows inwards the node 412 of the R-2R resistor ladder 410 , the current I 42 is divided equally into two currents I 42 /2, which one flows into the node 414 and the other into the switch device b 3 . On this account, there will be four currents I 42 /2, I 42 /4, I 42 /8 and I 42 /16 flowing respectively through the switch devices b 3 , b 2 , b 1 and b 0 . The on/off states of the switch devices b 3 , b 2 , b 1 and b 0 can be used individually to determine whether those currents charge the capacitor 42 . For example, when only the switch device b 3 is “on” and the others are “off”, the current I 42 /2 will charge the capacitor C 42 . But when the switch device b 1 is also “on”, the current (I 42 /2)+(I 42 /8) will charge the capacitor C 42 . Thus, the charging current will increase and the time constant will decrease naturally. Such that, the successive-approximation register 430 only directly control the switch devices b 3 , b 2 , b 1 and b 0 of the R-2R resistor ladder for the achievement on adjusting the time constant. Therefore, the time constant could be more fine-tuned with the character of the R-2R resistor ladder. Equivalently, this current configuration can control the charging current magnitude of the capacitor C 32 , which is known as a binary-weighted control relation from the indication of the current value in the drawings.

The above-mentions are only the preferred embodiments of the present invention, not intended to limit the scope thereof. It will be appreciated and carried out by those professions skilled in the art. Thus, many modifications of the embodiments which can be made without departing from the spirit of the present invention should be covered by the following claims.