Driver for a plasma display panel

This application claims the benefit, under 35 U.S.C. § 119 of French Patent Application 03/09749, filed Aug. 7, 2003.

The present invention relates to a driver for a plasma display panel.

Currently, there are plasma display panel (hereafter referred to as PDP) drivers whose elements are divided between two boards, the elements for controlling the sustain electrodes Ys of the display cells being disposed on a first board and the elements for controlling the address-sustain electrodes Yas of the display cells being disposed on a second board.

The object of the invention is to reduce the size of the current loops in the driver in order to reduce the electromagnetic emissions.

Referring to FIG. 1 a typical means for controlling the sustain electrodes Ys of the display cells are assembled on a first board B 1 . Two switches I 1 and I 2 are connected in series between a power supply terminal T 1 receiving the voltage Vs and a terminal T 2 connected to ground. The voltage Vs denotes the peak voltage of the sustain pulse signal to be applied to the sustain electrodes Ys and to the address-sustain electrodes Yas of the display cells. The intermediate point situated between the switches I 1 and I 2 is connected to a connector CNI accessing the electrodes Ys of the display cells. In addition, a power-supply and decoupling capacitor C 1 is connected across the terminals T 1 and T 2 .

In a same manner, the means for controlling the sustain electrodes Yas of the display cells are assembled on a second board B 2 . Two switches I 3 and I 4 are connected in series between a power supply terminal T 3 receiving the voltage Vs and a terminal T 4 connected to ground. The intermediate point situated between the switches I 3 and I 4 is connected to a connector CN 2 accessing the electrodes Yas of the display cells. In addition, a power-supply and decoupling capacitor C 2 is connected across the terminals T 3 and T 4 .

In the sustain phase, the switches I 1 and I 4 are firstly closed, then the switches I 2 and I 3 are closed. FIG. 2A shows the current loop present in the driver when the switches I 1 and I 4 are closed. The direction of the current in this loop is indicated by arrows. Similarly, FIG. 2B shows the loop of the current flowing in the driver when the switches I 2 and I 3 are closed.

In order to reduce the size of these current loops, one solution is to regroup the 2 parts of the driver onto a single board. This case is illustrated in FIG. 3 . In this second driver, an energy recovery circuit, well-known to those skilled in the art, has been provided. All the elements of the driven in FIG. 1 are thus mounted on a single board, apart from the power supply terminal T 3 and the ground terminal T 4 that are not shown. The current loop between the recovery circuit and the display electrodes Ys and Yas is illustrated in FIG. 4A . Similarly, the current loops when the switches I 1 and I 4 on the one hand, and the switches I 2 and I 3 on the other, are closed are show in FIGS. 4B and 4C . The size of these loops is reduced with respect to those of the driver in FIG. 1 , but they are still present even if the circuit is a hybrid circuit (with certain components being integrated).

The invention relates to a driver for a plasma display panel comprising a sustain circuit designed to deliver a first sustain pulse signal to the sustain electrodes of the cells of the said display and a second sustain pulse signal to the address-sustain electrodes of the display, the said sustain circuit comprising a first switch connected between a first connector accessing the sustain electrodes of the display cells and a power supply terminal receiving the peak voltage of the said first and second sustain pulse signals, a second switch connected between the said first access connector and ground, a third switch connected between a second connector accessing the address-sustain electrodes of the display cells and the said power supply terminal and a fourth switch connected between the said second access connector and ground, characterized in that it is mounted on a single board and in that the said first and fourth switches, and similarly the said second and third switches, are disposed next to one another in order to reduce the size of the current loops during the sustain of the display cells.

Advantageously, the said first and second access connectors are disposed at the periphery of the board, on the same edge next to one another in order to further reduce the size of the current loops.

According to a preferred embodiment, one of the access connectors is disposed on the kont face of the said board and the other on the back face. According to another embodiment, the said first and second access connectors are incorporated into a single connector.

The invention will be better understood upon reading the description that follows, presented as a non-limiting example and with reference to the appended figures, among which:

FIG. 1 , described above, shows a PDP driver of the prior art divided between 2 boards;

FIGS. 2A and 2B , described above, show the current loops in the circuit shown in FIG. 1 ;

FIG. 3 , described above, shows a mono-board driver of the prior art,

FIGS. 4A to 4C , described above, show the current loops in the circuit shown in FIG. 3 ;

FIGS. 5A and 5B respectively show front and cross-sectional views of a driver according to the invention;

FIGS. 6A to 6F show the current loops in the circuit shown in FIGS. 5A and 5B .

According to the invention, the position of the elements in the driver of the PDP is optimized in order to reduce the size of the loops in all three dimensions. FIG. 5A shows the driver of the invention in one plane (x,y) and FIG. 5B shows this same circuit in the plane (y, z).

In these figures, the switches I 1 and I 4 are positioned next to one another, at the same level on the x axis, so as to reduce the loop of the current flowing through them when closed. The same applies to the switches I 2 and I 3 in order to reduce the loop of the current flowing through them when closed.

Furthermore, the access connectors CN 1 and CN 2 are disposed, at the periphery of the board, next to one another on the same edge of the board, here on the left-hand edge of the board. Given that all the current loops pass through these two access connectors, this allows the size of these loops to be again reduced. In this preferred embodiment, the connector CN 1 is located on the front face of the board and the connector CN 2 is located, in the same position in the plane (x,y), on the back face. The track connecting the mid-point situated between the switches I 2 and I 3 to the connector CN 2 is therefore made on the back face of the board together with the track connecting this mid-point to the energy recovery circuit. All the other circuit components and tracks are mounted on the front face of the board and a screw is, for example, provided for linking the track on the back face with the components on the front face.

Accordingly, as can be seen from FIGS. 6A to 6F , the current loops are greatly reduced. FIGS. 6A and 6B show the current loop between the recovery circuit and the display electrodes Ys and Yas. FIGS. 6C and 6D show the loop of the current flowing through the switches I 1 and I 4 when these are closed. FIGS. 6E and 6F show the loop of the current flowing through the switches I 2 and I 3 when these are closed.

The size of the current loops in the z direction is greatly reduced and is essentially determined by the thickness of the board. In the plane (x,y), the size of the current loops is reduced if the switches I 1 and I 4 , and also I 2 and I 3 , are very close to one another and if they are disposed near to the access connectors CN 1 and CN 2 . It should be noted that, in this figure, two power supply terminals T 1 and T 4 and two ground terminals T 2 and T 3 are shown in order to simplify the circuit diagram. It is clear that the provision of only one power supply terminal and one ground terminal is possible with additional tracks being used to link the elements connected to the missing terminals to these two terminals.

This solution is valid for an integrated circuit design or for one with discrete components. Near-field measurements demonstrated that the electromagnetic emissions were reduced relative to conventional circuits.

As a variant, the use of a single connector in place of the connectors CN 1 and CN 2 may be envisaged. In this case, some of the pins of this connector would be assigned to the electrodes Ys and the others to the electrodes Yas.