On chip word line voltage with PVT tracking for memory embedded in logic process

The present disclosure relates generally to regulation of voltage for semiconductor devices.

Variances in process, temperature, and/or voltage may affect operational characteristics of the circuits fabricated by the processing. Prior art methods and circuits often use negative and positive temperature effect current sources to bias a detection circuit to ameliorate variances caused by process used, temperature, and/or voltage variations. This, however, often focuses only on temperature compensation and/or on voltage tracking. Often a bipolar device is used to generate a positive temperature effect current source.

In the described examples, the positive supply voltage is designated as supply voltage V DD and the ground supply voltage, having a nominal value of 0 Volts is designated as supply voltage V SS .

FIG. 1 is a representation of a prior art DRAM memory cell. The memory cell includes a p-channel access transistor 101 and a p-channel storage transistor 102 that is configured as a storage capacitor. The gate of the access transistor 101 is connected to word line 103 and the drain of the access transistor 101 is connected to the bit line 105 . The source of access transistor 101 is coupled to the source region of transistor 102 . The gate of transistor 102 is connected to receive a negative boosted bias voltage V BB . The Bias voltage V BB is limited by the break down voltage of the gate oxide of capacitor 102 and the highest voltage stored on the electrode. In general, bias voltage V BB is set to a voltage that is greater V 1 minus Vbd. In general V 1 is equal to the positive supply voltage V DD . N-well is biased to a boosted positive voltage V PP that is greater than the V DD supply voltage by a voltage that is approximately equal to the absolute value of the threshold voltage of p-channel access transistor 101 .

Certain voltage levels, e.g. V PP , need to be at desired levels in order for the circuit ( FIG. 1 , for example) to work correctly. V PP needs to be at a level that will turn off a transfer gate well, V BB needs to be deep enough to turn on transfer gates, and so on. However, at fast corner processing, for example, or at high temperature, threshold voltages may shrink, meaning a gate may be turned on with a shallower voltage V BB but may need a greater voltage V PP to turn off the gate. The inverse may be true at slow corner processing. Therefore, V PP often needs to track V DD variations, e.g. maintain a constant voltage differential.

Table 1 is an example of desired V PP and V BB levels for variation in operations, temperature vs. baseline conditions which reflect the events above.

A problem with the prior art is that the methods and circuits used to compensate for process-voltage-temperature (PVT) variations cannot reflect real world demands placed in word line voltage in the existence of process variations. For example, the prior art methods and circuits cannot work for a low voltage process because of the numerous components, e.g. two MOS transistors, a resistor, and a bipolar transistor connected in series between V DD and V SS voltage sources for positive temperature effect current source.

Further, often the prior art maintains voltages at set levels, e.g. V PP =V DD +|V TP | and V BB =V SS −|V TP |. If the threshold voltage V TP becomes small, such as from environmental changes, off-currents may increase due to a smaller turn off voltage operated in a leaky condition. FIGS. 2 through 4 are representative of prior art solutions.

FIG. 2 is a prior art V PP detection circuit which uses I NTE and I PTE current sources. FIGS. 3 a and 3 b are prior art current sources associated with prior art solutions, such as shown in FIGS. 2 and 4 . FIG. 3 a shows a prior art circuit for I NTE and FIG. 3 b shows a prior art circuit for I PTE where I NTE =|V TP |/R is negative and I PTE =kT/q×Ln(m) is positive. FIG. 4 is a prior art V BB detection circuit. These prior art solutions use negative and positive temperature effect currents sources to bias the detection circuit and only focus on temperature and voltage tracking and thus cannot reflect the real demand on word line voltage from process variations.

Therefore in order to obviate the deficiencies in the prior art, it is an object of the present disclosure to provide a circuit that provides desirables word line voltage levels V PP and V BB over P.V.T variations.

These objects and other advantages of the disclosed subject matter will be readily apparent to one skilled in the art to which the disclosure pertains from a perusal or the claims, the appended drawings, and the following detailed description of the preferred embodiments.

FIG. 1 is a schematic diagram of a prior art DRAM memory cell.

FIG. 2 is a schematic diagram of a prior art V PP detection circuit.

FIG. 3 a is a schematic diagram of a prior art I NTE current source.

FIG. 3 b is a schematic diagram of a prior art I PTE current source.

FIG. 4 is a schematic diagram of a prior art V BB detection circuit.

FIG. 5 is a schematic diagram of a V PP detection circuit according to an embodiment of the present disclosure.

FIG. 6 is a schematic diagram of a MOS sub-threshold current source according to an embodiment of the present disclosure.

FIG. 7 is a schematic diagram of a bias independent current source according to an embodiment of the present disclosure.

FIG. 8 is a schematic diagram of a V BB detection circuit according to an embodiment of the present disclosure.

FIG. 9 is a representative flow chart of a method for P.V.T compensation for a chip line voltage.

Referring now to FIG. 5 , in a preferred embodiment a circuit for providing a controlled voltage level may comprise PMOS transistor 501 coupled to voltage coupler 10 ; MOS sub-threshold current source 600 coupled to voltage coupler 20 ; and bias independent current source 700 coupled to MOS sub-threshold current source 600 and PMOS transistor 501 intermediate MOS sub-threshold current source 600 and PMOS transistor 501 .

Additionally, an inhibit coupler 800 may be provided intermediate to the bias independent source 700 and source 600 . In this embodiment, the voltage source coupled to voltage coupler 10 may be allowed to be compensated to rise in response to a rise in sub-threshold current I sbt . The voltage source to be compensated, e.g. V PP , may also be allowed to fall in response to a fall in sub-threshold current I sbt . Inhibit coupler 800 may be used to provide a reference signal to detect a value of the voltage at the voltage source to be compensated, e.g. V PP . For example, a high value at inhibit coupler 800 may be used to indicate that the voltage at the voltage source to be compensated has reached a desired value.

The gate of PMOS transistor 501 may be coupled to the drain of PMOS transistor 501 .

In a preferred embodiment, voltage coupler 10 may be adapted to be coupled to a source of V PP voltage and voltage coupler 20 may be adapted to be coupled to ground.

MOS sub-threshold current source 600 may further comprise a source of ppc current, I ppc . I ppc denotes the positive temperature current source of V PP and I bbc denotes the positive temperature current source for V BB . I ppc comprises two components, a bias independent current source I ref and a MOS saturation current source I sat , such that I ppc =C 1 I ref +C 2 I sat , where C 1 and C 2 are real numbers.

Referring now to FIG. 6 which is an embodiment of an MOS sub threshold current source 600 . MOS sub-threshold current source 600 may further comprise voltage coupler 12 ; a resistor 601 having a first terminal coupled to voltage coupler 12 and a second terminal; a bias independent current source 701 coupled to the second terminal of resistor 601 ; PMOS transistor 602 , the source of which is coupled to voltage coupler 12 and the gate of which is coupled to the second terminal of resistor 601 ; a bias independent current source 702 coupled to the drain of PMOS transistor 601 ; NMOS transistor 603 , the drain of which is coupled to the drain of PMOS transistor 602 and to the gate of NMOS transistor 603 and the source of which is coupled to voltage coupler 20 a ; and NMOS transistor 604 , the gate of which is coupled to the gate of NMOS transistor 603 , the source of which is coupled to voltage coupler 20 d , and the drain of which is coupled to a source of I ppc current.

In a preferred embodiment, voltage coupler 12 is adapted to couple to a source of V DD voltage and voltage couplers 20 a and 20 b are adapted to couple to ground.

Referring now to FIG. 7 , preferably, each bias independent current source 700 , e.g. 701 and 702 ( FIG. 6 ), further comprise voltage coupler 13 ; reference resistor 705 , comprising a first terminal coupled to voltage coupler 13 and a second terminal; PMOS transistor 710 , the source of which is coupled to the second terminal of reference resistor 705 ; PMOS transistor 712 , the gate of which is coupled to the gate of PMOS transistor 710 and to the drain of PMOS transistor 712 and the source of which is coupled to voltage coupler 13 ; NMOS transistor 711 , the drain and gate of which are coupled to the drain of PMOS transistor 710 and the source of which is coupled to voltage coupler 20 c ; and NMOS transistor 713 , the drain of which is coupled to the drain of PMOS transistor 712 , the gate of which is coupled to the gate of NMOS transistor 711 , and the source of which is coupled to voltage coupler 20 d.

Voltage coupler 13 may be coupled to a source of V DD voltage and voltage couplers 20 c and 20 d may be coupled to ground.

Bias independent current source 700 may further comprise first coupling terminal VDD and a second coupling terminal. First coupling terminal may be coupled to the drain of PMOS transistor 501 and the second coupling terminal may be coupled to the MOS sub-threshold current source.

Referring now to FIG. 8 , which is an embodiment of a V BB detection circuit. The V BB detection circuit may comprise first voltage source (not shown in the figure), comprising a first terminal, coupled to the first voltage source at voltage coupler 14 , and a second terminal; bias independent current source 700 , comprising a first terminal coupled to the second terminal of the current source I bbc and a second terminal; and PMOS transistor 801 , the source of which is coupled to the second terminal of bias independent current source 700 , the gate of which is coupled to the drain, and the drain of which is coupled to voltage source 15 . I bbc is a combination of I ref and I sat such that I bbc =D 1 I ref +D 2 I sat , where D 1 and D 2 are real numbers that can be selected.

First voltage source may be a source of V DD voltage and voltage source 15 may be coupled to a source of V BB voltage.

In the operation of an exemplary embodiment, referring to FIG. 9 , on chip line voltage with adequate process-voltage-temperature (PVT) compensation may be provided by providing transistor 501 ( FIG. 5 ) configured in a diode-connected state, step 900 ; coupling transistor 501 to voltage source 10 ( FIG. 5 ) which will be compensated, step 910 ; providing bias independent source 700 ( FIG. 5 ) which will provide a reference current I REF , step 920 ; coupling bias independent source 700 to transistor 501 , step 930 ; providing source 600 of a sub-threshold current I sbt , step 940 , where source 600 comprises bias independent source 701 ( FIG. 6 ) of reference current I REF and transistor 602 ( FIG. 6 ) adapted to be driven into a saturation state; coupling source 600 to bias independent source 700 , step 950 ; and allowing a change in the sub-threshold current I sbt in response to a change in threshold voltage, step 960 .

In this method, decreasing threshold voltage results in an increase in the current I sbt and increasing threshold voltage results in a decrease in the sub threshold current I sbt .

An aspect of the present disclosure is a circuit that generates desirable word line voltage levels for varied environment of process, voltage and temperature variations. This allows the word line voltage levels to be responsive to more than just temperature.

Another aspect of the present disclosure is the generation of environmentally independent and insensitive V PP and V BB voltage levels by selection of the coefficients C 1 , C 2 and D 1 and D 2 respectively. The lower the Coefficients C 2 and D 2 the more insensitive V PP and V BB are to environmental variations. Conversely the greater the coefficients C 2 and D 2 the more sensitive V PP and V BB become to environmental variations.

Still another aspect of the present disclosure is that it may be implement in any kind of process including low voltage processes and is a simple circuit that is easy to implement.

It will be understood that various changes in the details, materials, and arrangements of the parts which have been described and illustrated above in order to explain the nature of this present disclosure may be made by those skilled in the art without departing from the principle and scope of the present disclosure as recited in the appended claims.